static void tnetw1130_write1w(tnetw1130_t *s, hwaddr addr,
uint16_t value)
{
assert(addr < TNETW1130_MEM1_SIZE);
reg_write16(s->mem1, addr, value);
TRACE(TNETW, logout("addr %s = 0x%04x\n", tnetw1130_regname1(addr), value));
}
static void tnetw1130_write1w(pci_tnetw1130_t * d, target_phys_addr_t addr,
uint16_t value)
{
tnetw1130_t *s = &d->tnetw1130;
assert(addr < TNETW1130_MEM1_SIZE);
reg_write16(s->mem1, addr, value);
TRACE(TNETW, logout("addr %s = 0x%04x\n", tnetw1130_regname1(addr), value));
}
static void tnetw1130_cmd(tnetw1130_t *s)
{
uint16_t cmd = reg_read16(s->mem1, CMD_MAILBOX);
s->irq_status |= HOST_INT_CMD_COMPLETE;
reg_write16(s->mem1, CMD_MAILBOX + 2, 0x0001);
switch (cmd) {
case ACX1xx_CMD_RESET: /* 0x00 */
tnetw1130_cmd_reset(s);
break;
case ACX1xx_CMD_INTERROGATE: /* 0x01 */
tnetw1130_cmd_interrogate(s);
break;
case ACX1xx_CMD_CONFIGURE: /* 0x02 */
case ACX1xx_CMD_CONFIG_TIM: /* 0x0a */
case ACX1xx_CMD_CONFIG_BEACON: /* 0x13 */
case ACX1xx_CMD_CONFIG_PROBE_RESPONSE: /* 0x14 */
case ACX1xx_CMD_CONFIG_NULL_DATA: /* 0x15 */
case ACX1xx_CMD_CONFIG_PROBE_REQUEST: /* 0x16 */
break;
}
}
static void tnetw1130_write0w(pci_tnetw1130_t * d, target_phys_addr_t addr,
uint16_t value)
{
tnetw1130_t *s = &d->tnetw1130;
if (addr < TNETW1130_MEM0_SIZE) {
reg_write16(s->mem0, addr, value);
} else {
UNEXPECTED();
}
if (addr == TNETW1130_SOFT_RESET) {
if (value & 1) {
TRACE(TNETW, logout("soft reset\n"));
}
} else if (addr == TNETW1130_INT_TRIG) {
if (value == 1) {
TRACE(TNETW, logout("trigger interrupt, status, cmd = %s\n",
tnetw1130_cmdname(reg_read16(s->mem1, CMD_MAILBOX))));
tnetw1130_cmd(s);
} else {
UNEXPECTED();
}
} else if (addr == TNETW1130_IRQ_ACK) {
/* !!! must reset irq */
s->irq_status &= ~value;
} else if (addr == TNETW1130_EE_START) {
if (value & 1) {
TRACE(TNETW, logout("start burst read from EEPROM\n"));
}
} else if (addr == TNETW1130_ECPU_CTRL) {
if (value & 1) {
TRACE(TNETW, logout("halt eCPU\n"));
//~ reg_write16(s->mem0, addr, value & ~1);
} else {
TRACE(TNETW, logout("start eCPU\n"));
s->irq_status |= HOST_INT_FCS_THRESHOLD;
}
}
TRACE(TNETW, logout("addr %s = 0x%04x\n", tnetw1130_regname(addr), value));
}
static int vlynq_tnetw1130_init(VLYNQDevice* vlynq_dev)
{
vlynq_tnetw1130_t *d = DO_UPCAST(vlynq_tnetw1130_t, dev, vlynq_dev);
//~ uint8_t *pci_conf = d->dev.config;
tnetw1130_t *s = &d->tnetw1130;
#if defined(DEBUG_TNETW1130)
set_traceflags("DEBUG_AR7");
#endif
TRACE(TNETW, logout("\n"));
/* TI TNETW1130 */
//~ tnetw1130_pci_config(pci_conf);
/* Handler for memory-mapped I/O */
// TODO: Code is missing.
logout("vlynq i/o is missing\n");
//~ s->io_memory[0] =
//~ cpu_register_io_memory(tnetw1130_region0_read, tnetw1130_region0_write,
//~ d, DEVICE_NATIVE_ENDIAN);
//~ s->io_memory[1] =
//~ cpu_register_io_memory(tnetw1130_region1_read, tnetw1130_region1_write,
//~ d, DEVICE_NATIVE_ENDIAN);
TRACE(TNETW, logout("io_memory = 0x%08x, 0x%08x\n", s->io_memory[0], s->io_memory[1]));
//~ memcpy(s->mem1 + 0x0001f000, pci_conf, 64);
/* eCPU is halted. */
reg_write16(s->mem0, TNETW1130_ECPU_CTRL, 1);
//~ tnetw1130_mem_map(&d->dev, 0, 0x04000000, 0x22000, 0); /* 0xf0000000 */
//~ tnetw1130_mem_map(&d->dev, 1, 0x04022000, 0x40000, 0); /* 0xc0000000 */
//~ tnetw1130_mem_map(&d->dev, 1, 0x04000000, 0x40000, 0);
//~ tnetw1130_mem_map(&d->dev, 0, 0x04040000, 0x22000, 0);
tnetw1130_mem_map(&d->dev, 0, 0x04000000, TNETW1130_MEM0_SIZE, 0);
tnetw1130_mem_map(&d->dev, 1, 0x04022000, TNETW1130_MEM1_SIZE, 0);
return 0;
}
void vlynq_tnetw1130_init(void)
{
pci_tnetw1130_t *d = &vlynq;
uint8_t *pci_conf = d->dev.config;
tnetw1130_t *s = &d->tnetw1130;
#if defined(DEBUG_TNETW1130)
set_traceflags("DEBUG_AR7");
#endif
TRACE(TNETW, logout("\n"));
/* TI TNETW1130 */
tnetw1130_pci_config(pci_conf);
/* Handler for memory-mapped I/O */
s->io_memory[0] =
cpu_register_io_memory(0, tnetw1130_region0_read, tnetw1130_region0_write, d);
s->io_memory[1] =
cpu_register_io_memory(0, tnetw1130_region1_read, tnetw1130_region1_write, d);
TRACE(TNETW, logout("io_memory = 0x%08x, 0x%08x\n", s->io_memory[0], s->io_memory[1]));
pci_register_io_region(&d->dev, 0, TNETW1130_MEM0_SIZE,
PCI_ADDRESS_SPACE_MEM, tnetw1130_mem_map);
pci_register_io_region(&d->dev, 1, TNETW1130_MEM1_SIZE,
PCI_ADDRESS_SPACE_MEM, tnetw1130_mem_map);
memcpy(s->mem1 + 0x0001f000, pci_conf, 64);
/* eCPU is halted. */
reg_write16(s->mem0, TNETW1130_ECPU_CTRL, 1);
//~ tnetw1130_mem_map(&d->dev, 0, 0x04000000, 0x22000, 0); /* 0xf0000000 */
//~ tnetw1130_mem_map(&d->dev, 1, 0x04022000, 0x40000, 0); /* 0xc0000000 */
//~ tnetw1130_mem_map(&d->dev, 1, 0x04000000, 0x40000, 0);
//~ tnetw1130_mem_map(&d->dev, 0, 0x04040000, 0x22000, 0);
tnetw1130_mem_map(&d->dev, 0, 0x04000000, TNETW1130_MEM0_SIZE, 0);
tnetw1130_mem_map(&d->dev, 1, 0x04022000, TNETW1130_MEM1_SIZE, 0);
}
static void
tda998x_encoder_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
u16 ref_pix, ref_line, n_pix, n_line;
u16 hs_pix_s, hs_pix_e;
u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
u16 vwin1_line_s, vwin1_line_e;
u16 vwin2_line_s, vwin2_line_e;
u16 de_pix_s, de_pix_e;
u8 reg, div, rep;
/*
* Internally TDA998x is using ITU-R BT.656 style sync but
* we get VESA style sync. TDA998x is using a reference pixel
* relative to ITU to sync to the input frame and for output
* sync generation. Currently, we are using reference detection
* from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
* which is position of rising VS with coincident rising HS.
*
* Now there is some issues to take care of:
* - HDMI data islands require sync-before-active
* - TDA998x register values must be > 0 to be enabled
* - REFLINE needs an additional offset of +1
* - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
*
* So we add +1 to all horizontal and vertical register values,
* plus an additional +3 for REFPIX as we are using RGB input only.
*/
n_pix = mode->htotal;
n_line = mode->vtotal;
hs_pix_e = mode->hsync_end - mode->hdisplay;
hs_pix_s = mode->hsync_start - mode->hdisplay;
de_pix_e = mode->htotal;
de_pix_s = mode->htotal - mode->hdisplay;
ref_pix = 3 + hs_pix_s;
/*
* Attached LCD controllers may generate broken sync. Allow
* those to adjust the position of the rising VS edge by adding
* HSKEW to ref_pix.
*/
if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
ref_pix += adjusted_mode->hskew;
if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
ref_line = 1 + mode->vsync_start - mode->vdisplay;
vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
vwin1_line_e = vwin1_line_s + mode->vdisplay;
vs1_pix_s = vs1_pix_e = hs_pix_s;
vs1_line_s = mode->vsync_start - mode->vdisplay;
vs1_line_e = vs1_line_s +
mode->vsync_end - mode->vsync_start;
vwin2_line_s = vwin2_line_e = 0;
vs2_pix_s = vs2_pix_e = 0;
vs2_line_s = vs2_line_e = 0;
} else {
ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
vs1_pix_s = vs1_pix_e = hs_pix_s;
vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
vs1_line_e = vs1_line_s +
(mode->vsync_end - mode->vsync_start)/2;
vwin2_line_s = vwin1_line_s + mode->vtotal/2;
vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
vs2_line_s = vs1_line_s + mode->vtotal/2 ;
vs2_line_e = vs2_line_s +
(mode->vsync_end - mode->vsync_start)/2;
}
div = 148500 / mode->clock;
if (div != 0) {
div--;
if (div > 3)
div = 3;
}
/* mute the audio FIFO: */
reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
/* set HDMI HDCP mode off: */
reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
reg_clear(priv, REG_TX33, TX33_HDMI);
reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
/* no pre-filter or interpolator: */
reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
HVF_CNTRL_0_INTPOL(0));
reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
VIP_CNTRL_4_BLC(0));
reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
PLL_SERIAL_3_SRL_DE);
reg_write(priv, REG_SERIALIZER, 0);
reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
/* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
rep = 0;
reg_write(priv, REG_RPT_CNTRL, 0);
reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
PLL_SERIAL_2_SRL_PR(rep));
/* set color matrix bypass flag: */
reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
MAT_CONTRL_MAT_SC(1));
/* set BIAS tmds value: */
reg_write(priv, REG_ANA_GENERAL, 0x09);
/*
* Sync on rising HSYNC/VSYNC
*/
reg = VIP_CNTRL_3_SYNC_HS;
/*
* TDA19988 requires high-active sync at input stage,
* so invert low-active sync provided by master encoder here
*/
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
reg |= VIP_CNTRL_3_H_TGL;
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
reg |= VIP_CNTRL_3_V_TGL;
reg_write(priv, REG_VIP_CNTRL_3, reg);
reg_write(priv, REG_VIDFORMAT, 0x00);
reg_write16(priv, REG_REFPIX_MSB, ref_pix);
reg_write16(priv, REG_REFLINE_MSB, ref_line);
reg_write16(priv, REG_NPIX_MSB, n_pix);
reg_write16(priv, REG_NLINE_MSB, n_line);
reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
reg_write16(priv, REG_DE_START_MSB, de_pix_s);
reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
if (priv->rev == TDA19988) {
/* let incoming pixels fill the active space (if any) */
reg_write(priv, REG_ENABLE_SPACE, 0x00);
}
/*
* Always generate sync polarity relative to input sync and
* revert input stage toggled sync at output stage
*/
reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
reg |= TBG_CNTRL_1_H_TGL;
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
reg |= TBG_CNTRL_1_V_TGL;
reg_write(priv, REG_TBG_CNTRL_1, reg);
/* must be last register set: */
reg_write(priv, REG_TBG_CNTRL_0, 0);
/* Only setup the info frames if the sink is HDMI */
if (priv->is_hdmi_sink) {
/* We need to turn HDMI HDCP stuff on to get audio through */
reg &= ~TBG_CNTRL_1_DWIN_DIS;
reg_write(priv, REG_TBG_CNTRL_1, reg);
reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
reg_set(priv, REG_TX33, TX33_HDMI);
tda998x_write_avi(priv, adjusted_mode);
if (priv->params.audio_cfg)
tda998x_configure_audio(priv, adjusted_mode,
&priv->params);
}
}
