int MTK_SPC_Init(void* dev) { SPCMSG("MTK_SPC_init() \n"); mt65xx_reg_sync_writel(readl(DEVAPC0_APC_CON) & (0xFFFFFFFF ^ (1<<2)), DEVAPC0_APC_CON); mt65xx_reg_sync_writel(readl(DEVAPC3_APC_CON) & (0xFFFFFFFF ^ (1<<2)), DEVAPC3_APC_CON); mt65xx_reg_sync_writel(readl(DEVAPC0_PD_APC_CON) & (0xFFFFFFFF ^ (1<<2)), DEVAPC0_PD_APC_CON); mt65xx_reg_sync_writel(readl(DEVAPC3_PD_APC_CON) & (0xFFFFFFFF ^ (1<<2)), DEVAPC3_PD_APC_CON); mt65xx_reg_sync_writel(0x0000007F, DEVAPC0_DXS_VIO_STA); //writel(0x00FF00FB, AP_DEVAPC0_DXS_VIO_MASK); // 0xfb:MM, 0xfd:EMI, 0xf9:Both mt65xx_reg_sync_writel(readl(DEVAPC0_DXS_VIO_MASK)&(~0x8), DEVAPC0_DXS_VIO_MASK); // 0xfb:MM, 0xfd:EMI, 0xf9:Both mt65xx_reg_sync_writel(readl(DEVAPC3_D0_VIO_STA) | ABORT_SMI , DEVAPC3_D0_VIO_STA); mt65xx_reg_sync_writel(readl(DEVAPC3_D0_VIO_MASK) & ~ABORT_SMI , DEVAPC3_D0_VIO_MASK); spc_register_isr(dev); #ifdef CONFIG_MTK_HIBERNATION register_swsusp_restore_noirq_func(ID_M_SPC, spc_pm_restore_noirq, NULL); #endif return 0; }
INT32 mtk_wcn_consys_hw_init() { INT32 iRet = -1; UINT32 addrPhy = 0; /*set MPU for EMI share Memory*/ WMT_PLAT_INFO_FUNC("setting MPU for EMI share memory\n"); emi_mpu_set_region_protection(gConEmiPhyBase + SZ_1M/2, gConEmiPhyBase + SZ_1M, 5, SET_ACCESS_PERMISSON(FORBIDDEN,NO_PROTECTION,FORBIDDEN,NO_PROTECTION)); WMT_PLAT_INFO_FUNC("get consys start phy address(0x%x)\n",gConEmiPhyBase); /*consys to ap emi remapping register:10001310, cal remapping address*/ addrPhy = (gConEmiPhyBase & 0xFFF00000) >> 20; /*enable consys to ap emi remapping bit12*/ addrPhy = addrPhy | 0x1000; CONSYS_REG_WRITE(CONSYS_EMI_MAPPING,CONSYS_REG_READ(CONSYS_EMI_MAPPING) | addrPhy); WMT_PLAT_INFO_FUNC("CONSYS_EMI_MAPPING dump(0x%08x)\n",CONSYS_REG_READ(CONSYS_EMI_MAPPING)); #if 1 pEmibaseaddr = ioremap_nocache(gConEmiPhyBase + CONSYS_EMI_AP_PHY_OFFSET,CONSYS_EMI_MEM_SIZE); #else pEmibaseaddr = ioremap_nocache(CONSYS_EMI_AP_PHY_BASE,CONSYS_EMI_MEM_SIZE); #endif //pEmibaseaddr = ioremap_nocache(0x80090400,270*KBYTE); if(pEmibaseaddr) { WMT_PLAT_INFO_FUNC("EMI mapping OK(0x%p)\n",pEmibaseaddr); memset(pEmibaseaddr,0,CONSYS_EMI_MEM_SIZE); iRet = 0; }else{ WMT_PLAT_ERR_FUNC("EMI mapping fail\n"); } WMT_PLAT_INFO_FUNC("register connsys restore cb for complying with IPOH function\n"); register_swsusp_restore_noirq_func(ID_M_CONNSYS,mtk_wcn_consys_hw_restore,NULL); return iRet; }
static int devapc_probe(struct platform_device *dev) { int ret; pr_warn("[DEVAPC] module probe. \n"); /*IO remap*/ devapc_ioremap(); /* * Interrupts of violation (including SPC in SMI, or EMI MPU) are triggered by the device APC. * need to share the interrupt with the SPC driver. */ ret = request_irq(devapc_irq, (irq_handler_t)devapc_violation_irq, IRQF_TRIGGER_LOW | IRQF_SHARED, "devapc", &g_devapc_ctrl); if (ret) { pr_warn("[DEVAPC] Failed to request irq! (%d)\n", ret); return ret; } #ifdef CONFIG_MTK_HIBERNATION register_swsusp_restore_noirq_func(ID_M_DEVAPC, devapc_pm_restore_noirq, NULL); #endif start_devapc(); return 0; }