Exemplo n.º 1
0
void BLE_SLP_Handler(void)
//void BLE_SLP_Handler_func(void)
{
	ble_regs_pop();
//	smpc_regs_pop();
    

//	SetBits16(SYS_CTRL_REG, DEBUGGER_ENABLE, 0);   

	SetBits16(GP_CONTROL_REG, BLE_WAKEUP_REQ, 0);   //just to be sure    

    if((jump_table_struct[0] == TASK_GTL) || (BLE_INTEGRATED_HOST_GTL == 1 ))
	{
		// UART and pads have already been activated by periph_init() which is called
		// at initialization by main_func() and during wakeup by BLE_WAKEUP_LP_Handler().
		
		gtl_eif_init();
	}

	SetBits32(BLE_INTACK_REG, SLPINTACK, 1);

#if DEEP_SLEEP //Needed only for compilation. Remove when ROM code is ready.
#if RW_BLE_SUPPORT
	rwip_wakeup();
#endif //RW_BLE_SUPPORT
#endif //DEEP_SLEEP
    
	/*
	* Radio Subsystem initialization. Execute here after making sure that BLE core is awake.
	*/
	rf_workaround_init();
	rf_reinit();	

    if (lp_clk_sel == LP_CLK_RCX20)
        calibrate_rcx20(20);
    
    rwble_last_event = BLE_EVT_SLP;
    
}
Exemplo n.º 2
0
/*
 * LOCAL FUNCTIONS DEFINITIONS
 ****************************************************************************************
 */
 
 
// ============================================================================================
// ==================== DEEP SLEEP PATCH - THIS CODE MUST STAY IN RAM =========================
// ============================================================================================
extern void rf_workaround_init(void);
extern void rf_reinit(void);

// /*********************************************************************************
//  *** WAKEUP_LP_INT ISR
//  ***/
void BLE_WAKEUP_LP_Handler(void)
{    
	volatile long t=0;

#if !(USE_WDOG)
    SetWord16(SET_FREEZE_REG, FRZ_WDOG); //Prepare WDOG, i.e. stop
#endif
     
//    // Gives 1dB higher sensitivity - UNTESTED
//    if (GetBits16(ANA_STATUS_REG, BOOST_SELECTED) == 0x1) 
//    { 
//        // Boost-mode
//        SetBits16(DCDC_CTRL2_REG, DCDC_CUR_LIM, 0x8); // 80mA
//    }
//    else 
//    { 
//        // Buck-mode
//        SetBits16(DCDC_CTRL2_REG, DCDC_CUR_LIM, 0x4); // 40mA
//    }
    
	/*
	* Wait and Switch to XTAL 16MHz
	* (default after each wake-up is RC 16MHz, but XTAL initialization sequence has been already initiated by PMU)
	* NOTE: 
	*       1. If app does not need XTAL16MHz but RC16MHz is enough then skip this section!
	*       2. Wait-loop BEFORE activating PERIPH_PD in order to save some power...
	*/
    // It will save some power if you lower the clock while waiting for XTAL16 to settle.
	// Could also switch to 32KHz, but then processing power is dramatically reduced (e.g. patching() routine may be too slow).
    SetBits16(CLK_AMBA_REG, PCLK_DIV, 3);  // lowest is 2MHz (div 8, source is RC @16MHz)
    SetBits16(CLK_AMBA_REG, HCLK_DIV, 3);

    while ( !GetBits16(SYS_STAT_REG, XTAL16_SETTLED) )  // this takes some mili seconds
        __NOP(), __NOP(), __NOP();  // reduce some APB activity

    SetBits16(CLK_CTRL_REG, SYS_CLK_SEL, 0); // select XTAL 16MHz
    SetBits16(CLK_16M_REG, RC16M_ENABLE, 0); // save power from RC 16MHz
    
    // and restore clock rates (refer to a couple of lines above)
    SetBits16(CLK_AMBA_REG, PCLK_DIV, 0);
    SetBits16(CLK_AMBA_REG, HCLK_DIV, 0);
    /*
	* Init System Power Domain blocks: GPIO, WD Timer, Sys Timer, etc.
	* Power up and init Peripheral Power Domain blocks,
	* and finally release the pad latches.
	*/
	
    periph_init();

    
	/*
	* Since XTAL 16MHz is activated, power-up the Radio Subsystem (including BLE)
	*
	* Note that BLE core clock is masked in order to handle the case where RADIO_PD does not get into power down state.
	* The BLE clock should be active only as long as system is running at XTAL 16MHz (not at RC16 or 32KHz).
	* Also BLE clock should be enabled before powering up the RADIO Power Domain !
	*/
	SetBits16(CLK_RADIO_REG, BLE_ENABLE, 1); // BLE clock enable
	SetBits16(PMU_CTRL_REG, RADIO_SLEEP, 0); // Power up! Note: System must run at 16MHz when powering up RADIO_PD.
	while (!(GetWord16(SYS_STAT_REG) & RAD_IS_UP)) ; // this may take up to 1/2 of the 32KHz clock period


	/* 
	* Wait for at least one Low Power clock edge after the power up of the Radio Power Domain *e.g. with ble_wait_lp_clk_posedge() )
	* or even better check the BLE_CNTL2_REG[WAKEUPLPSTAT] !
	* Thus you assure that BLE_WAKEUP_LP_IRQ is deasserted and BLE_SLP_IRQ is asserted.
	* After this check exit this ISE in order to proceed with BLE_SLP_Handler().
	*/
	while ( GetBits32(BLE_CNTL2_REG, WAKEUPLPSTAT) || !GetBits32(BLE_INTSTAT_REG, SLPINTSTAT))
		if (t) break;

	// Now BLE_WAKEUP_LP_IRQ is deasserted and BLE_SLP_IRQ is asserted, so exit in order to proceed with BLE_SLP_Handler().
	// NOTE: If returning from BLE_WAKEUP_LP_Handler() will not cause BLE_SLP_Handler() to start, 
	//       but the code after __WFI() is executed, then THERE WAS A SW SETUP PROBLEM !!! 
	//			 so it is recommended to place a check after __WFI().
	
	/*
	* Radio Subsystem initialization. Execute here after making sure that BLE core is awake.
	*/
	rf_workaround_init();
	rf_reinit();	
}