Exemplo n.º 1
0
int8_t tdma_init (uint8_t mode, uint8_t chan, uint16_t my_mac)
{
  tx_reserve = -1;
  tdma_rx_failure_cnt = 0;
  tdma_mode = mode;
  tdma_tx_slots = 0;

  sync_status=0;

  tdma_slots_per_cycle = TDMA_DEFAULT_SLOTS_PER_CYCLE;


  tdma_rx_pkt_signal = nrk_signal_create ();
  if (tdma_rx_pkt_signal == NRK_ERROR) {
    nrk_kprintf (PSTR ("TDMA ERROR: creating rx signal failed\r\n"));
    nrk_kernel_error_add (NRK_SIGNAL_CREATE_ERROR, nrk_cur_task_TCB->task_ID);
    return NRK_ERROR;
  }
  tdma_tx_pkt_done_signal = nrk_signal_create ();
  if (tdma_tx_pkt_done_signal == NRK_ERROR) {
    nrk_kprintf (PSTR ("TDMA ERROR: creating tx signal failed\r\n"));
    nrk_kernel_error_add (NRK_SIGNAL_CREATE_ERROR, nrk_cur_task_TCB->task_ID);
    return NRK_ERROR;
  }
  tdma_enable_signal = nrk_signal_create ();
  if (tdma_enable_signal == NRK_ERROR) {
    nrk_kprintf (PSTR ("TDMA ERROR: creating enable signal failed\r\n"));
    nrk_kernel_error_add (NRK_SIGNAL_CREATE_ERROR, nrk_cur_task_TCB->task_ID);
    return NRK_ERROR;
  }


  // Set the one main rx buffer
  tdma_rx_pkt_set_buffer (tdma_rx_buf, TDMA_MAX_PKT_SIZE);
  tdma_rx_buf_empty = 1;
  tx_data_ready = 0;


  // Setup the radio 
  rf_init (&tdma_rfRxInfo, chan, 0xffff, my_mac);
  tdma_chan = chan;
  tdma_my_mac = my_mac;

  //FASTSPI_SETREG (CC2420_RSSI, 0xE580); // CCA THR=-25
  //FASTSPI_SETREG (CC2420_TXCTRL, 0x80FF);       // TX TURNAROUND = 128 us
  //FASTSPI_SETREG (CC2420_RXCTRL1, 0x0A56);
  // default cca thresh of -45
  rf_set_cca_thresh (-45);

  asm volatile ("":::"memory");
  tdma_running = 1;
  tdma_is_enabled = 1;
  return NRK_OK;
}
Exemplo n.º 2
0
int8_t bmac_init (uint8_t chan)
{
    bmac_running=0;
    tx_reserve=-1;
    cca_active=true;
    rx_failure_cnt=0;
	
#ifdef NRK_SW_WDT
#ifdef BMAC_SW_WDT_ID

    _bmac_check_period.secs=30;
    _bmac_check_period.nano_secs=0;
    nrk_sw_wdt_init(BMAC_SW_WDT_ID, &_bmac_check_period, NULL );
    nrk_sw_wdt_start(BMAC_SW_WDT_ID);
#endif
#endif



    _bmac_check_period.secs=0;
    _bmac_check_period.nano_secs=BMAC_DEFAULT_CHECK_RATE_MS*NANOS_PER_MS;
	
	// SIGNAL
/*  bmac_rx_pkt_signal=nrk_signal_create();
    if(bmac_rx_pkt_signal==NRK_ERROR)
    {
        printf("BMAC ERROR: creating rx signal failed\r\n");
       // nrk_kernel_error_add(NRK_SIGNAL_CREATE_ERROR,nrk_cur_task_TCB->task_ID); // commented out by madhur: error implementation has not been checked yet
        return NRK_ERROR;
    }
*/    bmac_tx_pkt_done_signal=nrk_signal_create();
    if(bmac_tx_pkt_done_signal==NRK_ERROR)
    {
        printf("BMAC ERROR: creating tx signal failed\r\n");
        //nrk_kernel_error_add(NRK_SIGNAL_CREATE_ERROR,nrk_cur_task_TCB->task_ID);
        return NRK_ERROR;
    }
    bmac_enable_signal=nrk_signal_create();
    if(bmac_enable_signal==NRK_ERROR)
    {
        printf("BMAC ERROR: creating enable signal failed\r\n");
       // nrk_kernel_error_add(NRK_SIGNAL_CREATE_ERROR,nrk_cur_task_TCB->task_ID);
        return NRK_ERROR;
    }
	

    tx_data_ready=0;
		
    // Set the one main rx buffer
    rx_buf_empty=0;
    bmac_rfRxInfo.pPayload = NULL;
    bmac_rfRxInfo.max_length = 0;

    // Setup the MRF24J40 chip
    rf_init (&bmac_rfRxInfo, chan, 0xffff, 0);
    g_chan=chan;

		/*
    FASTSPI_SETREG(CC2420_RSSI, 0xE580); // CCA THR=-25
    FASTSPI_SETREG(CC2420_TXCTRL, 0x80FF); // TX TURNAROUND = 128 us
    FASTSPI_SETREG(CC2420_RXCTRL1, 0x0A56);
    */
		
		// default cca thresh of -45
    //rf_set_cca_thresh(-45);
    rf_set_cca_thresh(-45);
		
		// Disable checking address field
		rf_addr_decode_disable();
		
    bmac_running=1;
    is_enabled=1;
    return NRK_OK;
}
Exemplo n.º 3
0
int8_t bmac_set_cca_thresh(int8_t thresh)
{
    rf_set_cca_thresh(thresh);
    return NRK_OK;
}
Exemplo n.º 4
0
int8_t bmac_init (uint8_t chan)
{
  bmac_running = 0;
  tx_reserve = -1;
  cca_active = true;
  rx_failure_cnt = 0;
#ifdef NRK_SW_WDT
#ifdef BMAC_SW_WDT_ID

  _bmac_check_period.secs = 30;
  _bmac_check_period.nano_secs = 0;
  nrk_sw_wdt_init (BMAC_SW_WDT_ID, &_bmac_check_period, NULL);
  nrk_sw_wdt_start (BMAC_SW_WDT_ID);
#endif
#endif



  _bmac_check_period.secs = 0;
  _bmac_check_period.nano_secs = BMAC_DEFAULT_CHECK_RATE_MS * NANOS_PER_MS;
  bmac_rx_pkt_signal = nrk_signal_create ();
  if (bmac_rx_pkt_signal == NRK_ERROR) {
    nrk_kprintf (PSTR ("BMAC ERROR: creating rx signal failed\r\n"));
    nrk_kernel_error_add (NRK_SIGNAL_CREATE_ERROR, nrk_cur_task_TCB->task_ID);
    return NRK_ERROR;
  }
  bmac_tx_pkt_done_signal = nrk_signal_create ();
  if (bmac_tx_pkt_done_signal == NRK_ERROR) {
    nrk_kprintf (PSTR ("BMAC ERROR: creating tx signal failed\r\n"));
    nrk_kernel_error_add (NRK_SIGNAL_CREATE_ERROR, nrk_cur_task_TCB->task_ID);
    return NRK_ERROR;
  }
  bmac_enable_signal = nrk_signal_create ();
  if (bmac_enable_signal == NRK_ERROR) {
    nrk_kprintf (PSTR ("BMAC ERROR: creating enable signal failed\r\n"));
    nrk_kernel_error_add (NRK_SIGNAL_CREATE_ERROR, nrk_cur_task_TCB->task_ID);
    return NRK_ERROR;
  }


  tx_data_ready = 0;
  // Set the one main rx buffer
  rx_buf_empty = 0;
  bmac_rfRxInfo.pPayload = NULL;
  bmac_rfRxInfo.max_length = 0;

  // Setup the cc2420 chip
  rf_power_up ();
  rf_init (&bmac_rfRxInfo, chan, 0xffff, 0);
  g_chan = chan;

//    FASTSPI_SETREG(CC2420_RSSI, 0xE580); // CCA THR=-25
//    FASTSPI_SETREG(CC2420_TXCTRL, 0x80FF); // TX TURNAROUND = 128 us
//    FASTSPI_SETREG(CC2420_RXCTRL1, 0x0A56); 
  // default cca thresh of -45
  //rf_set_cca_thresh(-45); 
  rf_set_cca_thresh (0x0);
  bmac_running = 1;
  is_enabled = 1;
  return NRK_OK;
}