static void permute(KeccakContext* ctx) {
uint8_t LFSRstate = 0x01;
for (uint8_t round = 0; round < 24; ++round) {
{ // Theta step (see [Keccak Reference, Section 2.3.2])
uint64_t C[5], D;
for (uint8_t x = 0; x < 5; ++x) {
C[x] = readLane(x, 0) ^ readLane(x, 1) ^
readLane(x, 2) ^ readLane(x, 3) ^ readLane(x, 4);
}
for (uint8_t x = 0; x < 5; ++x) {
D = C[(x+4)%5] ^ rol64(C[(x+1)%5], 1);
for (uint8_t y = 0; y < 5; ++y) {
XORLane(x, y, D);
}
}
}
{ // p and Pi steps (see [Keccak Reference, Sections 2.3.3 and 2.3.4])
uint8_t x = 1, y = 0;
uint64_t current = readLane(x, y);
for (uint8_t t = 0; t < 24; ++t) {
uint8_t r = ((t + 1) * (t + 2) / 2) % 64;
uint8_t Y = (2*x + 3*y) % 5;
x = y; y = Y;
uint64_t temp = readLane(x, y);
writeLane(x, y, rol64(current, r));
current = temp;
}
}
{ // X step (see [Keccak Reference, Section 2.3.1])
for (uint8_t y = 0; y < 5; ++y) {
uint64_t temp[5];
for (uint8_t x = 0; x < 5; ++x) {
temp[x] = readLane(x, y);
}
for (uint8_t x = 0; x < 5; ++x) {
writeLane(x, y, temp[x] ^((~temp[(x+1)%5]) & temp[(x+2)%5]));
}
}
}
{ // i step (see [Keccak Reference, Section 2.3.5])
for (uint8_t j = 0; j < 7; ++j) {
if (LFSR86540(LFSRstate)) {
uint64_t bitPos = (1<<j) - 1;
XORLane(0, 0, (uint64_t)1 << bitPos);
}
}
}
}
}
static void test_rol(void *p)
{
/* rol16 */
int_check(rol16(1, 1), 2);
int_check(rol16(1, 15), 32768);
int_check(rol16(0x8000, 1), 1);
/* rol32 */
int_check(rol32(1, 1), 2);
int_check(rol32(0x80000000, 1), 1);
/* rol64 */
ull_check(rol64(1, 1), 2);
ull_check(rol64(1, 63), 0x8000000000000000);
end:;
}
static inline void keccak_do_chunk(uint64_t state[25], uint64_t buf[], int bufsz)
{
int i, j, r;
uint64_t tmp, bc[5];
/* merge buf with state */
for (i = 0; i < bufsz; i++)
state[i] ^= le64_to_cpu(buf[i]);
/* run keccak rounds */
for (r = 0; r < KECCAK_NB_ROUNDS; r++) {
/* compute the parity of each columns */
for (i = 0; i < 5; i++)
bc[i] = state[i] ^ state[i+5] ^ state[i+10] ^ state[i+15] ^ state[i+20];
for (i = 0; i < 5; i++) {
tmp = bc[(i + 4) % 5] ^ rol64(bc[(i + 1) % 5], 1);
for (j = 0; j < 25; j += 5)
state[j + i] ^= tmp;
}
/* rho pi */
tmp = state[1];
for (i = 0; i < 24; i++) {
j = keccak_piln[i];
bc[0] = state[j];
state[j] = rol64(tmp, keccak_rotc[i]);
tmp = bc[0];
}
/* bitwise combine along rows using a = a xor (not b and c) */
for (j = 0; j < 25; j += 5) {
for (i = 0; i < 5; i++)
bc[i] = state[j + i];
#define andn(b,c) (~(b) & (c))
state[j + 0] ^= andn(bc[1], bc[2]);
state[j + 1] ^= andn(bc[2], bc[3]);
state[j + 2] ^= andn(bc[3], bc[4]);
state[j + 3] ^= andn(bc[4], bc[0]);
state[j + 4] ^= andn(bc[0], bc[1]);
#undef andn
}
/* xor the round constant */
state[0] ^= keccak_rndc[r];
}
}
/* Interpret pseudo code in tb. */
tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
{
long tcg_temps[CPU_TEMP_BUF_NLONGS];
uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
tcg_target_ulong next_tb = 0;
tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
tci_reg[TCG_REG_CALL_STACK] = sp_value;
assert(tb_ptr);
for (;;) {
TCGOpcode opc = tb_ptr[0];
#if !defined(NDEBUG)
uint8_t op_size = tb_ptr[1];
uint8_t *old_code_ptr = tb_ptr;
#endif
tcg_target_ulong t0;
tcg_target_ulong t1;
tcg_target_ulong t2;
tcg_target_ulong label;
TCGCond condition;
target_ulong taddr;
#ifndef CONFIG_SOFTMMU
tcg_target_ulong host_addr;
#endif
uint8_t tmp8;
uint16_t tmp16;
uint32_t tmp32;
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
uint64_t v64;
#endif
#if defined(GETPC)
tci_tb_ptr = (uintptr_t)tb_ptr;
#endif
/* Skip opcode and size entry. */
tb_ptr += 2;
switch (opc) {
case INDEX_op_end:
case INDEX_op_nop:
break;
case INDEX_op_nop1:
case INDEX_op_nop2:
case INDEX_op_nop3:
case INDEX_op_nopn:
case INDEX_op_discard:
TODO();
break;
case INDEX_op_set_label:
TODO();
break;
case INDEX_op_call:
t0 = tci_read_ri(&tb_ptr);
#if TCG_TARGET_REG_BITS == 32
tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
tci_read_reg(TCG_REG_R1),
tci_read_reg(TCG_REG_R2),
tci_read_reg(TCG_REG_R3),
tci_read_reg(TCG_REG_R5),
tci_read_reg(TCG_REG_R6),
tci_read_reg(TCG_REG_R7),
tci_read_reg(TCG_REG_R8),
tci_read_reg(TCG_REG_R9),
tci_read_reg(TCG_REG_R10));
tci_write_reg(TCG_REG_R0, tmp64);
tci_write_reg(TCG_REG_R1, tmp64 >> 32);
#else
tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
tci_read_reg(TCG_REG_R1),
tci_read_reg(TCG_REG_R2),
tci_read_reg(TCG_REG_R3),
tci_read_reg(TCG_REG_R5));
tci_write_reg(TCG_REG_R0, tmp64);
#endif
break;
case INDEX_op_br:
label = tci_read_label(&tb_ptr);
assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = (uint8_t *)label;
continue;
case INDEX_op_setcond_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
condition = *tb_ptr++;
tci_write_reg32(t0, tci_compare32(t1, t2, condition));
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
t0 = *tb_ptr++;
tmp64 = tci_read_r64(&tb_ptr);
v64 = tci_read_ri64(&tb_ptr);
condition = *tb_ptr++;
tci_write_reg32(t0, tci_compare64(tmp64, v64, condition));
break;
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
condition = *tb_ptr++;
tci_write_reg64(t0, tci_compare64(t1, t2, condition));
break;
#endif
case INDEX_op_mov_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg32(t0, t1);
break;
case INDEX_op_movi_i32:
t0 = *tb_ptr++;
t1 = tci_read_i32(&tb_ptr);
tci_write_reg32(t0, t1);
break;
/* Load/store operations (32 bit). */
case INDEX_op_ld8u_i32:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i32:
case INDEX_op_ld16u_i32:
TODO();
break;
case INDEX_op_ld16s_i32:
TODO();
break;
case INDEX_op_ld_i32:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
break;
case INDEX_op_st8_i32:
t0 = tci_read_r8(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint8_t *)(t1 + t2) = t0;
break;
case INDEX_op_st16_i32:
t0 = tci_read_r16(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint16_t *)(t1 + t2) = t0;
break;
case INDEX_op_st_i32:
t0 = tci_read_r32(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint32_t *)(t1 + t2) = t0;
break;
/* Arithmetic operations (32 bit). */
case INDEX_op_add_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 + t2);
break;
case INDEX_op_sub_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 - t2);
break;
case INDEX_op_mul_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 * t2);
break;
#if TCG_TARGET_HAS_div_i32
case INDEX_op_div_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2);
break;
case INDEX_op_divu_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 / t2);
break;
case INDEX_op_rem_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2);
break;
case INDEX_op_remu_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 % t2);
break;
#elif TCG_TARGET_HAS_div2_i32
case INDEX_op_div2_i32:
case INDEX_op_divu2_i32:
TODO();
break;
#endif
case INDEX_op_and_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 & t2);
break;
case INDEX_op_or_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 | t2);
break;
case INDEX_op_xor_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 ^ t2);
break;
/* Shift/rotate operations (32 bit). */
case INDEX_op_shl_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 << t2);
break;
case INDEX_op_shr_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 >> t2);
break;
case INDEX_op_sar_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, ((int32_t)t1 >> t2));
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, rol32(t1, t2));
break;
case INDEX_op_rotr_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, ror32(t1, t2));
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
case INDEX_op_deposit_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
t2 = tci_read_r32(&tb_ptr);
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp32 = (((1 << tmp8) - 1) << tmp16);
tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
break;
#endif
case INDEX_op_brcond_i32:
t0 = tci_read_r32(&tb_ptr);
t1 = tci_read_ri32(&tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare32(t0, t1, condition)) {
assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = (uint8_t *)label;
continue;
}
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
t0 = *tb_ptr++;
t1 = *tb_ptr++;
tmp64 = tci_read_r64(&tb_ptr);
tmp64 += tci_read_r64(&tb_ptr);
tci_write_reg64(t1, t0, tmp64);
break;
case INDEX_op_sub2_i32:
t0 = *tb_ptr++;
t1 = *tb_ptr++;
tmp64 = tci_read_r64(&tb_ptr);
tmp64 -= tci_read_r64(&tb_ptr);
tci_write_reg64(t1, t0, tmp64);
break;
case INDEX_op_brcond2_i32:
tmp64 = tci_read_r64(&tb_ptr);
v64 = tci_read_ri64(&tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare64(tmp64, v64, condition)) {
assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = (uint8_t *)label;
continue;
}
break;
case INDEX_op_mulu2_i32:
t0 = *tb_ptr++;
t1 = *tb_ptr++;
t2 = tci_read_r32(&tb_ptr);
tmp64 = tci_read_r32(&tb_ptr);
tci_write_reg64(t1, t0, t2 * tmp64);
break;
#endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32
case INDEX_op_ext8s_i32:
t0 = *tb_ptr++;
t1 = tci_read_r8s(&tb_ptr);
tci_write_reg32(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i32
case INDEX_op_ext16s_i32:
t0 = *tb_ptr++;
t1 = tci_read_r16s(&tb_ptr);
tci_write_reg32(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext8u_i32
case INDEX_op_ext8u_i32:
t0 = *tb_ptr++;
t1 = tci_read_r8(&tb_ptr);
tci_write_reg32(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i32
case INDEX_op_ext16u_i32:
t0 = *tb_ptr++;
t1 = tci_read_r16(&tb_ptr);
tci_write_reg32(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_bswap16_i32
case INDEX_op_bswap16_i32:
t0 = *tb_ptr++;
t1 = tci_read_r16(&tb_ptr);
tci_write_reg32(t0, bswap16(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap32_i32
case INDEX_op_bswap32_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg32(t0, bswap32(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i32
case INDEX_op_not_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg32(t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i32
case INDEX_op_neg_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg32(t0, -t1);
break;
#endif
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_mov_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
tci_write_reg64(t0, t1);
break;
case INDEX_op_movi_i64:
t0 = *tb_ptr++;
t1 = tci_read_i64(&tb_ptr);
tci_write_reg64(t0, t1);
break;
/* Load/store operations (64 bit). */
case INDEX_op_ld8u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i64:
case INDEX_op_ld16u_i64:
case INDEX_op_ld16s_i64:
TODO();
break;
case INDEX_op_ld32u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
break;
case INDEX_op_ld32s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg32s(t0, *(int32_t *)(t1 + t2));
break;
case INDEX_op_ld_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg64(t0, *(uint64_t *)(t1 + t2));
break;
case INDEX_op_st8_i64:
t0 = tci_read_r8(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint8_t *)(t1 + t2) = t0;
break;
case INDEX_op_st16_i64:
t0 = tci_read_r16(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint16_t *)(t1 + t2) = t0;
break;
case INDEX_op_st32_i64:
t0 = tci_read_r32(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint32_t *)(t1 + t2) = t0;
break;
case INDEX_op_st_i64:
t0 = tci_read_r64(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint64_t *)(t1 + t2) = t0;
break;
/* Arithmetic operations (64 bit). */
case INDEX_op_add_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 + t2);
break;
case INDEX_op_sub_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 - t2);
break;
case INDEX_op_mul_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 * t2);
break;
#if TCG_TARGET_HAS_div_i64
case INDEX_op_div_i64:
case INDEX_op_divu_i64:
case INDEX_op_rem_i64:
case INDEX_op_remu_i64:
TODO();
break;
#elif TCG_TARGET_HAS_div2_i64
case INDEX_op_div2_i64:
case INDEX_op_divu2_i64:
TODO();
break;
#endif
case INDEX_op_and_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 & t2);
break;
case INDEX_op_or_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 | t2);
break;
case INDEX_op_xor_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 ^ t2);
break;
/* Shift/rotate operations (64 bit). */
case INDEX_op_shl_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 << t2);
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 >> t2);
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, ((int64_t)t1 >> t2));
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, rol64(t1, t2));
break;
case INDEX_op_rotr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, ror64(t1, t2));
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
case INDEX_op_deposit_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
t2 = tci_read_r64(&tb_ptr);
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp64 = (((1ULL << tmp8) - 1) << tmp16);
tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
break;
#endif
case INDEX_op_brcond_i64:
t0 = tci_read_r64(&tb_ptr);
t1 = tci_read_ri64(&tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare64(t0, t1, condition)) {
assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = (uint8_t *)label;
continue;
}
break;
#if TCG_TARGET_HAS_ext8u_i64
case INDEX_op_ext8u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r8(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext8s_i64
case INDEX_op_ext8s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r8s(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i64
case INDEX_op_ext16s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r16s(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i64
case INDEX_op_ext16u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r16(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext32s_i64
case INDEX_op_ext32s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32s(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext32u_i64
case INDEX_op_ext32u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_bswap16_i64
case INDEX_op_bswap16_i64:
TODO();
t0 = *tb_ptr++;
t1 = tci_read_r16(&tb_ptr);
tci_write_reg64(t0, bswap16(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap32_i64
case INDEX_op_bswap32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg64(t0, bswap32(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
tci_write_reg64(t0, bswap64(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i64
case INDEX_op_not_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
tci_write_reg64(t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i64
case INDEX_op_neg_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
tci_write_reg64(t0, -t1);
break;
#endif
#endif /* TCG_TARGET_REG_BITS == 64 */
/* QEMU specific operations. */
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
case INDEX_op_debug_insn_start:
TODO();
break;
#else
case INDEX_op_debug_insn_start:
TODO();
break;
#endif
case INDEX_op_exit_tb:
next_tb = *(uint64_t *)tb_ptr;
goto exit;
break;
case INDEX_op_goto_tb:
t0 = tci_read_i32(&tb_ptr);
assert(tb_ptr == old_code_ptr + op_size);
tb_ptr += (int32_t)t0;
continue;
case INDEX_op_qemu_ld8u:
t0 = *tb_ptr++;
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr));
#else
host_addr = (tcg_target_ulong)taddr;
tmp8 = *(uint8_t *)(host_addr + GUEST_BASE);
#endif
tci_write_reg8(t0, tmp8);
break;
case INDEX_op_qemu_ld8s:
t0 = *tb_ptr++;
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr));
#else
host_addr = (tcg_target_ulong)taddr;
tmp8 = *(uint8_t *)(host_addr + GUEST_BASE);
#endif
tci_write_reg8s(t0, tmp8);
break;
case INDEX_op_qemu_ld16u:
t0 = *tb_ptr++;
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr));
#else
host_addr = (tcg_target_ulong)taddr;
tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE));
#endif
tci_write_reg16(t0, tmp16);
break;
case INDEX_op_qemu_ld16s:
t0 = *tb_ptr++;
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr));
#else
host_addr = (tcg_target_ulong)taddr;
tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE));
#endif
tci_write_reg16s(t0, tmp16);
break;
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_qemu_ld32u:
t0 = *tb_ptr++;
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
#else
host_addr = (tcg_target_ulong)taddr;
tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
#endif
tci_write_reg32(t0, tmp32);
break;
case INDEX_op_qemu_ld32s:
t0 = *tb_ptr++;
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
#else
host_addr = (tcg_target_ulong)taddr;
tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
#endif
tci_write_reg32s(t0, tmp32);
break;
#endif /* TCG_TARGET_REG_BITS == 64 */
case INDEX_op_qemu_ld32:
t0 = *tb_ptr++;
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
#else
host_addr = (tcg_target_ulong)taddr;
tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
#endif
tci_write_reg32(t0, tmp32);
break;
case INDEX_op_qemu_ld64:
t0 = *tb_ptr++;
#if TCG_TARGET_REG_BITS == 32
t1 = *tb_ptr++;
#endif
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
tmp64 = helper_ldq_mmu(env, taddr, tci_read_i(&tb_ptr));
#else
host_addr = (tcg_target_ulong)taddr;
tmp64 = tswap64(*(uint64_t *)(host_addr + GUEST_BASE));
#endif
tci_write_reg(t0, tmp64);
#if TCG_TARGET_REG_BITS == 32
tci_write_reg(t1, tmp64 >> 32);
#endif
break;
case INDEX_op_qemu_st8:
t0 = tci_read_r8(&tb_ptr);
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
t2 = tci_read_i(&tb_ptr);
helper_stb_mmu(env, taddr, t0, t2);
#else
host_addr = (tcg_target_ulong)taddr;
*(uint8_t *)(host_addr + GUEST_BASE) = t0;
#endif
break;
case INDEX_op_qemu_st16:
t0 = tci_read_r16(&tb_ptr);
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
t2 = tci_read_i(&tb_ptr);
helper_stw_mmu(env, taddr, t0, t2);
#else
host_addr = (tcg_target_ulong)taddr;
*(uint16_t *)(host_addr + GUEST_BASE) = tswap16(t0);
#endif
break;
case INDEX_op_qemu_st32:
t0 = tci_read_r32(&tb_ptr);
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
t2 = tci_read_i(&tb_ptr);
helper_stl_mmu(env, taddr, t0, t2);
#else
host_addr = (tcg_target_ulong)taddr;
*(uint32_t *)(host_addr + GUEST_BASE) = tswap32(t0);
#endif
break;
case INDEX_op_qemu_st64:
tmp64 = tci_read_r64(&tb_ptr);
taddr = tci_read_ulong(&tb_ptr);
#ifdef CONFIG_SOFTMMU
t2 = tci_read_i(&tb_ptr);
helper_stq_mmu(env, taddr, tmp64, t2);
#else
host_addr = (tcg_target_ulong)taddr;
*(uint64_t *)(host_addr + GUEST_BASE) = tswap64(tmp64);
#endif
break;
default:
TODO();
break;
}
assert(tb_ptr == old_code_ptr + op_size);
}
exit:
return next_tb;
}
/* Interpret pseudo code in tb. */
uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
{
long tcg_temps[CPU_TEMP_BUF_NLONGS];
uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
uintptr_t ret = 0;
tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
tci_reg[TCG_REG_CALL_STACK] = sp_value;
tci_assert(tb_ptr);
for (;;) {
TCGOpcode opc = tb_ptr[0];
#if defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
uint8_t op_size = tb_ptr[1];
uint8_t *old_code_ptr = tb_ptr;
#endif
tcg_target_ulong t0;
tcg_target_ulong t1;
tcg_target_ulong t2;
tcg_target_ulong label;
TCGCond condition;
target_ulong taddr;
uint8_t tmp8;
uint16_t tmp16;
uint32_t tmp32;
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
uint64_t v64;
#endif
TCGMemOpIdx oi;
#if defined(GETPC)
tci_tb_ptr = (uintptr_t)tb_ptr;
#endif
/* Skip opcode and size entry. */
tb_ptr += 2;
switch (opc) {
case INDEX_op_call:
t0 = tci_read_ri(&tb_ptr);
#if TCG_TARGET_REG_BITS == 32
tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
tci_read_reg(TCG_REG_R1),
tci_read_reg(TCG_REG_R2),
tci_read_reg(TCG_REG_R3),
tci_read_reg(TCG_REG_R5),
tci_read_reg(TCG_REG_R6),
tci_read_reg(TCG_REG_R7),
tci_read_reg(TCG_REG_R8),
tci_read_reg(TCG_REG_R9),
tci_read_reg(TCG_REG_R10));
tci_write_reg(TCG_REG_R0, tmp64);
tci_write_reg(TCG_REG_R1, tmp64 >> 32);
#else
tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
tci_read_reg(TCG_REG_R1),
tci_read_reg(TCG_REG_R2),
tci_read_reg(TCG_REG_R3),
tci_read_reg(TCG_REG_R5));
tci_write_reg(TCG_REG_R0, tmp64);
#endif
break;
case INDEX_op_br:
label = tci_read_label(&tb_ptr);
tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = (uint8_t *)label;
continue;
case INDEX_op_setcond_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
condition = *tb_ptr++;
tci_write_reg32(t0, tci_compare32(t1, t2, condition));
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
t0 = *tb_ptr++;
tmp64 = tci_read_r64(&tb_ptr);
v64 = tci_read_ri64(&tb_ptr);
condition = *tb_ptr++;
tci_write_reg32(t0, tci_compare64(tmp64, v64, condition));
break;
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
condition = *tb_ptr++;
tci_write_reg64(t0, tci_compare64(t1, t2, condition));
break;
#endif
case INDEX_op_mov_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg32(t0, t1);
break;
case INDEX_op_movi_i32:
t0 = *tb_ptr++;
t1 = tci_read_i32(&tb_ptr);
tci_write_reg32(t0, t1);
break;
/* Load/store operations (32 bit). */
case INDEX_op_ld8u_i32:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i32:
case INDEX_op_ld16u_i32:
TODO();
break;
case INDEX_op_ld16s_i32:
TODO();
break;
case INDEX_op_ld_i32:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
break;
case INDEX_op_st8_i32:
t0 = tci_read_r8(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint8_t *)(t1 + t2) = t0;
break;
case INDEX_op_st16_i32:
t0 = tci_read_r16(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint16_t *)(t1 + t2) = t0;
break;
case INDEX_op_st_i32:
t0 = tci_read_r32(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint32_t *)(t1 + t2) = t0;
break;
/* Arithmetic operations (32 bit). */
case INDEX_op_add_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 + t2);
break;
case INDEX_op_sub_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 - t2);
break;
case INDEX_op_mul_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 * t2);
break;
#if TCG_TARGET_HAS_div_i32
case INDEX_op_div_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2);
break;
case INDEX_op_divu_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 / t2);
break;
case INDEX_op_rem_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2);
break;
case INDEX_op_remu_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 % t2);
break;
#elif TCG_TARGET_HAS_div2_i32
case INDEX_op_div2_i32:
case INDEX_op_divu2_i32:
TODO();
break;
#endif
case INDEX_op_and_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 & t2);
break;
case INDEX_op_or_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 | t2);
break;
case INDEX_op_xor_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 ^ t2);
break;
/* Shift/rotate operations (32 bit). */
case INDEX_op_shl_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 << (t2 & 31));
break;
case INDEX_op_shr_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, t1 >> (t2 & 31));
break;
case INDEX_op_sar_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31)));
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, rol32(t1, t2 & 31));
break;
case INDEX_op_rotr_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, ror32(t1, t2 & 31));
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
case INDEX_op_deposit_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
t2 = tci_read_r32(&tb_ptr);
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp32 = (((1 << tmp8) - 1) << tmp16);
tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
break;
#endif
case INDEX_op_brcond_i32:
t0 = tci_read_r32(&tb_ptr);
t1 = tci_read_ri32(&tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare32(t0, t1, condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = (uint8_t *)label;
continue;
}
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
t0 = *tb_ptr++;
t1 = *tb_ptr++;
tmp64 = tci_read_r64(&tb_ptr);
tmp64 += tci_read_r64(&tb_ptr);
tci_write_reg64(t1, t0, tmp64);
break;
case INDEX_op_sub2_i32:
t0 = *tb_ptr++;
t1 = *tb_ptr++;
tmp64 = tci_read_r64(&tb_ptr);
tmp64 -= tci_read_r64(&tb_ptr);
tci_write_reg64(t1, t0, tmp64);
break;
case INDEX_op_brcond2_i32:
tmp64 = tci_read_r64(&tb_ptr);
v64 = tci_read_ri64(&tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare64(tmp64, v64, condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = (uint8_t *)label;
continue;
}
break;
case INDEX_op_mulu2_i32:
t0 = *tb_ptr++;
t1 = *tb_ptr++;
t2 = tci_read_r32(&tb_ptr);
tmp64 = tci_read_r32(&tb_ptr);
tci_write_reg64(t1, t0, t2 * tmp64);
break;
#endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32
case INDEX_op_ext8s_i32:
t0 = *tb_ptr++;
t1 = tci_read_r8s(&tb_ptr);
tci_write_reg32(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i32
case INDEX_op_ext16s_i32:
t0 = *tb_ptr++;
t1 = tci_read_r16s(&tb_ptr);
tci_write_reg32(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext8u_i32
case INDEX_op_ext8u_i32:
t0 = *tb_ptr++;
t1 = tci_read_r8(&tb_ptr);
tci_write_reg32(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i32
case INDEX_op_ext16u_i32:
t0 = *tb_ptr++;
t1 = tci_read_r16(&tb_ptr);
tci_write_reg32(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_bswap16_i32
case INDEX_op_bswap16_i32:
t0 = *tb_ptr++;
t1 = tci_read_r16(&tb_ptr);
tci_write_reg32(t0, bswap16(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap32_i32
case INDEX_op_bswap32_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg32(t0, bswap32(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i32
case INDEX_op_not_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg32(t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i32
case INDEX_op_neg_i32:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg32(t0, -t1);
break;
#endif
#if TCG_TARGET_REG_BITS == 64
case INDEX_op_mov_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
tci_write_reg64(t0, t1);
break;
case INDEX_op_movi_i64:
t0 = *tb_ptr++;
t1 = tci_read_i64(&tb_ptr);
tci_write_reg64(t0, t1);
break;
/* Load/store operations (64 bit). */
case INDEX_op_ld8u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i64:
case INDEX_op_ld16u_i64:
case INDEX_op_ld16s_i64:
TODO();
break;
case INDEX_op_ld32u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
break;
case INDEX_op_ld32s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg32s(t0, *(int32_t *)(t1 + t2));
break;
case INDEX_op_ld_i64:
t0 = *tb_ptr++;
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_write_reg64(t0, *(uint64_t *)(t1 + t2));
break;
case INDEX_op_st8_i64:
t0 = tci_read_r8(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint8_t *)(t1 + t2) = t0;
break;
case INDEX_op_st16_i64:
t0 = tci_read_r16(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint16_t *)(t1 + t2) = t0;
break;
case INDEX_op_st32_i64:
t0 = tci_read_r32(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
*(uint32_t *)(t1 + t2) = t0;
break;
case INDEX_op_st_i64:
t0 = tci_read_r64(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
tci_assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint64_t *)(t1 + t2) = t0;
break;
/* Arithmetic operations (64 bit). */
case INDEX_op_add_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 + t2);
break;
case INDEX_op_sub_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 - t2);
break;
case INDEX_op_mul_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 * t2);
break;
#if TCG_TARGET_HAS_div_i64
case INDEX_op_div_i64:
case INDEX_op_divu_i64:
case INDEX_op_rem_i64:
case INDEX_op_remu_i64:
TODO();
break;
#elif TCG_TARGET_HAS_div2_i64
case INDEX_op_div2_i64:
case INDEX_op_divu2_i64:
TODO();
break;
#endif
case INDEX_op_and_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 & t2);
break;
case INDEX_op_or_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 | t2);
break;
case INDEX_op_xor_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 ^ t2);
break;
/* Shift/rotate operations (64 bit). */
case INDEX_op_shl_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 << (t2 & 63));
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, t1 >> (t2 & 63));
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63)));
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, rol64(t1, t2 & 63));
break;
case INDEX_op_rotr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, ror64(t1, t2 & 63));
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
case INDEX_op_deposit_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
t2 = tci_read_r64(&tb_ptr);
tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++;
tmp64 = (((1ULL << tmp8) - 1) << tmp16);
tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
break;
#endif
case INDEX_op_brcond_i64:
t0 = tci_read_r64(&tb_ptr);
t1 = tci_read_ri64(&tb_ptr);
condition = *tb_ptr++;
label = tci_read_label(&tb_ptr);
if (tci_compare64(t0, t1, condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr = (uint8_t *)label;
continue;
}
break;
#if TCG_TARGET_HAS_ext8u_i64
case INDEX_op_ext8u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r8(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext8s_i64
case INDEX_op_ext8s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r8s(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16s_i64
case INDEX_op_ext16s_i64:
t0 = *tb_ptr++;
t1 = tci_read_r16s(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext16u_i64
case INDEX_op_ext16u_i64:
t0 = *tb_ptr++;
t1 = tci_read_r16(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#endif
#if TCG_TARGET_HAS_ext32s_i64
case INDEX_op_ext32s_i64:
#endif
case INDEX_op_ext_i32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32s(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#if TCG_TARGET_HAS_ext32u_i64
case INDEX_op_ext32u_i64:
#endif
case INDEX_op_extu_i32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg64(t0, t1);
break;
#if TCG_TARGET_HAS_bswap16_i64
case INDEX_op_bswap16_i64:
t0 = *tb_ptr++;
t1 = tci_read_r16(&tb_ptr);
tci_write_reg64(t0, bswap16(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap32_i64
case INDEX_op_bswap32_i64:
t0 = *tb_ptr++;
t1 = tci_read_r32(&tb_ptr);
tci_write_reg64(t0, bswap32(t1));
break;
#endif
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
tci_write_reg64(t0, bswap64(t1));
break;
#endif
#if TCG_TARGET_HAS_not_i64
case INDEX_op_not_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
tci_write_reg64(t0, ~t1);
break;
#endif
#if TCG_TARGET_HAS_neg_i64
case INDEX_op_neg_i64:
t0 = *tb_ptr++;
t1 = tci_read_r64(&tb_ptr);
tci_write_reg64(t0, -t1);
break;
#endif
#endif /* TCG_TARGET_REG_BITS == 64 */
/* QEMU specific operations. */
case INDEX_op_exit_tb:
ret = *(uint64_t *)tb_ptr;
goto exit;
break;
case INDEX_op_goto_tb:
/* Jump address is aligned */
tb_ptr = QEMU_ALIGN_PTR_UP(tb_ptr, 4);
t0 = atomic_read((int32_t *)tb_ptr);
tb_ptr += sizeof(int32_t);
tci_assert(tb_ptr == old_code_ptr + op_size);
tb_ptr += (int32_t)t0;
continue;
case INDEX_op_qemu_ld_i32:
t0 = *tb_ptr++;
taddr = tci_read_ulong(&tb_ptr);
oi = tci_read_i(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
tmp32 = qemu_ld_ub;
break;
case MO_SB:
tmp32 = (int8_t)qemu_ld_ub;
break;
case MO_LEUW:
tmp32 = qemu_ld_leuw;
break;
case MO_LESW:
tmp32 = (int16_t)qemu_ld_leuw;
break;
case MO_LEUL:
tmp32 = qemu_ld_leul;
break;
case MO_BEUW:
tmp32 = qemu_ld_beuw;
break;
case MO_BESW:
tmp32 = (int16_t)qemu_ld_beuw;
break;
case MO_BEUL:
tmp32 = qemu_ld_beul;
break;
default:
tcg_abort();
}
tci_write_reg(t0, tmp32);
break;
case INDEX_op_qemu_ld_i64:
t0 = *tb_ptr++;
if (TCG_TARGET_REG_BITS == 32) {
t1 = *tb_ptr++;
}
taddr = tci_read_ulong(&tb_ptr);
oi = tci_read_i(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
case MO_UB:
tmp64 = qemu_ld_ub;
break;
case MO_SB:
tmp64 = (int8_t)qemu_ld_ub;
break;
case MO_LEUW:
tmp64 = qemu_ld_leuw;
break;
case MO_LESW:
tmp64 = (int16_t)qemu_ld_leuw;
break;
case MO_LEUL:
tmp64 = qemu_ld_leul;
break;
case MO_LESL:
tmp64 = (int32_t)qemu_ld_leul;
break;
case MO_LEQ:
tmp64 = qemu_ld_leq;
break;
case MO_BEUW:
tmp64 = qemu_ld_beuw;
break;
case MO_BESW:
tmp64 = (int16_t)qemu_ld_beuw;
break;
case MO_BEUL:
tmp64 = qemu_ld_beul;
break;
case MO_BESL:
tmp64 = (int32_t)qemu_ld_beul;
break;
case MO_BEQ:
tmp64 = qemu_ld_beq;
break;
default:
tcg_abort();
}
tci_write_reg(t0, tmp64);
if (TCG_TARGET_REG_BITS == 32) {
tci_write_reg(t1, tmp64 >> 32);
}
break;
case INDEX_op_qemu_st_i32:
t0 = tci_read_r(&tb_ptr);
taddr = tci_read_ulong(&tb_ptr);
oi = tci_read_i(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
case MO_UB:
qemu_st_b(t0);
break;
case MO_LEUW:
qemu_st_lew(t0);
break;
case MO_LEUL:
qemu_st_lel(t0);
break;
case MO_BEUW:
qemu_st_bew(t0);
break;
case MO_BEUL:
qemu_st_bel(t0);
break;
default:
tcg_abort();
}
break;
case INDEX_op_qemu_st_i64:
tmp64 = tci_read_r64(&tb_ptr);
taddr = tci_read_ulong(&tb_ptr);
oi = tci_read_i(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
case MO_UB:
qemu_st_b(tmp64);
break;
case MO_LEUW:
qemu_st_lew(tmp64);
break;
case MO_LEUL:
qemu_st_lel(tmp64);
break;
case MO_LEQ:
qemu_st_leq(tmp64);
break;
case MO_BEUW:
qemu_st_bew(tmp64);
break;
case MO_BEUL:
qemu_st_bel(tmp64);
break;
case MO_BEQ:
qemu_st_beq(tmp64);
break;
default:
tcg_abort();
}
break;
case INDEX_op_mb:
/* Ensure ordering for all kinds */
smp_mb();
break;
default:
TODO();
break;
}
tci_assert(tb_ptr == old_code_ptr + op_size);
}
static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
{
uint64_t l64, h64;
switch (op) {
CASE_OP_32_64(add):
return x + y;
CASE_OP_32_64(sub):
return x - y;
CASE_OP_32_64(mul):
return x * y;
CASE_OP_32_64(and):
return x & y;
CASE_OP_32_64(or):
return x | y;
CASE_OP_32_64(xor):
return x ^ y;
case INDEX_op_shl_i32:
return (uint32_t)x << (y & 31);
case INDEX_op_shl_i64:
return (uint64_t)x << (y & 63);
case INDEX_op_shr_i32:
return (uint32_t)x >> (y & 31);
case INDEX_op_trunc_shr_i32:
case INDEX_op_shr_i64:
return (uint64_t)x >> (y & 63);
case INDEX_op_sar_i32:
return (int32_t)x >> (y & 31);
case INDEX_op_sar_i64:
return (int64_t)x >> (y & 63);
case INDEX_op_rotr_i32:
return ror32(x, y & 31);
case INDEX_op_rotr_i64:
return (TCGArg)ror64(x, y & 63);
case INDEX_op_rotl_i32:
return rol32(x, y & 31);
case INDEX_op_rotl_i64:
return (TCGArg)rol64(x, y & 63);
CASE_OP_32_64(not):
return ~x;
CASE_OP_32_64(neg):
return 0-x;
CASE_OP_32_64(andc):
return x & ~y;
CASE_OP_32_64(orc):
return x | ~y;
CASE_OP_32_64(eqv):
return ~(x ^ y);
CASE_OP_32_64(nand):
return ~(x & y);
CASE_OP_32_64(nor):
return ~(x | y);
CASE_OP_32_64(ext8s):
return (int8_t)x;
CASE_OP_32_64(ext16s):
return (int16_t)x;
CASE_OP_32_64(ext8u):
return (uint8_t)x;
CASE_OP_32_64(ext16u):
return (uint16_t)x;
case INDEX_op_ext32s_i64:
return (int32_t)x;
case INDEX_op_ext32u_i64:
return (uint32_t)x;
case INDEX_op_muluh_i32:
return ((uint64_t)(uint32_t)x * (uint32_t)y) >> 32;
case INDEX_op_mulsh_i32:
return ((int64_t)(int32_t)x * (int32_t)y) >> 32;
case INDEX_op_muluh_i64:
mulu64(&l64, &h64, x, y);
return (TCGArg)h64;
case INDEX_op_mulsh_i64:
muls64(&l64, &h64, x, y);
return (TCGArg)h64;
case INDEX_op_div_i32:
/* Avoid crashing on divide by zero, otherwise undefined. */
return (int32_t)x / ((int32_t)y ? (int32_t)y : 1);
case INDEX_op_divu_i32:
return (uint32_t)x / ((uint32_t)y ? (uint32_t)y : 1);
case INDEX_op_div_i64:
return (int64_t)x / ((int64_t)y ? (int64_t)y : 1);
case INDEX_op_divu_i64:
return (uint64_t)x / ((uint64_t)y ? (uint64_t)y : 1);
case INDEX_op_rem_i32:
return (int32_t)x % ((int32_t)y ? (int32_t)y : 1);
case INDEX_op_remu_i32:
return (uint32_t)x % ((uint32_t)y ? (uint32_t)y : 1);
case INDEX_op_rem_i64:
return (int64_t)x % ((int64_t)y ? (int64_t)y : 1);
case INDEX_op_remu_i64:
return (uint64_t)x % ((uint64_t)y ? (uint64_t)y : 1);
default:
fprintf(stderr,
"Unrecognized operation %d in do_constant_folding.\n", op);
tcg_abort();
}
}
__u64 jent_rol64(__u64 word, unsigned int shift)
{
return rol64(word, shift);
}
