/** @brief Prepares new time vector.
*
* Prepares new time vector based on currently used parameters.
*
* @param [out] out_signal New output time signal, from t_start to t_stop
* @param [in] dec_factor Decimation factor programmed in FPGA.
* @param [in] t_start Starting time defined by main module and client.
* @param [in] t_stop Stop time defined by main module and client.
* @param [in] time_unit Time units used with current parameters.
*
* @retval 0 Always returns 0
*/
int rp_osc_prepare_time_vector(float **out_signal, int dec_factor,
float t_start, float t_stop, int time_unit)
{
float smpl_period = c_osc_fpga_smpl_period * dec_factor;
float t_step, t_curr;
int out_idx, in_idx;
int idx_step;
int t_unit_factor = rp_osc_get_time_unit_factor(time_unit);;
float *s = *out_signal;
if(t_stop <= t_start) {
t_start = 0;
t_stop = OSC_FPGA_SIG_LEN * smpl_period;
}
t_step = (t_stop - t_start) / (SIGNAL_LENGTH-1);
idx_step = (int)(ceil(t_step/smpl_period));
if(idx_step > 8)
idx_step = 8;
for(out_idx = 0, in_idx = 0, t_curr=t_start; out_idx < SIGNAL_LENGTH;
out_idx++, t_curr += t_step, in_idx += idx_step) {
s[out_idx] = t_curr * t_unit_factor;
}
return 0;
}
/** @brief Processing function used
*
* This function takes as argument raw FPGA signal and performs decimation and
* conversion from ADC samples to voltage.
* Output signals are of length SIGNAL_LENGTH (defined in main_osc.h), input
* signals are of length OSC_FPGA_SIG_LEN (defined in fpga_osc.h).
* @param [out] cha_out_signal - processed output signal for Channel A
* @param [in] cha_in_signal - input raw signal for Channel A
* @param [out] chb_out_signal - processed output signal for Channel B
* @param [in] chb_in_signal - input raw signal for Channel B
* @param [out] time_out_signal - processed output time vector signal
* @param [inout] next_wr_ptr - write pointer used for FPGA signal readout
* (it is updated during decimation and returned, so
* worker thread can wait for next samples)
* @param [in] last_wr_ptr - Last expected write pointer (when next_wr_ptr
* reaches this value full signal is acquired)
* @param [in] next_out_idx - Starting index for output signals
* @param [in] dec_factor - decimation factor parameter set by main or client
* @param [in] t_start - starting time of requested acquisition
* @param [in] t_stop - stopping time of requested acquisition
* @param [in] time_unit - time units currently used
*
* @retval last_out_idx Function returns last sample written to output signal.
*/
int rp_osc_decimate_partial(float **cha_out_signal, int *cha_in_signal,
float **chb_out_signal, int *chb_in_signal,
float **time_out_signal, int *next_wr_ptr,
int last_wr_ptr, int step_wr_ptr, int next_out_idx,
float t_start, int dec_factor, int time_unit)
{
//float *cha_out = *cha_out_signal;//ERG :: removes compiler error
//float *chb_out = *chb_out_signal;//ERG :: removes compiler error
float *t_out = *time_out_signal;
int in_idx = *next_wr_ptr;
float smpl_period = c_osc_fpga_smpl_period * dec_factor;
int t_unit_factor = rp_osc_get_time_unit_factor(time_unit);
int curr_ptr;
/* check if we have reached currently acquired signals in FPGA */
osc_fpga_get_wr_ptr(&curr_ptr, NULL);
for(; (next_out_idx < SIGNAL_LENGTH); next_out_idx++,
in_idx += step_wr_ptr) {
int curr_ptr;
int diff_ptr;
/* check if we have reached currently acquired signals in FPGA */
osc_fpga_get_wr_ptr(&curr_ptr, NULL);
if(in_idx >= OSC_FPGA_SIG_LEN)
in_idx = in_idx % OSC_FPGA_SIG_LEN;
diff_ptr = (in_idx-curr_ptr);
/* Check that we did not hit the curr ptr (and that pointer is not
* wrapped
*/
if((in_idx >= curr_ptr) && (diff_ptr > 0) && (diff_ptr < 100))
break;
//ERG :: note that rp_osc_decimate_partial is not used, so don't care about next 2 lines
//cha_out[next_out_idx] = osc_fpga_cnv_cnt_to_v(cha_in_signal[in_idx]);
//chb_out[next_out_idx] = osc_fpga_cnv_cnt_to_v(chb_in_signal[in_idx]);
t_out[next_out_idx] =
(t_start + ((next_out_idx*step_wr_ptr)*smpl_period))*t_unit_factor;
}
*next_wr_ptr = in_idx;
return next_out_idx;
}
/** @brief Returns current parameters.
*
* This function returns an array of parameters.
*
* @param [out] p Returned pointer to the parameters array.
*
* @retval -1 Failure
* @retval otherwise Length of returned parameters array.
*
* @note Returned parameters pointer must be cleaned up externally!
*/
int rp_get_params(float **p)
{
float *p_copy = NULL;
int t_unit_factor =
rp_osc_get_time_unit_factor(rp_main_params[TIME_UNIT_PARAM].value);
int i;
p_copy = (float *)malloc(PARAMS_NUM * sizeof(float));
if(p_copy == NULL)
return -1;
for(i = 0; i < PARAMS_NUM; i++)
p_copy[i] = rp_main_params[i].value;
p_copy[MIN_GUI_PARAM] = p_copy[MIN_GUI_PARAM] * t_unit_factor;
p_copy[MAX_GUI_PARAM] = p_copy[MAX_GUI_PARAM] * t_unit_factor;
*p = p_copy;
return PARAMS_NUM;
}
/* Returned vector must be free'd externally! */
int rp_get_params(rp_app_params_t **p)
{
rp_app_params_t *p_copy = NULL;
int t_unit_factor;
int i;
p_copy = (rp_app_params_t *)malloc((PARAMS_NUM+1) * sizeof(rp_app_params_t));
if(p_copy == NULL)
return -1;
pthread_mutex_lock(&rp_main_params_mutex);
t_unit_factor =
rp_osc_get_time_unit_factor(rp_main_params[TIME_UNIT_PARAM].value);
for(i = 0; i < PARAMS_NUM; i++) {
int p_strlen = strlen(rp_main_params[i].name);
p_copy[i].name = (char *)malloc(p_strlen+1);
strncpy((char *)&p_copy[i].name[0], &rp_main_params[i].name[0],
p_strlen);
p_copy[i].name[p_strlen]='\0';
p_copy[i].value = rp_main_params[i].value;
p_copy[i].fpga_update = rp_main_params[i].fpga_update;
p_copy[i].read_only = rp_main_params[i].read_only;
p_copy[i].min_val = rp_main_params[i].min_val;
p_copy[i].max_val = rp_main_params[i].max_val;
}
pthread_mutex_unlock(&rp_main_params_mutex);
p_copy[PARAMS_NUM].name = NULL;
p_copy[MIN_GUI_PARAM].value = p_copy[MIN_GUI_PARAM].value * t_unit_factor;
p_copy[MAX_GUI_PARAM].value = p_copy[MAX_GUI_PARAM].value * t_unit_factor;
*p = p_copy;
return PARAMS_NUM;
}
int rp_osc_decimate(float **cha_signal, int *in_cha_signal,
float **chb_signal, int *in_chb_signal,
float **time_signal, int dec_factor,
float t_start, float t_stop, int time_unit)
{
int t_start_idx, t_stop_idx;
float smpl_period = c_osc_fpga_smpl_period * dec_factor;
int t_unit_factor = rp_osc_get_time_unit_factor(time_unit);
int t_step;
int in_idx, out_idx, t_idx;
int wr_ptr_curr, wr_ptr_trig;
float *cha_s = *cha_signal;
float *chb_s = *chb_signal;
float *t = *time_signal;
/* If illegal take whole frame */
if(t_stop <= t_start) {
t_start = 0;
t_stop = (OSC_FPGA_SIG_LEN-1) * smpl_period;
}
/* convert time to samples */
t_start_idx = round(t_start / smpl_period);
t_stop_idx = round(t_stop / smpl_period);
if((((t_stop_idx-t_start_idx)/(float)(SIGNAL_LENGTH-1))) < 1)
t_step = 1;
else {
/* ceil was used already in rp_osc_main() for parameters, so we can easily
* use round() here
*/
t_step = round((t_stop_idx-t_start_idx)/(float)(SIGNAL_LENGTH-1));
}
osc_fpga_get_wr_ptr(&wr_ptr_curr, &wr_ptr_trig);
if (dec_factor==1)
in_idx = wr_ptr_trig + t_start_idx + 3;
else
in_idx = wr_ptr_trig + t_start_idx + 1; // There it additional FPGA delay when decimation enabled.
if (dec_factor>8192)
in_idx = wr_ptr_trig + t_start_idx + 0;
if(in_idx < 0)
in_idx = OSC_FPGA_SIG_LEN + in_idx;
if(in_idx >= OSC_FPGA_SIG_LEN)
in_idx = in_idx % OSC_FPGA_SIG_LEN;
for(out_idx=0, t_idx=0; out_idx < SIGNAL_LENGTH;
out_idx++, in_idx+=t_step, t_idx+=t_step) {
/* Wrap the pointer */
if(in_idx >= OSC_FPGA_SIG_LEN)
in_idx = in_idx % OSC_FPGA_SIG_LEN;
cha_s[out_idx] = osc_fpga_cnv_cnt_to_v(in_cha_signal[in_idx]);
chb_s[out_idx] = osc_fpga_cnv_cnt_to_v(in_chb_signal[in_idx]);
t[out_idx] = (t_start + (t_idx * smpl_period)) * t_unit_factor;
}
return 0;
}
/** @brief Main processing function used to decimate and convert data signals.
*
* This function takes as argument raw FPGA signal and performs decimation and
* conversion from ADC samples to voltage.
* Output signals are of length SIGNAL_LENGTH (defined in main_osc.h), input
* signals are of length OSC_FPGA_SIG_LEN (defined in fpga_osc.h).
*
* @param [out] cha_signal - processed output signal for Channel A
* @param [in] in_cha_signal - input raw signal for Channel A
* @param [out] chb_signal - processed output signal for Channel B
* @param [in] in_chb_signal - input raw signal for Channel B
* @param [out] time_signal - processed output time vector signal
* @param [in] dec_factor - decimation factor parameter set by main or client
* @param [in] t_start - starting time of requested acquisition
* @param [in] t_stop - stopping time of requested acquisition
* @param [in] time_unit - time units currently used
*
* @retval 0 Always returns 0.
*/
int rp_osc_decimate_with_calib(float **cha_signal, int *in_cha_signal,
float **chb_signal, int *in_chb_signal,
float **time_signal, int dec_factor,
float t_start, float t_stop, int time_unit,
rp_osc_meas_res_t *ch1_meas, rp_osc_meas_res_t *ch2_meas,
float ch1_max_adc_v, float ch2_max_adc_v,
float ch1_user_dc_off, float ch2_user_dc_off)
{
int t_start_idx, t_stop_idx;
float smpl_period = c_osc_fpga_smpl_period * dec_factor;
int t_unit_factor = rp_osc_get_time_unit_factor(time_unit);
int t_step;
int in_idx, out_idx, t_idx;
int wr_ptr_curr, wr_ptr_trig;
float *cha_s = *cha_signal;
float *chb_s = *chb_signal;
float *t = *time_signal;
/* If illegal take whole frame */
if(t_stop <= t_start) {
t_start = 0;
t_stop = (OSC_FPGA_SIG_LEN-1) * smpl_period;
}
/* convert time to samples */
t_start_idx = round(t_start / smpl_period);
t_stop_idx = round(t_stop / smpl_period);
if((((t_stop_idx-t_start_idx)/(float)(SIGNAL_LENGTH-1))) < 1)
t_step = 1;
else {
/* ceil was used already in rp_osc_main() for parameters, so we can easily
* use round() here
*/
t_step = round((t_stop_idx-t_start_idx)/(float)(SIGNAL_LENGTH-1));
}
osc_fpga_get_wr_ptr(&wr_ptr_curr, &wr_ptr_trig);
in_idx = wr_ptr_trig + t_start_idx - 3;
if(in_idx < 0)
in_idx = OSC_FPGA_SIG_LEN + in_idx;
if(in_idx >= OSC_FPGA_SIG_LEN)
in_idx = in_idx % OSC_FPGA_SIG_LEN;
/* First perform measurements on non-decimated signal:
* - min, max - performed in the loop
* - avg, amp - performed after the loop
* - freq, period - performed in the next decimation loop
*/
for(out_idx=0; out_idx < OSC_FPGA_SIG_LEN; out_idx++) {
rp_osc_meas_min_max(ch1_meas, in_cha_signal[out_idx]);
rp_osc_meas_min_max(ch2_meas, in_chb_signal[out_idx]);
}
for(out_idx=0, t_idx=0; out_idx < SIGNAL_LENGTH;
out_idx++, in_idx+=t_step, t_idx+=t_step) {
/* Wrap the pointer */
if(in_idx >= OSC_FPGA_SIG_LEN)
in_idx = in_idx % OSC_FPGA_SIG_LEN;
cha_s[out_idx] = osc_fpga_cnv_cnt_to_v_with_calib(in_cha_signal[in_idx], ch1_max_adc_v,
wrkr_rp_calib_params->fe_ch1_dc_offs,
ch1_user_dc_off);
chb_s[out_idx] = osc_fpga_cnv_cnt_to_v_with_calib(in_chb_signal[in_idx], ch2_max_adc_v,
wrkr_rp_calib_params->fe_ch2_dc_offs,
ch2_user_dc_off);
t[out_idx] = (t_start + (t_idx * smpl_period)) * t_unit_factor;
/* A bug in FPGA? - Trig & write pointers not sample-accurate. */
if ( (dec_factor > 64) && (out_idx == 1) ) {
int i;
for (i=0; i < out_idx; i++) {
cha_s[i] = cha_s[out_idx];
chb_s[i] = chb_s[out_idx];
}
}
}
return 0;
}
/*----------------------------------------------------------------------------------*/
int rp_osc_decimate_partial(float **cha_out_signal, int *cha_in_signal,
float **chb_out_signal, int *chb_in_signal,
float **time_out_signal, int *next_wr_ptr,
int last_wr_ptr, int step_wr_ptr, int next_out_idx,
float t_start, int dec_factor, int time_unit,
rp_osc_meas_res_t *ch1_meas,
rp_osc_meas_res_t *ch2_meas,
float ch1_max_adc_v, float ch2_max_adc_v,
float ch1_user_dc_off, float ch2_user_dc_off)
{
float *cha_out = *cha_out_signal;
float *chb_out = *chb_out_signal;
float *t_out = *time_out_signal;
int in_idx = *next_wr_ptr;
float smpl_period = c_osc_fpga_smpl_period * dec_factor;
int t_unit_factor = rp_osc_get_time_unit_factor(time_unit);
int curr_ptr;
/* check if we have reached currently acquired signals in FPGA */
osc_fpga_get_wr_ptr(&curr_ptr, NULL);
for(; in_idx < curr_ptr; in_idx++) {
if(in_idx >= OSC_FPGA_SIG_LEN)
in_idx = in_idx % OSC_FPGA_SIG_LEN;
rp_osc_meas_min_max(ch1_meas, cha_in_signal[in_idx]);
rp_osc_meas_min_max(ch2_meas, chb_in_signal[in_idx]);
}
in_idx = *next_wr_ptr;
for(; (next_out_idx < ((int)rp_get_params_bode(5))); next_out_idx++,
in_idx += step_wr_ptr) {
int curr_ptr;
int diff_ptr;
/* check if we have reached currently acquired signals in FPGA */
osc_fpga_get_wr_ptr(&curr_ptr, NULL);
if(in_idx >= OSC_FPGA_SIG_LEN)
in_idx = in_idx % OSC_FPGA_SIG_LEN;
diff_ptr = (in_idx-curr_ptr);
/* Check that we did not hit the curr ptr (and that pointer is not
* wrapped
*/
if((in_idx >= curr_ptr) && (diff_ptr > 0) && (diff_ptr < 100))
break;
cha_out[next_out_idx] =
osc_fpga_cnv_cnt_to_v(cha_in_signal[in_idx], ch1_max_adc_v,
rp_calib_params->fe_ch1_dc_offs,
ch1_user_dc_off);
chb_out[next_out_idx] =
osc_fpga_cnv_cnt_to_v(chb_in_signal[in_idx], ch2_max_adc_v,
rp_calib_params->fe_ch1_dc_offs,
ch2_user_dc_off);
t_out[next_out_idx] =
(t_start + ((next_out_idx*step_wr_ptr)*smpl_period))*t_unit_factor;
/* A bug in FPGA? - Trig & write pointers not sample-accurate. */
if ( (dec_factor > 64) && (next_out_idx == 2) ) {
int i;
for (i=0; i < next_out_idx; i++) {
cha_out[i] = cha_out[next_out_idx];
chb_out[i] = chb_out[next_out_idx];
}
}
}
*next_wr_ptr = in_idx;
return next_out_idx;
}
/* Main worker thread */
void *rp_osc_worker_thread(void *args)
{
rp_osc_worker_state_t old_state, state;
rp_app_params_t *curr_params = NULL;
int fpga_update = 0;
int dec_factor = 0;
int time_vect_update = 0;
uint32_t trig_source = 0;
int params_dirty = 0;
/* Long acquisition special function */
int long_acq = 0; /* long_acq if acq_time > 1 [s] */
int long_acq_idx = 0;
int long_acq_first_wr_ptr = 0;
int long_acq_last_wr_ptr = 0;
int long_acq_step = 0;
int long_acq_init_trig_ptr;
rp_osc_meas_res_t ch1_meas, ch2_meas;
float ch1_max_adc_v = 1, ch2_max_adc_v = 1;
float max_adc_norm = osc_fpga_calc_adc_max_v(rp_calib_params->fe_ch1_fs_g_hi, 0);
pthread_mutex_lock(&rp_osc_ctrl_mutex);
old_state = state = rp_osc_ctrl;
pthread_mutex_unlock(&rp_osc_ctrl_mutex);
while(1) {
/* update states - we also save old state to see if we need to reset
* FPGA
*/
int start_measure = rp_get_params_bode(0);
if(start_measure == 1){
char command[100];
float read_amp = rp_get_params_bode(1);
float read_avg = rp_get_params_bode(2);
float read_dc_bias = rp_get_params_bode(3);
float read_start_freq = rp_get_params_bode(4);
float read_counts = rp_get_params_bode(5);
float read_scale = rp_get_params_bode(6);
float read_end_freq = rp_get_params_bode(9);
char amp[5];
char avg[5];
char dc_bias[5];
char s_freq[20];
char e_freq[20];
char scale[5];
char counts[5];
snprintf(amp, 5, "%f", read_amp);
snprintf(avg, 5, "%f", read_avg);
snprintf(dc_bias, 5, "%f", read_dc_bias);
snprintf(s_freq, 20, "%f", read_start_freq);
snprintf(e_freq,20, "%f", read_end_freq);
snprintf(scale, 5, "%f", read_scale);
snprintf(counts, 5, "%f", read_counts);
strcpy(command, "/opt/www/apps/bode_plotter/bode 1 ");
strcat(command, amp);
strcat(command, " ");
strcat(command, dc_bias);
strcat(command, " ");
strcat(command, avg);
strcat(command, " ");
strcat(command, counts);
strcat(command, " ");
strcat(command, s_freq);
strcat(command, " ");
strcat(command, e_freq);
strcat(command, " ");
strcat(command, scale);
system(command);
rp_set_params_bode(0, 0);
}
old_state = state;
pthread_mutex_lock(&rp_osc_ctrl_mutex);
state = rp_osc_ctrl;
/* If there are no new params */
if(rp_osc_params_dirty) {
rp_copy_params(rp_osc_params, (rp_app_params_t **)&curr_params);
fpga_update = rp_osc_params_fpga_update;
rp_osc_params_dirty = 0;
dec_factor =
osc_fpga_cnv_time_range_to_dec(curr_params[TIME_RANGE_PARAM].value);
time_vect_update = 1;
uint32_t fe_fsg1 = (curr_params[GAIN_CH1].value == 0) ?
rp_calib_params->fe_ch1_fs_g_hi :
rp_calib_params->fe_ch1_fs_g_lo;
ch1_max_adc_v =
osc_fpga_calc_adc_max_v(fe_fsg1, (int)curr_params[PRB_ATT_CH1].value);
uint32_t fe_fsg2 = (curr_params[GAIN_CH2].value == 0) ?
rp_calib_params->fe_ch2_fs_g_hi :
rp_calib_params->fe_ch2_fs_g_lo;
ch2_max_adc_v =
osc_fpga_calc_adc_max_v(fe_fsg2, (int)curr_params[PRB_ATT_CH2].value);
}
pthread_mutex_unlock(&rp_osc_ctrl_mutex);
/* request to stop worker thread, we will shut down */
if(state == rp_osc_quit_state) {
rp_clean_params(curr_params);
return 0;
}
if(state == rp_osc_auto_set_state) {
/* Auto-set algorithm was selected - run it */
rp_osc_auto_set(curr_params, ch1_max_adc_v, ch2_max_adc_v,
curr_params[GEN_DC_OFFS_1].value,
curr_params[GEN_DC_OFFS_2].value,
curr_params[PRB_ATT_CH1].value,
curr_params[PRB_ATT_CH2].value,
curr_params[GAIN_CH1].value,
curr_params[GAIN_CH2].value,
curr_params[EN_AVG_AT_DEC].value);
/* Return calculated parameters to main module */
rp_update_main_params(curr_params);
/* while(1) - loop until break */
continue;
}
if(fpga_update) {
/* Reset write state machine? LG */
osc_fpga_reset();
if(osc_fpga_update_params((curr_params[TRIG_MODE_PARAM].value == 0),
curr_params[TRIG_SRC_PARAM].value,
curr_params[TRIG_EDGE_PARAM].value,
/* Here we could use trigger, but it is safer
* to use start GUI value (it was recalculated
* correctly already in rp_osc_main() so we
* can use it and be sure that all signal
* (even if extended because of decimation
* will be covered in the acquisition
*/
/*curr_params[TRIG_DLY_PARAM].value,*/
curr_params[MIN_GUI_PARAM].value,
curr_params[TRIG_LEVEL_PARAM].value,
curr_params[TIME_RANGE_PARAM].value,
max_adc_norm, max_adc_norm,
rp_calib_params->fe_ch1_dc_offs,
curr_params[GEN_DC_OFFS_1].value,
rp_calib_params->fe_ch2_dc_offs,
curr_params[GEN_DC_OFFS_2].value,
curr_params[PRB_ATT_CH1].value,
curr_params[PRB_ATT_CH2].value,
curr_params[GAIN_CH1].value,
curr_params[GAIN_CH2].value,
curr_params[EN_AVG_AT_DEC].value) < 0) {
fprintf(stderr, "Setting of FPGA registers failed\n");
rp_osc_worker_change_state(rp_osc_idle_state);
}
trig_source = osc_fpga_cnv_trig_source(
(curr_params[TRIG_MODE_PARAM].value == 0),
curr_params[TRIG_SRC_PARAM].value,
curr_params[TRIG_EDGE_PARAM].value);
fpga_update = 0;
}
if(state == rp_osc_idle_state) {
usleep(10000);
continue;
}
/* Time vector update? */
if(time_vect_update) {
float unit_factor =
rp_osc_get_time_unit_factor(curr_params[TIME_UNIT_PARAM].value);
float t_acq = (curr_params[MAX_GUI_PARAM].value -
curr_params[MIN_GUI_PARAM].value) / unit_factor;
rp_osc_prepare_time_vector((float **)&rp_tmp_signals[0],
dec_factor,
curr_params[MIN_GUI_PARAM].value,
curr_params[MAX_GUI_PARAM].value,
curr_params[TIME_UNIT_PARAM].value);
time_vect_update = 0;
/* check if we have long acquisition - if yes the algorithm
* (wait for pre-defined time and return partial signal) */
/* TODO: Make it programmable */
if(t_acq >= 1.5) {
long_acq = 1;
/* Catch initial trigger - we will poll trigger pointer,
* when it changes we will act like official 'trigger'
* came
*/
rp_osc_meas_clear(&ch1_meas);
rp_osc_meas_clear(&ch2_meas);
osc_fpga_get_wr_ptr(NULL, &long_acq_init_trig_ptr);
} else {
long_acq_first_wr_ptr = 0;
long_acq_last_wr_ptr = 0;
long_acq = 0;
}
long_acq_idx = 0;
}
/* Start new acquisition only if it is the index 0 (new acquisition) */
if(long_acq_idx == 0) {
float time_delay = curr_params[TRIG_DLY_PARAM].value;
/* Start the writting machine */
osc_fpga_arm_trigger();
/* Be sure to have enough time to load necessary history - wait */
if(time_delay < 0) {
/* time delay is always in seconds - convert to [us] and
* sleep
*/
usleep(round(-1 * time_delay * 1e6));
} else {
if(curr_params[TIME_RANGE_PARAM].value > 4)
usleep(5000);
else
usleep(1);
}
/* Start the trigger */
osc_fpga_set_trigger(trig_source);
}
/* start working */
pthread_mutex_lock(&rp_osc_ctrl_mutex);
old_state = state = rp_osc_ctrl;
pthread_mutex_unlock(&rp_osc_ctrl_mutex);
if((state == rp_osc_idle_state) || (state == rp_osc_abort_state)) {
continue;
} else if(state == rp_osc_quit_state) {
break;
}
if(long_acq_idx == 0) {
/* polling until data is ready */
while(1) {
pthread_mutex_lock(&rp_osc_ctrl_mutex);
state = rp_osc_ctrl;
params_dirty = rp_osc_params_dirty;
pthread_mutex_unlock(&rp_osc_ctrl_mutex);
/* change in state, abort polling */
if((state != old_state) || params_dirty) {
break;
}
if(!long_acq && osc_fpga_triggered()) {
/* for non-long acquisition wait for trigger */
break;
} else if(long_acq) {
int trig_ptr, curr_ptr;
osc_fpga_get_wr_ptr(&curr_ptr, &trig_ptr);
if((long_acq_init_trig_ptr != trig_ptr) || osc_fpga_triggered()) {
/* FPGA wrote new trigger pointer - which means
* new trigger happened
*/
break;
}
}
usleep(1000);
}
}
if((state != old_state) || params_dirty) {
params_dirty = 0;
continue;
}
if(long_acq) {
/* Long acquisition - after trigger wait for a while to collect some
* data
*/
/* TODO: Make it programmable - Sleep for 200 [ms] */
const int long_acq_part_delay = 1000 * 200;
if(long_acq_idx == 0) {
/* Trigger - so let's arrange all the needed pointers & stuff */
int wr_ptr_curr, wr_ptr_trig;
float smpl_period = c_osc_fpga_smpl_period * dec_factor;
int t_start_idx =
round(curr_params[MIN_GUI_PARAM].value / smpl_period);
float unit_factor =
rp_osc_get_time_unit_factor(
curr_params[TIME_UNIT_PARAM].value);
float t_acq = (curr_params[MAX_GUI_PARAM].value -
curr_params[MIN_GUI_PARAM].value) /
unit_factor;
osc_fpga_get_wr_ptr(&wr_ptr_curr, &wr_ptr_trig);
long_acq_first_wr_ptr = wr_ptr_trig + t_start_idx - 3;
if(long_acq_first_wr_ptr < 0)
long_acq_first_wr_ptr =
OSC_FPGA_SIG_LEN + long_acq_first_wr_ptr;
long_acq_last_wr_ptr = long_acq_first_wr_ptr +
(t_acq / (c_osc_fpga_smpl_period * dec_factor));
long_acq_last_wr_ptr = long_acq_last_wr_ptr % OSC_FPGA_SIG_LEN;
if(round((t_acq / (c_osc_fpga_smpl_period * dec_factor) /
(((int)rp_get_params_bode(5))-1))) < 0)
long_acq_step = 1;
else
long_acq_step =
round((t_acq / (c_osc_fpga_smpl_period * dec_factor)) /
(((int)rp_get_params_bode(5))-1));
rp_osc_meas_clear(&ch1_meas);
rp_osc_meas_clear(&ch2_meas);
}
/* we are after trigger - so let's wait a while to collect some
* samples */
usleep(long_acq_part_delay); /* Sleep for 200 [ms] */
}
pthread_mutex_lock(&rp_osc_ctrl_mutex);
state = rp_osc_ctrl;
params_dirty = rp_osc_params_dirty;
pthread_mutex_unlock(&rp_osc_ctrl_mutex);
if((state != old_state) || params_dirty)
continue;
if(!long_acq) {
/* Triggered, decimate & convert the values */
rp_osc_meas_clear(&ch1_meas);
rp_osc_meas_clear(&ch2_meas);
bode_start_measure((float **)&rp_tmp_signals[1], &rp_fpga_cha_signal[0],
(float **)&rp_tmp_signals[2], &rp_fpga_chb_signal[0],
(float **)&rp_tmp_signals[0]);
} else {
long_acq_idx = rp_osc_decimate_partial((float **)&rp_tmp_signals[1],
&rp_fpga_cha_signal[0],
(float **)&rp_tmp_signals[2],
&rp_fpga_chb_signal[0],
(float **)&rp_tmp_signals[0],
&long_acq_first_wr_ptr,
long_acq_last_wr_ptr,
long_acq_step, long_acq_idx,
curr_params[MIN_GUI_PARAM].value,
dec_factor,
curr_params[TIME_UNIT_PARAM].value,
&ch1_meas, &ch2_meas,
ch1_max_adc_v, ch2_max_adc_v,
curr_params[GEN_DC_OFFS_1].value,
curr_params[GEN_DC_OFFS_2].value);
/* Acquisition over, start one more! */
if(long_acq_idx >= ((int)rp_get_params_bode(5))-1) {
long_acq_idx = 0;
osc_fpga_get_wr_ptr(NULL, &long_acq_init_trig_ptr);
if(state == rp_osc_single_state) {
rp_osc_worker_change_state(rp_osc_idle_state);
}
}
}
/* check again for change of state */
pthread_mutex_lock(&rp_osc_ctrl_mutex);
state = rp_osc_ctrl;
pthread_mutex_unlock(&rp_osc_ctrl_mutex);
/* We have acquisition - if we are in single put state machine
* to idle */
if((state == rp_osc_single_state) && (!long_acq)) {
rp_osc_worker_change_state(rp_osc_idle_state);
}
/* copy the results to the user buffer - if we are finished or not */
if(!long_acq || long_acq_idx == 0) {
/* Finish the measurement */
rp_osc_meas_avg_amp(&ch1_meas, OSC_FPGA_SIG_LEN);
rp_osc_meas_avg_amp(&ch2_meas, OSC_FPGA_SIG_LEN);
rp_osc_meas_period(&ch1_meas, &ch2_meas, &rp_fpga_cha_signal[0],
&rp_fpga_chb_signal[0], dec_factor);
rp_osc_meas_convert(&ch1_meas, ch1_max_adc_v, rp_calib_params->fe_ch1_dc_offs);
rp_osc_meas_convert(&ch2_meas, ch2_max_adc_v, rp_calib_params->fe_ch2_dc_offs);
rp_osc_set_meas_data(ch1_meas, ch2_meas);
rp_osc_set_signals(rp_tmp_signals, ((int)rp_get_params_bode(5))-1);
} else {
rp_osc_set_signals(rp_tmp_signals, long_acq_idx);
}
/* do not loop too fast */
usleep(10000);
}
rp_clean_params(curr_params);
return 0;
}
