/* * Initialize rtNaN needed by the generated code. * NaN is initialized as non-signaling. Assumes IEEE. */ real_T rtGetNaN(void) { size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar); real_T nan = 0.0; if (bitsPerReal == 32U) { nan = rtGetNaNF(); } else { union { LittleEndianIEEEDouble bitVal; real_T fltVal; } tmpVal; tmpVal.bitVal.words.wordH = 0xFFF80000U; tmpVal.bitVal.words.wordL = 0x00000000U; nan = tmpVal.fltVal; } return nan; }
/* * Initialize rtNaN needed by the generated code. * NaN is initialized as non-signaling. Assumes IEEE. */ real_T rtGetNaN(void) { size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar); real_T nan = 0.0; if (bitsPerReal == 32U) { nan = rtGetNaNF(); } else { uint16_T one = 1U; enum { LittleEndian, BigEndian } machByteOrder = (*((uint8_T *) &one) == 1U) ? LittleEndian : BigEndian; switch (machByteOrder) { case LittleEndian: { union { LittleEndianIEEEDouble bitVal; real_T fltVal; } tmpVal; tmpVal.bitVal.words.wordH = 0xFFF80000U; tmpVal.bitVal.words.wordL = 0x00000000U; nan = tmpVal.fltVal; break; } case BigEndian: { union { BigEndianIEEEDouble bitVal; real_T fltVal; } tmpVal; tmpVal.bitVal.words.wordH = 0x7FFFFFFFU; tmpVal.bitVal.words.wordL = 0xFFFFFFFFU; nan = tmpVal.fltVal; break; } } } return nan; }
rtMinusInfF ; real32_T rtNaNF ; void rt_InitInfAndNaN ( size_t realSize ) { ( void ) ( realSize ) ; rtNaN = rtGetNaN ( ) ; rtNaNF = rtGetNaNF ( ) ; rtInf = rtGetInf ( ) ; rtInfF = rtGetInfF ( ) ; rtMinusInf = rtGetMinusInf ( ) ; rtMinusInfF = rtGetMinusInfF ( ) ; } boolean_T rtIsInf ( real_T value ) {