/* Reload the hardware state from a saved domain */
static int rtc_load(struct domain *d, hvm_domain_context_t *h)
{
RTCState *s = domain_vrtc(d);
if ( !has_vrtc(d) )
return -ENODEV;
spin_lock(&s->lock);
/* Restore the registers */
if ( hvm_load_entry(RTC, h, &s->hw) != 0 )
{
spin_unlock(&s->lock);
return -EINVAL;
}
/* Reset the wall-clock time. In normal running, this runs with host
* time, so let's keep doing that. */
s->current_tm = gmtime(get_localtime(d));
rtc_copy_date(s);
/* Reset the periodic interrupt timer based on the registers */
rtc_timer_update(s);
check_update_timer(s);
alarm_timer_update(s);
spin_unlock(&s->lock);
return 0;
}
void rtc_init(struct domain *d)
{
RTCState *s = domain_vrtc(d);
if ( !has_vrtc(d) )
return;
spin_lock_init(&s->lock);
init_timer(&s->update_timer, rtc_update_timer, s, smp_processor_id());
init_timer(&s->update_timer2, rtc_update_timer2, s, smp_processor_id());
init_timer(&s->alarm_timer, rtc_alarm_cb, s, smp_processor_id());
register_portio_handler(d, RTC_PORT(0), 2, handle_rtc_io);
rtc_reset(d);
spin_lock(&s->lock);
s->hw.cmos_data[RTC_REG_A] = RTC_REF_CLCK_32KHZ | 6; /* ~1kHz */
s->hw.cmos_data[RTC_REG_B] = RTC_24H;
s->hw.cmos_data[RTC_REG_C] = 0;
s->hw.cmos_data[RTC_REG_D] = RTC_VRT;
s->current_tm = gmtime(get_localtime(d));
s->start_time = NOW();
rtc_copy_date(s);
check_update_timer(s);
spin_unlock(&s->lock);
}
static void rtc_update_second2(void *opaque)
{
RTCState *s = opaque;
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
rtc_copy_date(s);
}
/* check alarm */
if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
s->cmos_data[RTC_REG_C] |= 0xa0;
rtc_irq_raise(s->irq);
}
}
/* update ended interrupt */
if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
s->cmos_data[RTC_REG_C] |= 0x90;
rtc_irq_raise(s->irq);
}
/* clear update in progress bit */
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
s->next_second_time += ticks_per_sec;
qemu_mod_timer(s->second_timer, s->next_second_time);
}
static uint32_t rtc_ioport_read(RTCState *s, uint32_t addr)
{
int ret;
struct domain *d = vrtc_domain(s);
if ( (addr & 1) == 0 )
return 0xff;
spin_lock(&s->lock);
switch ( s->hw.cmos_index )
{
case RTC_SECONDS:
case RTC_MINUTES:
case RTC_HOURS:
case RTC_DAY_OF_WEEK:
case RTC_DAY_OF_MONTH:
case RTC_MONTH:
case RTC_YEAR:
/* if not in set mode, adjust cmos before reading*/
if (!(s->hw.cmos_data[RTC_REG_B] & RTC_SET))
{
s->current_tm = gmtime(get_localtime(d));
rtc_copy_date(s);
}
ret = s->hw.cmos_data[s->hw.cmos_index];
break;
case RTC_REG_A:
ret = s->hw.cmos_data[s->hw.cmos_index];
if ((s->use_timer == 0) && update_in_progress(s))
ret |= RTC_UIP;
break;
case RTC_REG_C:
check_for_pf_ticks(s);
ret = s->hw.cmos_data[s->hw.cmos_index];
s->hw.cmos_data[RTC_REG_C] = 0x00;
if ( ret & RTC_IRQF )
hvm_isa_irq_deassert(d, RTC_IRQ);
check_update_timer(s);
alarm_timer_update(s);
s->pt_dead_ticks = 0;
break;
default:
ret = s->hw.cmos_data[s->hw.cmos_index];
break;
}
spin_unlock(&s->lock);
return ret;
}
static void rtc_update_second2(void *opaque)
{
RTCState *s = opaque;
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
rtc_copy_date(s);
}
/* check alarm */
if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) &&
((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) &&
((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) {
s->cmos_data[RTC_REG_C] |= REG_C_AF;
if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
qemu_irq_raise(s->irq);
s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
}
}
/* update ended interrupt */
s->cmos_data[RTC_REG_C] |= REG_C_UF;
if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
qemu_irq_raise(s->irq);
}
/* clear update in progress bit */
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
s->next_second_time += get_ticks_per_sec();
qemu_mod_timer(s->second_timer, s->next_second_time);
}
static int rtc_ioport_write(void *opaque, uint32_t addr, uint32_t data)
{
RTCState *s = opaque;
struct domain *d = vrtc_domain(s);
uint32_t orig;
spin_lock(&s->lock);
if ( (addr & 1) == 0 )
{
data &= 0x7f;
s->hw.cmos_index = data;
spin_unlock(&s->lock);
return (data < RTC_CMOS_SIZE);
}
if ( s->hw.cmos_index >= RTC_CMOS_SIZE )
{
spin_unlock(&s->lock);
return 0;
}
orig = s->hw.cmos_data[s->hw.cmos_index];
switch ( s->hw.cmos_index )
{
case RTC_SECONDS_ALARM:
case RTC_MINUTES_ALARM:
case RTC_HOURS_ALARM:
s->hw.cmos_data[s->hw.cmos_index] = data;
alarm_timer_update(s);
break;
case RTC_SECONDS:
case RTC_MINUTES:
case RTC_HOURS:
case RTC_DAY_OF_WEEK:
case RTC_DAY_OF_MONTH:
case RTC_MONTH:
case RTC_YEAR:
/* if in set mode, just write the register */
if ( (s->hw.cmos_data[RTC_REG_B] & RTC_SET) )
s->hw.cmos_data[s->hw.cmos_index] = data;
else
{
/* Fetch the current time and update just this field. */
s->current_tm = gmtime(get_localtime(d));
rtc_copy_date(s);
s->hw.cmos_data[s->hw.cmos_index] = data;
rtc_set_time(s);
}
alarm_timer_update(s);
break;
case RTC_REG_A:
/* UIP bit is read only */
s->hw.cmos_data[RTC_REG_A] = (data & ~RTC_UIP) | (orig & RTC_UIP);
if ( (data ^ orig) & ~RTC_UIP )
rtc_timer_update(s);
break;
case RTC_REG_B:
if ( data & RTC_SET )
{
/* set mode: reset UIP mode */
s->hw.cmos_data[RTC_REG_A] &= ~RTC_UIP;
/* adjust cmos before stopping */
if (!(orig & RTC_SET))
{
s->current_tm = gmtime(get_localtime(d));
rtc_copy_date(s);
}
}
else
{
/* if disabling set mode, update the time */
if ( orig & RTC_SET )
rtc_set_time(s);
}
check_for_pf_ticks(s);
s->hw.cmos_data[RTC_REG_B] = data;
/*
* If the interrupt is already set when the interrupt becomes
* enabled, raise an interrupt immediately.
*/
rtc_update_irq(s);
if ( (data ^ orig) & RTC_PIE )
{
TRACE_0D(TRC_HVM_EMUL_RTC_STOP_TIMER);
destroy_periodic_time(&s->pt);
s->period = 0;
rtc_timer_update(s);
}
if ( (data ^ orig) & RTC_SET )
check_update_timer(s);
if ( (data ^ orig) & (RTC_24H | RTC_DM_BINARY | RTC_SET) )
alarm_timer_update(s);
break;
case RTC_REG_C:
case RTC_REG_D:
/* cannot write to them */
break;
}
spin_unlock(&s->lock);
return 1;
}
/* handle alarm timer */
static void alarm_timer_update(RTCState *s)
{
uint64_t next_update_time, next_alarm_sec;
uint64_t expire_time;
int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
int32_t hour, min;
struct domain *d = vrtc_domain(s);
ASSERT(spin_is_locked(&s->lock));
stop_timer(&s->alarm_timer);
if (!(s->hw.cmos_data[RTC_REG_C] & RTC_AF) &&
!(s->hw.cmos_data[RTC_REG_B] & RTC_SET))
{
s->current_tm = gmtime(get_localtime(d));
rtc_copy_date(s);
alarm_sec = from_bcd(s, s->hw.cmos_data[RTC_SECONDS_ALARM]);
alarm_min = from_bcd(s, s->hw.cmos_data[RTC_MINUTES_ALARM]);
alarm_hour = convert_hour(s, s->hw.cmos_data[RTC_HOURS_ALARM]);
cur_sec = from_bcd(s, s->hw.cmos_data[RTC_SECONDS]);
cur_min = from_bcd(s, s->hw.cmos_data[RTC_MINUTES]);
cur_hour = convert_hour(s, s->hw.cmos_data[RTC_HOURS]);
next_update_time = USEC_PER_SEC - (get_localtime_us(d) % USEC_PER_SEC);
next_update_time = next_update_time * NS_PER_USEC + NOW();
if ((s->hw.cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0)
{
if ((s->hw.cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0)
{
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec = 1;
else if (cur_sec < alarm_sec)
next_alarm_sec = alarm_sec - cur_sec;
else
next_alarm_sec = alarm_sec + SEC_PER_MIN - cur_sec;
}
else
{
if (cur_min < alarm_min)
{
min = alarm_min - cur_min;
next_alarm_sec = min * SEC_PER_MIN - cur_sec;
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec += 0;
else
next_alarm_sec += alarm_sec;
}
else if (cur_min == alarm_min)
{
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec = 1;
else if (cur_sec < alarm_sec)
next_alarm_sec = alarm_sec - cur_sec;
else
{
min = alarm_min + MIN_PER_HOUR - cur_min;
next_alarm_sec =
alarm_sec + min * SEC_PER_MIN - cur_sec;
}
}
else
{
min = alarm_min + MIN_PER_HOUR - cur_min;
next_alarm_sec = min * SEC_PER_MIN - cur_sec;
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec += 0;
else
next_alarm_sec += alarm_sec;
}
}
}
else
{
if (cur_hour < alarm_hour)
{
hour = alarm_hour - cur_hour;
next_alarm_sec = hour * SEC_PER_HOUR -
cur_min * SEC_PER_MIN - cur_sec;
if ((s->hw.cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0)
{
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec += 0;
else
next_alarm_sec += alarm_sec;
}
else
{
next_alarm_sec += alarm_min * SEC_PER_MIN;
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec += 0;
else
next_alarm_sec += alarm_sec;
}
}
else if (cur_hour == alarm_hour)
{
if ((s->hw.cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0)
{
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec = 1;
else if (cur_sec < alarm_sec)
next_alarm_sec = alarm_sec - cur_sec;
else
next_alarm_sec = alarm_sec + SEC_PER_MIN - cur_sec;
}
else if (cur_min < alarm_min)
{
min = alarm_min - cur_min;
next_alarm_sec = min * SEC_PER_MIN - cur_sec;
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec += 0;
else
next_alarm_sec += alarm_sec;
}
else if (cur_min == alarm_min)
{
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec = 1;
else if (cur_sec < alarm_sec)
next_alarm_sec = alarm_sec - cur_sec;
else
{
hour = alarm_hour + HOUR_PER_DAY - cur_hour;
next_alarm_sec = hour * SEC_PER_HOUR -
cur_min * SEC_PER_MIN - cur_sec;
next_alarm_sec += alarm_min * SEC_PER_MIN + alarm_sec;
}
}
else
{
hour = alarm_hour + HOUR_PER_DAY - cur_hour;
next_alarm_sec = hour * SEC_PER_HOUR -
cur_min * SEC_PER_MIN - cur_sec;
next_alarm_sec += alarm_min * SEC_PER_MIN;
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec += 0;
else
next_alarm_sec += alarm_sec;
}
}
else
{
hour = alarm_hour + HOUR_PER_DAY - cur_hour;
next_alarm_sec = hour * SEC_PER_HOUR -
cur_min * SEC_PER_MIN - cur_sec;
if ((s->hw.cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0)
{
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec += 0;
else
next_alarm_sec += alarm_sec;
}
else
{
next_alarm_sec += alarm_min * SEC_PER_MIN;
if ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0)
next_alarm_sec += 0;
else
next_alarm_sec += alarm_sec;
}
}
}
expire_time = (next_alarm_sec - 1) * NS_PER_SEC + next_update_time;
/* release lock before set timer */
spin_unlock(&s->lock);
set_timer(&s->alarm_timer, expire_time);
/* fetch lock again */
spin_lock(&s->lock);
}
}
void rtc_set_date(RTCState *s, const struct tm *tm)
{
s->current_tm = *tm;
rtc_copy_date(s);
}
void rtc_set_date(ISADevice *dev, const struct tm *tm)
{
RTCState *s = DO_UPCAST(RTCState, dev, dev);
s->current_tm = *tm;
rtc_copy_date(s);
}
static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
{
RTCState *s = opaque;
if ((addr & 1) == 0) {
s->cmos_index = data & 0x7f;
} else {
CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
s->cmos_index, data);
switch(s->cmos_index) {
case RTC_SECONDS_ALARM:
case RTC_MINUTES_ALARM:
case RTC_HOURS_ALARM:
s->cmos_data[s->cmos_index] = data;
break;
case RTC_SECONDS:
case RTC_MINUTES:
case RTC_HOURS:
case RTC_DAY_OF_WEEK:
case RTC_DAY_OF_MONTH:
case RTC_MONTH:
case RTC_YEAR:
s->cmos_data[s->cmos_index] = data;
/* if in set mode, do not update the time */
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
rtc_set_time(s);
}
break;
case RTC_REG_A:
/* UIP bit is read only */
s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
(s->cmos_data[RTC_REG_A] & REG_A_UIP);
rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
break;
case RTC_REG_B:
if (data & REG_B_SET) {
/* set mode: reset UIP mode */
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
data &= ~REG_B_UIE;
} else {
/* if disabling set mode, update the time */
if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
rtc_set_time(s);
}
}
if (((s->cmos_data[RTC_REG_B] ^ data) & (REG_B_DM | REG_B_24H)) &&
!(data & REG_B_SET)) {
/* If the time format has changed and not in set mode,
update the registers immediately. */
s->cmos_data[RTC_REG_B] = data;
rtc_copy_date(s);
} else {
s->cmos_data[RTC_REG_B] = data;
}
rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
break;
case RTC_REG_C:
case RTC_REG_D:
/* cannot write to them */
break;
default:
s->cmos_data[s->cmos_index] = data;
break;
}
}
}
static int rtc_ioport_write(void *opaque, uint32_t addr, uint32_t data)
{
RTCState *s = opaque;
struct domain *d = vrtc_domain(s);
uint32_t orig;
spin_lock(&s->lock);
if ( (addr & 1) == 0 )
{
data &= 0x7f;
s->hw.cmos_index = data;
spin_unlock(&s->lock);
return (data < RTC_CMOS_SIZE);
}
if ( s->hw.cmos_index >= RTC_CMOS_SIZE )
{
spin_unlock(&s->lock);
return 0;
}
orig = s->hw.cmos_data[s->hw.cmos_index];
switch ( s->hw.cmos_index )
{
case RTC_SECONDS_ALARM:
case RTC_MINUTES_ALARM:
case RTC_HOURS_ALARM:
s->hw.cmos_data[s->hw.cmos_index] = data;
alarm_timer_update(s);
break;
case RTC_SECONDS:
case RTC_MINUTES:
case RTC_HOURS:
case RTC_DAY_OF_WEEK:
case RTC_DAY_OF_MONTH:
case RTC_MONTH:
case RTC_YEAR:
s->hw.cmos_data[s->hw.cmos_index] = data;
/* if in set mode, do not update the time */
if ( !(s->hw.cmos_data[RTC_REG_B] & RTC_SET) )
rtc_set_time(s);
alarm_timer_update(s);
break;
case RTC_REG_A:
/* UIP bit is read only */
s->hw.cmos_data[RTC_REG_A] = (data & ~RTC_UIP) | (orig & RTC_UIP);
if ( (data ^ orig) & ~RTC_UIP )
rtc_timer_update(s);
break;
case RTC_REG_B:
if ( data & RTC_SET )
{
/* set mode: reset UIP mode */
s->hw.cmos_data[RTC_REG_A] &= ~RTC_UIP;
/* adjust cmos before stopping */
if (!(s->hw.cmos_data[RTC_REG_B] & RTC_SET))
{
s->current_tm = gmtime(get_localtime(d));
rtc_copy_date(s);
}
}
else
{
/* if disabling set mode, update the time */
if ( s->hw.cmos_data[RTC_REG_B] & RTC_SET )
rtc_set_time(s);
}
/* if the interrupt is already set when the interrupt become
* enabled, raise an interrupt immediately*/
if ((data & RTC_UIE) && !(s->hw.cmos_data[RTC_REG_B] & RTC_UIE))
if (s->hw.cmos_data[RTC_REG_C] & RTC_UF)
{
hvm_isa_irq_deassert(d, RTC_IRQ);
hvm_isa_irq_assert(d, RTC_IRQ);
}
s->hw.cmos_data[RTC_REG_B] = data;
if ( (data ^ orig) & RTC_PIE )
rtc_timer_update(s);
check_update_timer(s);
alarm_timer_update(s);
break;
case RTC_REG_C:
case RTC_REG_D:
/* cannot write to them */
break;
}
spin_unlock(&s->lock);
return 1;
}
