t_stat mux_reset (DEVICE *dptr)
{
int32 i;
if (mux_dev.flags & DEV_DIS) /* master disabled? */
muxl_dev.flags = muxl_dev.flags | DEV_DIS; /* disable lines */
else muxl_dev.flags = muxl_dev.flags & ~DEV_DIS;
if (mux_unit[MUXC].flags & UNIT_ATT) /* master att? */
rtc_register (RTC_COC, mux_tps, &mux_unit[MUXI]); /* register timer */
else rtc_register (RTC_COC, RTC_HZ_OFF, NULL); /* else dereg */
for (i = 0; i < MUX_LINES; i++) /* reset lines */
mux_reset_ln (i);
return SCPE_OK;
}
t_stat tt_reset (DEVICE *dptr)
{
rtc_register (RTC_TTI, tti_tps, &tt_unit[TTI]); /* register timer */
sim_cancel (&tt_unit[TTO]); /* stop dev thread */
tt_cmd = TTS_IDLE; /* idle */
chan_reset_dev (tt_dib.dva); /* clr int, active */
tto_pos = 0;
return SCPE_OK;
}
t_stat mux_attach (UNIT *uptr, char *cptr)
{
t_stat r;
r = tmxr_attach (&mux_desc, uptr, cptr); /* attach */
if (r != SCPE_OK) /* error */
return r;
rtc_register (RTC_COC, mux_tps, &mux_unit[MUXC]); /* register timer */
return SCPE_OK;
}
static int
rtctimer_open(struct snd_timer *t)
{
int err;
err = rtc_register(&rtc_task);
if (err < 0)
return err;
t->private_data = &rtc_task;
return 0;
}
t_stat mux_detach (UNIT *uptr)
{
int32 i;
t_stat r;
r = tmxr_detach (&mux_desc, uptr); /* detach */
for (i = 0; i < MUX_LINES; i++) /* disable rcv */
mux_reset_ln (i);
rtc_register (RTC_COC, RTC_HZ_OFF, NULL); /* dereg */
return r;
}
t_stat rtc_reset (DEVICE *dptr)
{
uint32 i;
sim_rtcn_init (rtc_unit.wait, TMR_RTC); /* init base clock */
sim_activate_abs (&rtc_unit, rtc_unit.wait); /* activate unit */
for (i = 0; i < RTC_NUM_EVNTS; i++) { /* clear counters */
if (i < RTC_NUM_CNTRS) {
rtc_cntr[i] = 0;
rtc_xtra[i] = 0;
rtc_indx[i] = 0;
rtc_usrv[i] = NULL;
if (rtc_register (i, rtc_tps[i], &rtc_cntr_unit[i]) != SCPE_OK)
return SCPE_IERR;
}
else if ((rtc_usrv[i] != NULL) &&
(rtc_register (i, rtc_indx[i], rtc_usrv[i]) != SCPE_OK))
return SCPE_IERR;
}
return SCPE_OK;
}
