rte_acl_init(void)
{
enum rte_acl_classify_alg alg = RTE_ACL_CLASSIFY_DEFAULT;
#ifdef CC_AVX2_SUPPORT
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
alg = RTE_ACL_CLASSIFY_AVX2;
else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
#else
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
#endif
alg = RTE_ACL_CLASSIFY_SSE;
rte_acl_set_default_classify(alg);
}
/**
* Checks if the machine is adequate for running the binary. If it is not, the
* program exits with status 1.
*/
void
rte_cpu_check_supported(void)
{
/* This is generated at compile-time by the build system */
static const enum rte_cpu_flag_t compile_time_flags[] = {
RTE_COMPILE_TIME_CPUFLAGS
};
unsigned count = RTE_DIM(compile_time_flags), i;
int ret;
for (i = 0; i < count; i++) {
ret = rte_cpu_get_flag_enabled(compile_time_flags[i]);
if (ret < 0) {
fprintf(stderr,
"ERROR: CPU feature flag lookup failed with error %d\n",
ret);
exit(1);
}
if (!ret) {
fprintf(stderr,
"ERROR: This system does not support \"%s\".\n"
"Please check that RTE_MACHINE is set correctly.\n",
rte_cpu_get_flag_name(compile_time_flags[i]));
exit(1);
}
}
}
i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
{
uintptr_t p;
struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
mb_def.nb_segs = 1;
mb_def.data_off = RTE_PKTMBUF_HEADROOM;
mb_def.port = rxq->port_id;
rte_mbuf_refcnt_set(&mb_def, 1);
/* prevent compiler reordering: rearm_data covers previous fields */
rte_compiler_barrier();
p = (uintptr_t)&mb_def.rearm_data;
rxq->mbuf_initializer = *(uint64_t *)p;
return 0;
}
int __attribute__((cold))
i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
{
return 0;
}
int __attribute__((cold))
i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
{
#ifndef RTE_LIBRTE_IEEE1588
struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
/* need SSE4.1 support */
if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
return -1;
#ifndef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
/* whithout rx ol_flags, no VP flag report */
if (rxmode->hw_vlan_strip != 0 ||
rxmode->hw_vlan_extend != 0)
return -1;
#endif
/* no fdir support */
if (fconf->mode != RTE_FDIR_MODE_NONE)
return -1;
/* - no csum error report support
* - no header split support
*/
if (rxmode->hw_ip_checksum == 1 ||
rxmode->header_split == 1)
return -1;
return 0;
#else
RTE_SET_USED(dev);
return -1;
#endif
}
rte_acl_init(void)
{
enum rte_acl_classify_alg alg = RTE_ACL_CLASSIFY_DEFAULT;
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
alg = RTE_ACL_CLASSIFY_SSE;
rte_acl_set_default_classify(alg);
}
rte_acl_init(void)
{
enum rte_acl_classify_alg alg = RTE_ACL_CLASSIFY_DEFAULT;
#if defined(RTE_ARCH_ARM64)
alg = RTE_ACL_CLASSIFY_NEON;
#elif defined(RTE_ARCH_ARM)
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))
alg = RTE_ACL_CLASSIFY_NEON;
#elif defined(RTE_ARCH_PPC_64)
alg = RTE_ACL_CLASSIFY_ALTIVEC;
#else
#ifdef CC_AVX2_SUPPORT
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
alg = RTE_ACL_CLASSIFY_AVX2;
else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
#else
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
#endif
alg = RTE_ACL_CLASSIFY_SSE;
#endif
rte_acl_set_default_classify(alg);
}
/* Initialize the flow table */
static void
flow_table_init(void)
{
/* Check if hardware-accelerated hashing supported */
if (ut_params.hash_func == rte_hash_crc &&
!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_2)) {
RTE_LOG(WARNING, HASH, "CRC32 instruction requires SSE4.2, "
"which is not supported on this system. "
"Falling back to software hash.\n");
ut_params.hash_func = rte_jhash;
}
handle = rte_hash_create(&ut_params);
if (handle == NULL) {
RTE_LOG(WARNING, APP, "Failed to create hash table\n");
exit(EXIT_FAILURE);
}
}
static int
test_cpuflags(void)
{
int result;
printf("\nChecking for flags from different registers...\n");
#ifdef RTE_ARCH_PPC_64
printf("Check for PPC64:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_PPC64);
printf("Check for PPC32:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_PPC32);
printf("Check for VSX:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_VSX);
printf("Check for DFP:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_DFP);
printf("Check for FPU:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_FPU);
printf("Check for SMT:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_SMT);
printf("Check for MMU:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_MMU);
printf("Check for ALTIVEC:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_ALTIVEC);
printf("Check for ARCH_2_06:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_ARCH_2_06);
printf("Check for ARCH_2_07:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_ARCH_2_07);
printf("Check for ICACHE_SNOOP:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_ICACHE_SNOOP);
#endif
#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686)
printf("Check for SSE:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_SSE);
printf("Check for SSE2:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_SSE2);
printf("Check for SSE3:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_SSE3);
printf("Check for SSE4.1:\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_SSE4_1);
printf("Check for SSE4.2:\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_SSE4_2);
printf("Check for AVX:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_AVX);
printf("Check for AVX2:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_AVX2);
printf("Check for TRBOBST:\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_TRBOBST);
printf("Check for ENERGY_EFF:\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_ENERGY_EFF);
printf("Check for LAHF_SAHF:\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_LAHF_SAHF);
printf("Check for 1GB_PG:\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_1GB_PG);
printf("Check for INVTSC:\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
#endif
/*
* Check if invalid data is handled properly
*/
printf("\nCheck for invalid flag:\t");
result = rte_cpu_get_flag_enabled(RTE_CPUFLAG_NUMFLAGS);
printf("%s\n", cpu_flag_result(result));
if (result != -ENOENT)
return -1;
return 0;
}
rte_rtm_init(void)
{
rte_rtm_supported = rte_cpu_get_flag_enabled(RTE_CPUFLAG_RTM);
}
static int
cryptodev_aesni_mb_create(const char *name, unsigned socket_id)
{
struct rte_cryptodev *dev;
char crypto_dev_name[RTE_CRYPTODEV_NAME_MAX_LEN];
struct aesni_mb_private *internals;
enum aesni_mb_vector_mode vector_mode;
/* Check CPU for support for AES instruction set */
if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) {
MB_LOG_ERR("AES instructions not supported by CPU");
return -EFAULT;
}
/* Check CPU for supported vector instruction set */
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
vector_mode = RTE_AESNI_MB_AVX2;
else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX))
vector_mode = RTE_AESNI_MB_AVX;
else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
vector_mode = RTE_AESNI_MB_SSE;
else {
MB_LOG_ERR("Vector instructions are not supported by CPU");
return -EFAULT;
}
/* create a unique device name */
if (create_unique_device_name(crypto_dev_name,
RTE_CRYPTODEV_NAME_MAX_LEN) != 0) {
MB_LOG_ERR("failed to create unique cryptodev name");
return -EINVAL;
}
dev = rte_cryptodev_pmd_virtual_dev_init(crypto_dev_name,
sizeof(struct aesni_mb_private), socket_id);
if (dev == NULL) {
MB_LOG_ERR("failed to create cryptodev vdev");
goto init_error;
}
dev->dev_type = RTE_CRYPTODEV_AESNI_MB_PMD;
dev->dev_ops = rte_aesni_mb_pmd_ops;
/* register rx/tx burst functions for data path */
dev->dequeue_burst = aesni_mb_pmd_dequeue_burst;
dev->enqueue_burst = aesni_mb_pmd_enqueue_burst;
/* Set vector instructions mode supported */
internals = dev->data->dev_private;
internals->vector_mode = vector_mode;
internals->max_nb_queue_pairs = RTE_AESNI_MB_PMD_MAX_NB_QUEUE_PAIRS;
internals->max_nb_sessions = RTE_AESNI_MB_PMD_MAX_NB_SESSIONS;
return dev->data->dev_id;
init_error:
MB_LOG_ERR("driver %s: cryptodev_aesni_create failed", name);
cryptodev_aesni_mb_uninit(crypto_dev_name);
return -EFAULT;
}
