static void test_cache_aligned_alloc(void)
{
void *p0;
void *p1;
size_t cls;
printf("test rtems_cache_aligned_malloc()\n");
p0 = rtems_cache_aligned_malloc(1);
p1 = rtems_cache_aligned_malloc(1);
rtems_test_assert(p0 != NULL);
rtems_test_assert(p1 != NULL);
cls = rtems_cache_get_data_line_size();
if (cls > 0) {
size_t m = cls - 1;
uintptr_t a0 = (uintptr_t) p0;
uintptr_t a1 = (uintptr_t) p1;
rtems_test_assert(a1 - a0 > cls);
rtems_test_assert((a0 & m) == 0);
rtems_test_assert((a1 & m) == 0);
}
free(p0);
free(p1);
}
static void Init(rtems_task_argument arg)
{
uint32_t load = 0;
TEST_BEGIN();
printf("<Test>\n");
cache_line_size = rtems_cache_get_data_line_size();
if (cache_line_size == 0) {
cache_line_size = 32;
}
data_size = rtems_cache_get_data_cache_size(0);
if (data_size == 0) {
data_size = cache_line_size;
}
main_data = malloc(data_size);
rtems_test_assert(main_data != NULL);
test(false, load);
test(true, load);
for (load = 1; load < rtems_get_processor_count(); ++load) {
rtems_status_code sc;
rtems_id id;
volatile int *load_data = NULL;
load_data = malloc(data_size);
if (load_data == NULL) {
load_data = main_data;
}
sc = rtems_task_create(
rtems_build_name('L', 'O', 'A', 'D'),
1,
RTEMS_MINIMUM_STACK_SIZE,
RTEMS_DEFAULT_MODES,
RTEMS_DEFAULT_ATTRIBUTES,
&id
);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
sc = rtems_task_start(id, load_task, (rtems_task_argument) load_data);
rtems_test_assert(sc == RTEMS_SUCCESSFUL);
test(true, load);
}
printf("</Test>\n");
TEST_END();
rtems_test_exit(0);
}
void
rtems_bsd_chunk_init(rtems_bsd_chunk_control *self, uintptr_t info_size,
rtems_bsd_chunk_info_ctor info_ctor, rtems_bsd_chunk_info_dtor info_dtor)
{
uintptr_t align = rtems_cache_get_data_line_size();
if (align < CPU_HEAP_ALIGNMENT)
align = CPU_HEAP_ALIGNMENT;
info_size = roundup(info_size, align);
self->info_size = info_size;
self->info_ctor = info_ctor;
self->info_dtor = info_dtor;
rtems_rbtree_initialize_empty(&self->chunks);
}
int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum)
{
unsigned opcode = *(unsigned *) frame->EXC_SRR0;
/* Do we have a dcbz instruction? */
if ((opcode & 0xffe007ff) == 0x7c0007ec) {
unsigned clsz = (unsigned) rtems_cache_get_data_line_size();
unsigned a = (opcode >> 16) & 0x1f;
unsigned b = (opcode >> 11) & 0x1f;
unsigned *regs = &frame->GPR0;
unsigned *current = (unsigned *)
(((a == 0 ? 0 : regs [a]) + regs [b]) & (clsz - 1));
unsigned *end = current + clsz / 4;
while (current != end) {
*current = 0;
++current;
}
frame->EXC_SRR0 += 4;
return 0;
} else {
static void test_data_flush_and_invalidate(void)
{
if (rtems_cache_get_data_line_size() > 0) {
rtems_interrupt_lock lock;
rtems_interrupt_lock_context lock_context;
volatile int *vdata = &data[0];
int n = 32;
int i;
size_t data_size = n * sizeof(data[0]);
bool write_through;
printf("data cache flush and invalidate test\n");
rtems_interrupt_lock_initialize(&lock, "test");
rtems_interrupt_lock_acquire(&lock, &lock_context);
for (i = 0; i < n; ++i) {
vdata[i] = i;
}
rtems_cache_flush_multiple_data_lines(&data[0], data_size);
for (i = 0; i < n; ++i) {
rtems_test_assert(vdata[i] == i);
}
for (i = 0; i < n; ++i) {
vdata[i] = ~i;
}
rtems_cache_invalidate_multiple_data_lines(&data[0], data_size);
write_through = vdata[0] == ~0;
if (write_through) {
for (i = 0; i < n; ++i) {
rtems_test_assert(vdata[i] == ~i);
}
} else {
for (i = 0; i < n; ++i) {
rtems_test_assert(vdata[i] == i);
}
}
for (i = 0; i < n; ++i) {
vdata[i] = ~i;
}
rtems_cache_flush_multiple_data_lines(&data[0], data_size);
rtems_cache_invalidate_multiple_data_lines(&data[0], data_size);
for (i = 0; i < n; ++i) {
rtems_test_assert(vdata[i] == ~i);
}
rtems_interrupt_lock_release(&lock, &lock_context);
rtems_interrupt_lock_destroy(&lock);
printf(
"data cache operations by line passed the test (%s cache detected)\n",
write_through ? "write-through" : "copy-back"
);
} else {
printf(
"skip data cache flush and invalidate test"
" due to cache line size of zero\n"
);
}
/* Make sure these are nops */
rtems_cache_flush_multiple_data_lines(NULL, 0);
rtems_cache_invalidate_multiple_data_lines(NULL, 0);
}
static void test_timing(void)
{
rtems_interrupt_lock lock;
rtems_interrupt_lock_context lock_context;
size_t data_size = sizeof(data);
uint64_t d[3];
uint32_t cache_level;
size_t cache_size;
rtems_interrupt_lock_initialize(&lock, "test");
printf(
"data cache line size %zi bytes\n"
"data cache size %zi bytes\n",
rtems_cache_get_data_line_size(),
rtems_cache_get_data_cache_size(0)
);
cache_level = 1;
cache_size = rtems_cache_get_data_cache_size(cache_level);
while (cache_size > 0) {
printf(
"data cache level %" PRIu32 " size %zi bytes\n",
cache_level,
cache_size
);
++cache_level;
cache_size = rtems_cache_get_data_cache_size(cache_level);
}
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = load();
d[1] = load();
rtems_cache_flush_entire_data();
d[2] = load();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"load %zi bytes with flush entire data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with flushed cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = load();
d[1] = load();
rtems_cache_flush_multiple_data_lines(&data[0], sizeof(data));
d[2] = load();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"load %zi bytes with flush multiple data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with flushed cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = load();
d[1] = load();
rtems_cache_invalidate_multiple_data_lines(&data[0], sizeof(data));
d[2] = load();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"load %zi bytes with invalidate multiple data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with invalidated cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = store();
d[1] = store();
rtems_cache_flush_entire_data();
d[2] = store();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"store %zi bytes with flush entire data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with flushed cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = store();
d[1] = store();
rtems_cache_flush_multiple_data_lines(&data[0], sizeof(data));
d[2] = store();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"store %zi bytes with flush multiple data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with flushed cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = store();
d[1] = store();
rtems_cache_invalidate_multiple_data_lines(&data[0], sizeof(data));
d[2] = store();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"store %zi bytes with invalidate multiple data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with invalidated cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
printf(
"instruction cache line size %zi bytes\n"
"instruction cache size %zi bytes\n",
rtems_cache_get_instruction_line_size(),
rtems_cache_get_instruction_cache_size(0)
);
cache_level = 1;
cache_size = rtems_cache_get_instruction_cache_size(cache_level);
while (cache_size > 0) {
printf(
"instruction cache level %" PRIu32 " size %zi bytes\n",
cache_level,
cache_size
);
++cache_level;
cache_size = rtems_cache_get_instruction_cache_size(cache_level);
}
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = do_some_work();
d[1] = do_some_work();
rtems_cache_invalidate_entire_instruction();
d[2] = do_some_work();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"invalidate entire instruction\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with invalidated cache %" PRIu64 " ns\n",
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = do_some_work();
d[1] = do_some_work();
rtems_cache_invalidate_multiple_instruction_lines(do_some_work, 4096);
d[2] = do_some_work();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"invalidate multiple instruction\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with invalidated cache %" PRIu64 " ns\n",
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_destroy(&lock);
}
static void initializeHardware(struct bfin_ethernetSoftc *sc) {
struct ifnet *ifp;
struct mbuf *m;
unsigned char *hwaddr;
int cacheAlignment;
int rxStatusSize;
int txStatusSize;
char *ptr;
int i;
void *ethBase;
void *rxdmaBase;
void *txdmaBase;
uint32_t divisor;
ifp = &sc->arpcom.ac_if;
ethBase = sc->ethBase;
rxdmaBase = sc->rxdmaBase;
txdmaBase = sc->txdmaBase;
BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) = 0;
BFIN_REG32(ethBase, EMAC_FLC_OFFSET) = 0;
divisor = (sc->sclk / 25000000) / 2 - 1;
BFIN_REG32(ethBase, EMAC_SYSCTL_OFFSET) = (divisor <<
EMAC_SYSCTL_MDCDIV_SHIFT) |
EMAC_SYSCTL_RXDWA;
#ifdef BFIN_IPCHECKSUMS
BFIN_REG32(ethBase, EMAC_SYSCTL_OFFSET) |= EMAC_SYSCTL_RXCKS;
#endif
BFIN_REG32(ethBase, EMAC_SYSTAT_OFFSET) = ~(uint32_t) 0;
BFIN_REG32(ethBase, EMAC_RX_IRQE_OFFSET) = 0;
BFIN_REG32(ethBase, EMAC_RX_STKY_OFFSET) = ~(uint32_t) 0;
BFIN_REG32(ethBase, EMAC_TX_IRQE_OFFSET) = 0;
BFIN_REG32(ethBase, EMAC_TX_STKY_OFFSET) = ~(uint32_t) 0;
BFIN_REG32(ethBase, EMAC_MMC_RIRQE_OFFSET) = 0;
BFIN_REG32(ethBase, EMAC_MMC_RIRQS_OFFSET) = ~(uint32_t) 0;
BFIN_REG32(ethBase, EMAC_MMC_TIRQE_OFFSET) = 0;
BFIN_REG32(ethBase, EMAC_MMC_TIRQS_OFFSET) = ~(uint32_t) 0;
BFIN_REG32(ethBase, EMAC_MMC_CTL_OFFSET) = EMAC_MMC_CTL_MMCE |
EMAC_MMC_CTL_CCOR |
EMAC_MMC_CTL_RSTC;
BFIN_REG32(ethBase, EMAC_MMC_CTL_OFFSET) = EMAC_MMC_CTL_MMCE |
EMAC_MMC_CTL_CCOR;
BFIN_REG16(rxdmaBase, DMA_CONFIG_OFFSET) = 0;
BFIN_REG16(txdmaBase, DMA_CONFIG_OFFSET) = 0;
BFIN_REG16(rxdmaBase, DMA_X_COUNT_OFFSET) = 0;
BFIN_REG16(txdmaBase, DMA_X_COUNT_OFFSET) = 0;
BFIN_REG16(rxdmaBase, DMA_X_MODIFY_OFFSET) = 4;
BFIN_REG16(txdmaBase, DMA_X_MODIFY_OFFSET) = 4;
BFIN_REG16(rxdmaBase, DMA_Y_COUNT_OFFSET) = 0;
BFIN_REG16(txdmaBase, DMA_Y_COUNT_OFFSET) = 0;
BFIN_REG16(rxdmaBase, DMA_Y_MODIFY_OFFSET) = 0;
BFIN_REG16(txdmaBase, DMA_Y_MODIFY_OFFSET) = 0;
BFIN_REG16(rxdmaBase, DMA_IRQ_STATUS_OFFSET) = DMA_IRQ_STATUS_DMA_ERR |
DMA_IRQ_STATUS_DMA_DONE;
/* The status structures cannot share cache lines with anything else,
including other status structures, so we can safely manage both the
processor and DMA writing to them. So this rounds up the structure
sizes to a multiple of the cache line size. */
cacheAlignment = rtems_cache_get_data_line_size();
if (cacheAlignment == 0)
cacheAlignment = 1;
rxStatusSize = cacheAlignment * ((sizeof(rxStatusT) + cacheAlignment - 1) /
cacheAlignment);
txStatusSize = cacheAlignment * ((sizeof(txStatusT) + cacheAlignment - 1) /
cacheAlignment);
/* Allocate enough extra to allow structures to start at cache aligned
boundary. */
sc->status = malloc(sc->rxDescCount * rxStatusSize +
sc->txDescCount * txStatusSize +
cacheAlignment - 1, M_DEVBUF, M_NOWAIT);
sc->rx = malloc(sc->rxDescCount * sizeof(*sc->rx), M_DEVBUF, M_NOWAIT);
sc->tx = malloc(sc->txDescCount * sizeof(*sc->tx), M_DEVBUF, M_NOWAIT);
if (sc->status == NULL || sc->rx == NULL || sc->tx == NULL)
rtems_panic("No memory!\n");
/* Start status structures at cache aligned boundary. */
ptr = (char *) (((intptr_t) sc->status + cacheAlignment - 1) &
~(cacheAlignment - 1));
memset(ptr, 0, sc->rxDescCount * rxStatusSize +
sc->txDescCount * txStatusSize);
memset(sc->rx, 0, sc->rxDescCount * sizeof(*sc->rx));
memset(sc->tx, 0, sc->txDescCount * sizeof(*sc->tx));
rtems_cache_flush_multiple_data_lines(ptr, sc->rxDescCount * rxStatusSize +
sc->txDescCount * txStatusSize);
for (i = 0; i < sc->rxDescCount; i++) {
MGETHDR(m, M_WAIT, MT_DATA);
MCLGET(m, M_WAIT);
m->m_pkthdr.rcvif = ifp;
sc->rx[i].m = m;
/* start dma at 32 bit boundary */
sc->rx[i].data.addr = (void *) (((intptr_t) m->m_data + 3) & ~3);
rtems_cache_invalidate_multiple_data_lines(
sc->rx[i].data.addr,
BFIN_ETHERNET_MAX_FRAME_LENGTH + 2);
sc->rx[i].data.dmaConfig = DMA_MODE_RX;
sc->rx[i].data.next = &(sc->rx[i].status);
sc->rx[i].status.addr = ptr;
if (i < sc->rxDescCount - 1) {
sc->rx[i].status.dmaConfig = DMA_MODE_STATUS;
sc->rx[i].status.next = &(sc->rx[i + 1].data);
} else {
sc->rx[i].status.dmaConfig = DMA_MODE_STATUS_LAST;
sc->rx[i].status.next = &(sc->rx[0].data);
}
ptr += rxStatusSize;
}
rtems_cache_flush_multiple_data_lines(sc->rx, sc->rxDescCount *
sizeof(*sc->rx));
for (i = 0; i < sc->txDescCount; i++) {
sc->tx[i].data.addr = &sc->tx[i].buffer.packet;
sc->tx[i].data.dmaConfig = DMA_MODE_TX;
sc->tx[i].data.next = &(sc->tx[i].status);
sc->tx[i].status.addr = ptr;
sc->tx[i].status.dmaConfig = DMA_MODE_STATUS_LAST;
if (i < sc->txDescCount - 1)
sc->tx[i].status.next = &(sc->tx[i + 1].data);
else
sc->tx[i].status.next = &(sc->tx[0].data);
sc->tx[i].inUse = false;
ptr += txStatusSize;
}
rtems_cache_flush_multiple_data_lines(sc->tx, sc->txDescCount *
sizeof(*sc->tx));
BFIN_REG32(rxdmaBase, DMA_NEXT_DESC_PTR_OFFSET) = (uint32_t) &sc->rx[0].data;
BFIN_REG32(txdmaBase, DMA_NEXT_DESC_PTR_OFFSET) = (uint32_t) &sc->tx[0].data;
hwaddr = sc->arpcom.ac_enaddr;
BFIN_REG16(ethBase, EMAC_ADDRHI_OFFSET) = ((uint16_t) hwaddr[5] << 8) |
hwaddr[4];
BFIN_REG32(ethBase, EMAC_ADDRLO_OFFSET) = ((uint32_t) hwaddr[3] << 24) |
((uint32_t) hwaddr[2] << 16) |
((uint32_t) hwaddr[1] << 8) |
hwaddr[0];
if (sc->acceptBroadcast)
BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) &= ~EMAC_OPMODE_DBF;
else
BFIN_REG32(ethBase, EMAC_OPMODE_OFFSET) |= EMAC_OPMODE_DBF;
}
