//
// Description: In normal chip, we should send some packet to Hw which will be used by Fw
// in FW LPS mode. The function is to fill the Tx descriptor of this packets, then
// Fw can tell Hw to send these packet derectly.
//
void rtl8188e_fill_fake_txdesc(
PADAPTER padapter,
u8* pDesc,
u32 BufferLen,
u8 IsPsPoll,
u8 IsBTQosNull)
{
struct tx_desc *ptxdesc;
// Clear all status
ptxdesc = (struct tx_desc*)pDesc;
_rtw_memset(pDesc, 0, TXDESC_SIZE);
//offset 0
ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); //own, bFirstSeg, bLastSeg;
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000); //32 bytes for TX Desc
ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); // Buffer size + command header
//offset 4
ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<<QSEL_SHT)&0x00001f00); // Fixed queue of Mgnt queue
//Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw.
if (IsPsPoll)
{
ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
}
else
{
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
}
if (_TRUE == IsBTQosNull)
{
ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); // BT NULL
}
//offset 16
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
// USB interface drop packet if the checksum of descriptor isn't correct.
// Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
rtl8188eu_cal_txdesc_chksum(ptxdesc);
#endif
}
void rtl8188e_fill_fake_txdesc(
struct adapter * padapter,
u8* pDesc,
u32 BufferLen,
u8 IsPsPoll,
u8 IsBTQosNull)
{
struct tx_desc *ptxdesc;
/* Clear all status */
ptxdesc = (struct tx_desc*)pDesc;
_rtw_memset(pDesc, 0, TXDESC_SIZE);
/* offset 0 */
ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); /* own, bFirstSeg, bLastSeg; */
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000); /* 32 bytes for TX Desc */
ptxdesc->txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); /* Buffer size + command header */
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<<QSEL_SHT)&0x00001f00); /* Fixed queue of Mgnt queue */
/* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */
if (IsPsPoll)
{
ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
}
else
{
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */
ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
}
if (true == IsBTQosNull)
{
ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */
}
/* offset 16 */
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */
/* USB interface drop packet if the checksum of descriptor isn't correct. */
/* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */
rtl8188eu_cal_txdesc_chksum(ptxdesc);
}
s32 rtl8812au_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
{
#ifdef PLATFORM_LINUX
u16 fc;
int rc, len, pipe;
unsigned int bmcst, tid, qsel;
struct sk_buff *skb, *pxmit_skb;
struct urb *urb;
unsigned char *pxmitbuf;
struct tx_desc *ptxdesc;
struct rtw_ieee80211_hdr *tx_hdr;
struct hostapd_priv *phostapdpriv = padapter->phostapdpriv;
struct net_device *pnetdev = padapter->pnetdev;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
//DBG_8192C("%s\n", __FUNCTION__);
skb = pkt;
len = skb->len;
tx_hdr = (struct rtw_ieee80211_hdr *)(skb->data);
fc = le16_to_cpu(tx_hdr->frame_ctl);
bmcst = IS_MCAST(tx_hdr->addr1);
if ((fc & RTW_IEEE80211_FCTL_FTYPE) != RTW_IEEE80211_FTYPE_MGMT)
goto _exit;
pxmit_skb = rtw_skb_alloc(len + TXDESC_SIZE);
if(!pxmit_skb)
goto _exit;
pxmitbuf = pxmit_skb->data;
urb = usb_alloc_urb(0, GFP_ATOMIC);
if (!urb) {
goto _exit;
}
// ----- fill tx desc -----
ptxdesc = (struct tx_desc *)pxmitbuf;
_rtw_memset(ptxdesc, 0, sizeof(*ptxdesc));
//offset 0
ptxdesc->txdw0 |= cpu_to_le32(len&0x0000ffff);
ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<<OFFSET_SHT)&0x00ff0000);//default = 32 bytes for TX Desc
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
if(bmcst)
{
ptxdesc->txdw0 |= cpu_to_le32(BIT(24));
}
//offset 4
ptxdesc->txdw1 |= cpu_to_le32(0x00);//MAC_ID
ptxdesc->txdw1 |= cpu_to_le32((0x12<<QSEL_SHT)&0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((0x06<< 16) & 0x000f0000);//b mode
//offset 8
//offset 12
ptxdesc->txdw3 |= cpu_to_le32((le16_to_cpu(tx_hdr->seq_ctl)<<16)&0xffff0000);
//offset 16
ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate
//offset 20
//HW append seq
ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
rtl8188eu_cal_txdesc_chksum(ptxdesc);
// ----- end of fill tx desc -----
//
skb_put(pxmit_skb, len + TXDESC_SIZE);
pxmitbuf = pxmitbuf + TXDESC_SIZE;
_rtw_memcpy(pxmitbuf, skb->data, len);
//DBG_8192C("mgnt_xmit, len=%x\n", pxmit_skb->len);
// ----- prepare urb for submit -----
//translate DMA FIFO addr to pipehandle
//pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX);
pipe = usb_sndbulkpipe(pdvobj->pusbdev, pHalData->Queue2EPNum[(u8)MGT_QUEUE_INX]&0x0f);
usb_fill_bulk_urb(urb, pdvobj->pusbdev, pipe,
pxmit_skb->data, pxmit_skb->len, rtl8192cu_hostap_mgnt_xmit_cb, pxmit_skb);
urb->transfer_flags |= URB_ZERO_PACKET;
usb_anchor_urb(urb, &phostapdpriv->anchored);
rc = usb_submit_urb(urb, GFP_ATOMIC);
if (rc < 0) {
usb_unanchor_urb(urb);
kfree_skb(skb);
}
usb_free_urb(urb);
_exit:
rtw_skb_free(skb);
#endif
return 0;
}
static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bagg_pkt)
{
int pull = 0;
uint qsel;
u8 data_rate, pwr_status, offset;
struct adapter *adapt = pxmitframe->padapter;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
struct tx_desc *ptxdesc = (struct tx_desc *)pmem;
struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
int bmcst = IS_MCAST(pattrib->ra);
if (adapt->registrypriv.mp_mode == 0) {
if ((!bagg_pkt) && (urb_zero_packet_chk(adapt, sz) == 0)) {
ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ);
pull = 1;
}
}
memset(ptxdesc, 0, sizeof(struct tx_desc));
/* 4 offset 0 */
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);/* update TXPKTSIZE */
offset = TXDESC_SIZE + OFFSET_SZ;
ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);/* 32 bytes for TX Desc */
if (bmcst)
ptxdesc->txdw0 |= cpu_to_le32(BMC);
if (adapt->registrypriv.mp_mode == 0) {
if (!bagg_pkt) {
if ((pull) && (pxmitframe->pkt_offset > 0))
pxmitframe->pkt_offset = pxmitframe->pkt_offset - 1;
}
}
/* pkt_offset, unit:8 bytes padding */
if (pxmitframe->pkt_offset > 0)
ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000);
/* driver uses rate */
ptxdesc->txdw4 |= cpu_to_le32(USERATE);/* rate control always by driver */
if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) {
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id & 0x3F);
qsel = (uint)(pattrib->qsel & 0x0000001f);
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000);
fill_txdesc_sectype(pattrib, ptxdesc);
if (pattrib->ampdu_en) {
ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);/* AGG EN */
ptxdesc->txdw6 = cpu_to_le32(0x6666f800);
} else {
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
}
/* offset 8 */
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0x0FFF0000);
/* offset 16 , offset 20 */
if (pattrib->qos_en)
ptxdesc->txdw4 |= cpu_to_le32(QOS);/* QoS */
/* offset 20 */
if (pxmitframe->agg_num > 1)
ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000);
if ((pattrib->ether_type != 0x888e) &&
(pattrib->ether_type != 0x0806) &&
(pattrib->ether_type != 0x88b4) &&
(pattrib->dhcp_pkt != 1)) {
/* Non EAP & ARP & DHCP type data packet */
fill_txdesc_vcs(pattrib, &ptxdesc->txdw4);
fill_txdesc_phy(pattrib, &ptxdesc->txdw4);
ptxdesc->txdw4 |= cpu_to_le32(0x00000008);/* RTS Rate=24M */
ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);/* DATA/RTS Rate FB LMT */
if (pattrib->ht_en) {
if (ODM_RA_GetShortGI_8188E(&haldata->odmpriv, pattrib->mac_id))
ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */
}
data_rate = ODM_RA_GetDecisionRate_8188E(&haldata->odmpriv, pattrib->mac_id);
ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F);
pwr_status = ODM_RA_GetHwPwrStatus_8188E(&haldata->odmpriv, pattrib->mac_id);
ptxdesc->txdw4 |= cpu_to_le32((pwr_status & 0x7) << PWR_STATUS_SHT);
} else {
/* EAP data packet and ARP packet and DHCP. */
/* Use the 1M data rate to send the EAP/ARP packet. */
/* This will maybe make the handshake smooth. */
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */
if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
ptxdesc->txdw4 |= cpu_to_le32(BIT(24));/* DATA_SHORT */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
} else if ((pxmitframe->frame_tag&0x0f) == MGNT_FRAMETAG) {
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id & 0x3f);
qsel = (uint)(pattrib->qsel&0x0000001f);
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000f0000);
/* offset 8 */
/* CCX-TXRPT ack for xmit mgmt frames. */
if (pxmitframe->ack_report)
ptxdesc->txdw2 |= cpu_to_le32(BIT(19));
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0FFF0000);
/* offset 20 */
ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);/* retry limit enable */
if (pattrib->retry_ctrl)
ptxdesc->txdw5 |= cpu_to_le32(0x00180000);/* retry limit = 6 */
else
ptxdesc->txdw5 |= cpu_to_le32(0x00300000);/* retry limit = 12 */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
} else if ((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG) {
DBG_88E("pxmitframe->frame_tag == TXAGG_FRAMETAG\n");
} else {
DBG_88E("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag);
/* offset 4 */
ptxdesc->txdw1 |= cpu_to_le32((4) & 0x3f);/* CAM_ID(MAC_ID) */
ptxdesc->txdw1 |= cpu_to_le32((6 << RATE_ID_SHT) & 0x000f0000);/* raid */
/* offset 8 */
/* offset 12 */
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0fff0000);
/* offset 20 */
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
/* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
/* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
/* mgnt frame should be controlled by Hw because Fw will also send null data */
/* which we cannot control when Fw LPS enable. */
/* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
/* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
/* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
/* 2010.06.23. Added by tynli. */
if (!pattrib->qos_en) {
ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); /* Hw set sequence number */
ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); /* Hw set sequence number */
}
rtl88eu_dm_set_tx_ant_by_tx_info(&haldata->odmpriv, pmem,
pattrib->mac_id);
rtl8188eu_cal_txdesc_chksum(ptxdesc);
_dbg_dump_tx_info(adapt, pxmitframe->frame_tag, ptxdesc);
return pull;
}
static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bagg_pkt)
{
int pull=0;
uint qsel;
u8 data_rate,pwr_status,offset;
_adapter *padapter = pxmitframe->padapter;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
//struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct tx_desc *ptxdesc = (struct tx_desc *)pmem;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
sint bmcst = IS_MCAST(pattrib->ra);
#ifdef CONFIG_P2P
struct wifidirect_info* pwdinfo = &padapter->wdinfo;
#endif //CONFIG_P2P
#ifdef CONFIG_CONCURRENT_MODE
if(rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER)
pHalData = GET_HAL_DATA(padapter->pbuddy_adapter);
#endif //CONFIG_CONCURRENT_MODE
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
if (padapter->registrypriv.mp_mode == 0)
{
if((!bagg_pkt) &&(urb_zero_packet_chk(padapter, sz)==0))//(sz %512) != 0
//if((!bagg_pkt) &&(rtw_usb_bulk_size_boundary(padapter,TXDESC_SIZE+sz)==_FALSE))
{
ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ);
//DBG_8192C("==> non-agg-pkt,shift pointer...\n");
pull = 1;
}
}
#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX
_rtw_memset(ptxdesc, 0, sizeof(struct tx_desc));
//4 offset 0
ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
//DBG_8192C("%s==> pkt_len=%d,bagg_pkt=%02x\n",__FUNCTION__,sz,bagg_pkt);
ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);//update TXPKTSIZE
offset = TXDESC_SIZE + OFFSET_SZ;
#ifdef CONFIG_TX_EARLY_MODE
if(bagg_pkt){
offset += EARLY_MODE_INFO_SIZE ;//0x28
}
#endif
//DBG_8192C("%s==>offset(0x%02x) \n",__FUNCTION__,offset);
ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);//32 bytes for TX Desc
if (bmcst) ptxdesc->txdw0 |= cpu_to_le32(BMC);
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
if (padapter->registrypriv.mp_mode == 0)
{
if(!bagg_pkt){
if((pull) && (pxmitframe->pkt_offset>0)) {
pxmitframe->pkt_offset = pxmitframe->pkt_offset -1;
}
}
}
#endif
//DBG_8192C("%s, pkt_offset=0x%02x\n",__FUNCTION__,pxmitframe->pkt_offset);
// pkt_offset, unit:8 bytes padding
if (pxmitframe->pkt_offset > 0)
ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000);
//driver uses rate
ptxdesc->txdw4 |= cpu_to_le32(USERATE);//rate control always by driver
if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG)
{
//DBG_8192C("pxmitframe->frame_tag == DATA_FRAMETAG\n");
//offset 4
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3F);
qsel = (uint)(pattrib->qsel & 0x0000001f);
//DBG_8192C("==> macid(%d) qsel:0x%02x \n",pattrib->mac_id,qsel);
ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000F0000);
fill_txdesc_sectype(pattrib, ptxdesc);
if(pattrib->ampdu_en==_TRUE){
ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);//AGG EN
//SET_TX_DESC_MAX_AGG_NUM_88E(pDesc, 0x1F);
//SET_TX_DESC_MCSG1_MAX_LEN_88E(pDesc, 0x6);
//SET_TX_DESC_MCSG2_MAX_LEN_88E(pDesc, 0x6);
//SET_TX_DESC_MCSG3_MAX_LEN_88E(pDesc, 0x6);
//SET_TX_DESC_MCS7_SGI_MAX_LEN_88E(pDesc, 0x6);
ptxdesc->txdw6 = 0x6666f800;
}
else{
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK
}
//offset 8
//offset 12
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<< SEQ_SHT)&0x0FFF0000);
//offset 16 , offset 20
if (pattrib->qos_en)
ptxdesc->txdw4 |= cpu_to_le32(QOS);//QoS
//offset 20
#ifdef CONFIG_USB_TX_AGGREGATION
if (pxmitframe->agg_num > 1){
//DBG_8192C("%s agg_num:%d\n",__FUNCTION__,pxmitframe->agg_num );
ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000);
}
#endif
if ((pattrib->ether_type != 0x888e) &&
(pattrib->ether_type != 0x0806) &&
(pattrib->ether_type != 0x88b4) &&
(pattrib->dhcp_pkt != 1))
{
//Non EAP & ARP & DHCP type data packet
fill_txdesc_vcs(pattrib, &ptxdesc->txdw4);
fill_txdesc_phy(pattrib, &ptxdesc->txdw4);
ptxdesc->txdw4 |= cpu_to_le32(0x00000008);//RTS Rate=24M
ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);//DATA/RTS Rate FB LMT
#if (RATE_ADAPTIVE_SUPPORT == 1)
if(pattrib->ht_en){
if( ODM_RA_GetShortGI_8188E(&pHalData->odmpriv,pattrib->mac_id))
ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI
}
data_rate =ODM_RA_GetDecisionRate_8188E(&pHalData->odmpriv,pattrib->mac_id);
ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F);
//for debug
#if 0
if(padapter->fix_rate!= 0xFF){
ptxdesc->datarate = padapter->fix_rate;
}
#endif
#if (POWER_TRAINING_ACTIVE==1)
pwr_status = ODM_RA_GetHwPwrStatus_8188E(&pHalData->odmpriv,pattrib->mac_id);
ptxdesc->txdw4 |=cpu_to_le32( (pwr_status & 0x7)<< PWR_STATUS_SHT);
#endif //(POWER_TRAINING_ACTIVE==1)
#else//if (RATE_ADAPTIVE_SUPPORT == 1)
if(pattrib->ht_en)
ptxdesc->txdw5 |= cpu_to_le32(SGI);//SGI
data_rate = 0x13; //default rate: MCS7
if(padapter->fix_rate!= 0xFF){//rate control by iwpriv
data_rate = padapter->fix_rate;
}
ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F);
#endif//if (RATE_ADAPTIVE_SUPPORT == 1)
}
else
{
// EAP data packet and ARP packet and DHCP.
// Use the 1M data rate to send the EAP/ARP packet.
// This will maybe make the handshake smooth.
ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK
if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
ptxdesc->txdw4 |= cpu_to_le32(BIT(24));// DATA_SHORT
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
//offset 24
if ( pattrib->hw_tcp_csum == 1 ) {
// ptxdesc->txdw6 = 0; // clear TCP_CHECKSUM and IP_CHECKSUM. It's zero already!!
u8 ip_hdr_offset = 32 + pattrib->hdrlen + pattrib->iv_len + 8;
ptxdesc->txdw7 = (1 << 31) | (ip_hdr_offset << 16);
DBG_8192C("ptxdesc->txdw7 = %08x\n", ptxdesc->txdw7);
}
#endif
}
else if((pxmitframe->frame_tag&0x0f)== MGNT_FRAMETAG)
{
//DBG_8192C("pxmitframe->frame_tag == MGNT_FRAMETAG\n");
//offset 4
ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x3f);
qsel = (uint)(pattrib->qsel&0x0000001f);
ptxdesc->txdw1 |= cpu_to_le32((qsel<<QSEL_SHT)&0x00001f00);
ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< RATE_ID_SHT) & 0x000f0000);
//fill_txdesc_sectype(pattrib, ptxdesc);
//offset 8
#ifdef CONFIG_XMIT_ACK
//CCX-TXRPT ack for xmit mgmt frames.
if (pxmitframe->ack_report) {
#ifdef DBG_CCX
static u16 ccx_sw = 0x123;
ptxdesc->txdw7 |= cpu_to_le32(((ccx_sw)<<16)&0x0fff0000);
DBG_871X("%s set ccx, sw:0x%03x\n", __func__, ccx_sw);
ccx_sw = (ccx_sw+1)%0xfff;
#endif
ptxdesc->txdw2 |= cpu_to_le32(BIT(19));
}
#endif //CONFIG_XMIT_ACK
//offset 12
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0FFF0000);
//offset 20
ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);//retry limit enable
if(pattrib->retry_ctrl == _TRUE)
ptxdesc->txdw5 |= cpu_to_le32(0x00180000);//retry limit = 6
else
ptxdesc->txdw5 |= cpu_to_le32(0x00300000);//retry limit = 12
#ifdef CONFIG_INTEL_PROXIM
if((padapter->proximity.proxim_on==_TRUE)&&(pattrib->intel_proxim==_TRUE)){
DBG_871X("\n %s pattrib->rate=%d\n",__FUNCTION__,pattrib->rate);
ptxdesc->txdw5 |= cpu_to_le32( pattrib->rate);
}
else
#endif
{
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
}
else if((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG)
{
DBG_8192C("pxmitframe->frame_tag == TXAGG_FRAMETAG\n");
}
#ifdef CONFIG_MP_INCLUDED
else if(((pxmitframe->frame_tag&0x0f) == MP_FRAMETAG) &&
(padapter->registrypriv.mp_mode == 1))
{
fill_txdesc_for_mp(padapter, ptxdesc);
}
#endif
else
{
DBG_8192C("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag);
//offset 4
ptxdesc->txdw1 |= cpu_to_le32((4)&0x3f);//CAM_ID(MAC_ID)
ptxdesc->txdw1 |= cpu_to_le32((6<< RATE_ID_SHT) & 0x000f0000);//raid
//offset 8
//offset 12
ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<SEQ_SHT)&0x0fff0000);
//offset 20
ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate));
}
// 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.
// (1) The sequence number of each non-Qos frame / broadcast / multicast /
// mgnt frame should be controled by Hw because Fw will also send null data
// which we cannot control when Fw LPS enable.
// --> default enable non-Qos data sequense number. 2010.06.23. by tynli.
// (2) Enable HW SEQ control for beacon packet, because we use Hw beacon.
// (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets.
// 2010.06.23. Added by tynli.
if(!pattrib->qos_en)
{
//ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number
//ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29.
ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); // Hw set sequence number
ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); // Hw set sequence number
}
#ifdef CONFIG_HW_ANTENNA_DIVERSITY //CONFIG_ANTENNA_DIVERSITY
ODM_SetTxAntByTxInfo_88E(&pHalData->odmpriv, pmem, pattrib->mac_id);
#endif
rtl8188eu_cal_txdesc_chksum(ptxdesc);
_dbg_dump_tx_info(padapter,pxmitframe->frame_tag,ptxdesc);
return pull;
}