static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) { struct rtsx_cr_option *option = &(pcr->option); u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST); int aspm_L1_1, aspm_L1_2; u8 val = 0; aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); if (active) { /* Run, latency: 60us */ if (aspm_L1_1) val = option->ltr_l1off_snooze_sspwrgate; } else { /* L1off, latency: 300us */ if (aspm_L1_2) val = option->ltr_l1off_sspwrgate; } if (aspm_L1_1 || aspm_L1_2) { if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) { if (card_exist) val &= ~L1OFF_MBIAS2_EN_5250; else val |= L1OFF_MBIAS2_EN_5250; } } rtsx_set_l1off_sub(pcr, val); }
static int rts5249_init_from_hw(struct rtsx_pcr *pcr) { struct rtsx_cr_option *option = &(pcr->option); if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN | PM_L1_1_EN | PM_L1_2_EN)) option->force_clkreq_0 = false; else option->force_clkreq_0 = true; return 0; }
static void rts5260_init_from_cfg(struct rtsx_pcr *pcr) { struct rtsx_cr_option *option = &pcr->option; u32 lval; rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_5260, &lval); if (lval & ASPM_L1_1_EN_MASK) rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); if (lval & ASPM_L1_2_EN_MASK) rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); if (lval & PM_L1_1_EN_MASK) rtsx_set_dev_flag(pcr, PM_L1_1_EN); if (lval & PM_L1_2_EN_MASK) rtsx_set_dev_flag(pcr, PM_L1_2_EN); rts5260_pwr_saving_setting(pcr); if (option->ltr_en) { u16 val; pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); if (val & PCI_EXP_DEVCTL2_LTR_EN) { option->ltr_enabled = true; option->ltr_active = true; rtsx_set_ltr_latency(pcr, option->ltr_active_latency); } else { option->ltr_enabled = false; } } if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN | PM_L1_1_EN | PM_L1_2_EN)) option->force_clkreq_0 = false; else option->force_clkreq_0 = true; }
static void rts5260_pwr_saving_setting(struct rtsx_pcr *pcr) { int lss_l1_1, lss_l1_2; lss_l1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN) | rtsx_check_dev_flag(pcr, PM_L1_1_EN); lss_l1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN) | rtsx_check_dev_flag(pcr, PM_L1_2_EN); if (lss_l1_2) { pcr_dbg(pcr, "Set parameters for L1.2."); rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL, 0xFF, PCIE_L1_2_EN); rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL, RTS5260_DVCC_OCP_EN | RTS5260_DVCC_OCP_CL_EN, RTS5260_DVCC_OCP_EN | RTS5260_DVCC_OCP_CL_EN); rtsx_pci_write_register(pcr, PWR_FE_CTL, 0xFF, PCIE_L1_2_PD_FE_EN); } else if (lss_l1_1) { pcr_dbg(pcr, "Set parameters for L1.1."); rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL, 0xFF, PCIE_L1_1_EN); rtsx_pci_write_register(pcr, PWR_FE_CTL, 0xFF, PCIE_L1_1_PD_FE_EN); } else { pcr_dbg(pcr, "Set parameters for L1."); rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL, 0xFF, PCIE_L1_0_EN); rtsx_pci_write_register(pcr, PWR_FE_CTL, 0xFF, PCIE_L1_0_PD_FE_EN); } rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_DPHY_RET_VALUE, 0xFF, CFG_L1_0_RET_VALUE_DEFAULT); rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_MAC_RET_VALUE, 0xFF, CFG_L1_0_RET_VALUE_DEFAULT); rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD30_RET_VALUE, 0xFF, CFG_L1_0_RET_VALUE_DEFAULT); rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD40_RET_VALUE, 0xFF, CFG_L1_0_RET_VALUE_DEFAULT); rtsx_pci_write_register(pcr, CFG_L1_0_SYS_RET_VALUE, 0xFF, CFG_L1_0_RET_VALUE_DEFAULT); /*Option cut APHY*/ rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_0, 0xFF, CFG_PCIE_APHY_OFF_0_DEFAULT); rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_1, 0xFF, CFG_PCIE_APHY_OFF_1_DEFAULT); rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_2, 0xFF, CFG_PCIE_APHY_OFF_2_DEFAULT); rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_3, 0xFF, CFG_PCIE_APHY_OFF_3_DEFAULT); /*CDR DEC*/ rtsx_pci_write_register(pcr, PWC_CDR, 0xFF, PWC_CDR_DEFAULT); /*PWMPFM*/ rtsx_pci_write_register(pcr, CFG_LP_FPWM_VALUE, 0xFF, CFG_LP_FPWM_VALUE_DEFAULT); /*No Power Saving WA*/ rtsx_pci_write_register(pcr, CFG_L1_0_CRC_MISC_RET_VALUE, 0xFF, CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT); }