void add_sleep_to_cpu(int sleep_time, int final_cpu_num){
int i;
//qemu_clock_enable(vm_clock, false);
if(sleep_penv == NULL) sleep_penv = first_cpu;
freezing_time = sleep_time;
for(i = 0; i < final_cpu_num; i++){
if(sleep_penv) {
//penv->stop = 1;
run_on_cpu(sleep_penv, mig_sleep_cpu, NULL);
//qemu_cpu_kick(penv);
if((sleep_penv = (CPUState *)sleep_penv->next_cpu) == NULL)
sleep_penv = first_cpu;
}
else{
printf("sleep_penv == NULL, no cpu? fatal error!\n");
fflush(stdout);
exit(1);
}
}
}
static void set_spr(CPUState *cs, int spr, target_ulong value,
target_ulong mask)
{
struct SPRSyncState s = {
.cs = cs,
.spr = spr,
.value = value,
.mask = mask
};
run_on_cpu(cs, do_spr_sync, &s);
}
static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
s390_cpu_gdb_init(cs);
qemu_init_vcpu(cs);
#if !defined(CONFIG_USER_ONLY)
run_on_cpu(cs, s390_do_cpu_full_reset, cs);
#else
cpu_reset(cs);
#endif
scc->parent_realize(dev, errp);
}
static ssize_t store_mmustat_enable(struct device *s,
struct device_attribute *attr, const char *buf,
size_t count)
{
unsigned long val, err;
int ret = sscanf(buf, "%lu", &val);
if (ret != 1)
return -EINVAL;
err = run_on_cpu(s->id, write_mmustat_enable, val);
if (err)
return -EIO;
return count;
}
static void spin_write(void *opaque, hwaddr addr, uint64_t value,
unsigned len)
{
SpinState *s = opaque;
int env_idx = addr / sizeof(SpinInfo);
CPUPPCState *env;
SpinInfo *curspin = &s->spin[env_idx];
uint8_t *curspin_p = (uint8_t*)curspin;
for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (env->cpu_index == env_idx) {
break;
}
}
if (!env) {
/* Unknown CPU */
return;
}
if (!env->cpu_index) {
/* primary CPU doesn't spin */
return;
}
curspin_p = &curspin_p[addr % sizeof(SpinInfo)];
switch (len) {
case 1:
stb_p(curspin_p, value);
break;
case 2:
stw_p(curspin_p, value);
break;
case 4:
stl_p(curspin_p, value);
break;
}
if (!(ldq_p(&curspin->addr) & 1)) {
/* run CPU */
SpinKick kick = {
.cpu = ppc_env_get_cpu(env),
.spin = curspin,
};
run_on_cpu(CPU(kick.cpu), spin_kick, &kick);
}
static int modified_clear_reset(S390CPU *cpu)
{
S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
CPUState *t;
pause_all_vcpus();
cpu_synchronize_all_states();
CPU_FOREACH(t) {
run_on_cpu(t, s390_do_cpu_full_reset, t);
}
cmma_reset(cpu);
subsystem_reset();
scc->load_normal(CPU(cpu));
cpu_synchronize_all_post_reset();
resume_all_vcpus();
return 0;
}
void ppc_set_compat_all(uint32_t compat_pvr, Error **errp)
{
CPUState *cs;
CPU_FOREACH(cs) {
SetCompatState s = {
.compat_pvr = compat_pvr,
.err = NULL,
};
run_on_cpu(cs, do_set_compat, RUN_ON_CPU_HOST_PTR(&s));
if (s.err) {
error_propagate(errp, s.err);
return;
}
}
}
static void spin_write(void *opaque, hwaddr addr, uint64_t value,
unsigned len)
{
SpinState *s = opaque;
int env_idx = addr / sizeof(SpinInfo);
CPUState *cpu;
SpinInfo *curspin = &s->spin[env_idx];
uint8_t *curspin_p = (uint8_t*)curspin;
cpu = qemu_get_cpu(env_idx);
if (cpu == NULL) {
/* Unknown CPU */
return;
}
if (cpu->cpu_index == 0) {
/* primary CPU doesn't spin */
return;
}
curspin_p = &curspin_p[addr % sizeof(SpinInfo)];
switch (len) {
case 1:
stb_p(curspin_p, value);
break;
case 2:
stw_p(curspin_p, value);
break;
case 4:
stl_p(curspin_p, value);
break;
}
if (!(ldq_p(&curspin->addr) & 1)) {
/* run CPU */
SpinKick kick = {
.cpu = POWERPC_CPU(cpu),
.spin = curspin,
};
run_on_cpu(cpu, spin_kick, &kick);
}
static void s5l8930_iop_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
s5l8930_iop_s *s = (s5l8930_iop_s *)opaque;
//fprintf(stderr, "%s:%s: offset 0x%08x value 0x%08x isARM7_CPU 0x%p\n", __FUNCTION__, s->name, offset, value, get_current_cpu());
//cpu_synchronize_all_states();
switch(offset) {
case 0x18:
case 0x1c:
case 0x24:
return;
case 0x100:
if(value & 0x10) { /* Stop CPU ? */
s->status |= 0x2;
break;
}
if(value & 0x1) {
fprintf(stderr, "switching cpu state to start IOP processing @ address 0x%08x\n", s->startaddr);
cpu_interrupt(s->s5l8930env, CPU_INTERRUPT_HALT);
//pause_all_vcpus();
//switch_iop_mode(s->env, ARM_MODE_IOP);
run_on_cpu(s->iopenv, do_iop_run, s);
//s->iopenv->regs[15] = s->startaddr;
//resume_all_vcpus();
}
s->status = value;
break;
case 0x110:
s->startaddr = value;
break;
default:
fprintf(stderr, "%s:%s: UNKNOWN offset 0x%08x value 0x%08x isARM7_CPU 0x%p\n", __FUNCTION__, s->name, offset, value, get_current_cpu());
break;
}
}
static ssize_t show_mmustat_enable(struct device *s,
struct device_attribute *attr, char *buf)
{
unsigned long val = run_on_cpu(s->id, read_mmustat_enable, 0);
return sprintf(buf, "%lx\n", val);
}
static void s390_cpu_machine_reset_cb(void *opaque)
{
S390CPU *cpu = opaque;
run_on_cpu(CPU(cpu), s390_do_cpu_full_reset, CPU(cpu));
}
void whpx_cpu_synchronize_post_reset(CPUState *cpu)
{
run_on_cpu(cpu, do_whpx_cpu_synchronize_post_reset, RUN_ON_CPU_NULL);
}
void whpx_cpu_synchronize_state(CPUState *cpu)
{
if (!cpu->vcpu_dirty) {
run_on_cpu(cpu, do_whpx_cpu_synchronize_state, RUN_ON_CPU_NULL);
}
}
void whpx_cpu_synchronize_pre_loadvm(CPUState *cpu)
{
run_on_cpu(cpu, do_whpx_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL);
}
static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
S390CPU *cpu = S390_CPU(dev);
CPUS390XState *env = &cpu->env;
Error *err = NULL;
/* the model has to be realized before qemu_init_vcpu() due to kvm */
s390_realize_cpu_model(cs, &err);
if (err) {
goto out;
}
#if !defined(CONFIG_USER_ONLY)
if (cpu->id >= max_cpus) {
error_setg(&err, "Unable to add CPU: %" PRIi64
", max allowed: %d", cpu->id, max_cpus - 1);
goto out;
}
#endif
if (cpu_exists(cpu->id)) {
error_setg(&err, "Unable to add CPU: %" PRIi64
", it already exists", cpu->id);
goto out;
}
if (cpu->id != scc->next_cpu_id) {
error_setg(&err, "Unable to add CPU: %" PRIi64
", The next available id is %" PRIi64, cpu->id,
scc->next_cpu_id);
goto out;
}
cpu_exec_realizefn(cs, &err);
if (err != NULL) {
goto out;
}
scc->next_cpu_id++;
#if !defined(CONFIG_USER_ONLY)
qemu_register_reset(s390_cpu_machine_reset_cb, cpu);
#endif
env->cpu_num = cpu->id;
s390_cpu_gdb_init(cs);
qemu_init_vcpu(cs);
#if !defined(CONFIG_USER_ONLY)
run_on_cpu(cs, s390_do_cpu_full_reset, RUN_ON_CPU_NULL);
#else
cpu_reset(cs);
#endif
scc->parent_realize(dev, &err);
#if !defined(CONFIG_USER_ONLY)
if (dev->hotplugged) {
raise_irq_cpu_hotplug();
}
#endif
out:
error_propagate(errp, err);
}
void hax_cpu_synchronize_post_init(CPUState *cpu)
{
run_on_cpu(cpu, do_hax_cpu_synchronize_post_init, RUN_ON_CPU_NULL);
}
