static int exynos_cfg_i2s_gpio(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
struct exynos_gpio_cfg exynos4_cfg[3] = {
{ EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2) },
{ EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2) },
{ EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(2) }
};
struct exynos_gpio_cfg exynos5_cfg[3] = {
{ EXYNOS5_GPZ(0), 7, S3C_GPIO_SFN(2) },
{ EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(2) },
{ EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(2) }
};
if (pdev->id < 0 || pdev->id > 2) {
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
s3c_gpio_cfgpin_range(exynos4_cfg[pdev->id].addr,
exynos4_cfg[pdev->id].num, exynos4_cfg[pdev->id].bit);
else if (soc_is_exynos5250())
s3c_gpio_cfgpin_range(exynos5_cfg[pdev->id].addr,
exynos5_cfg[pdev->id].num, exynos5_cfg[pdev->id].bit);
return 0;
}
static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S3C64XX_GPD(0);
break;
case 1:
base = S3C64XX_GPE(0);
break;
case 2:
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
return 0;
default:
printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
pdev->id);
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
return 0;
}
static int exynos_spdif_cfg_gpio(struct platform_device *pdev)
{
/* configure GPIO for SPDIF port */
if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
else if (soc_is_exynos5250())
s3c_gpio_cfgpin_range(EXYNOS5_GPB1(0), 2, S3C_GPIO_SFN(4));
return 0;
}
static int exynos_pcm_cfg_gpio(struct platform_device *pdev)
{
/* configure GPIO for pcm port */
struct exynos_gpio_cfg exynos4_cfg[3] = {
{ EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3) },
{ EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3) },
{ EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3) }
};
struct exynos_gpio_cfg exynos5_cfg[3] = {
{ EXYNOS5_GPZ(0), 5, S3C_GPIO_SFN(3) },
{ EXYNOS5_GPB0(0), 5, S3C_GPIO_SFN(3) },
{ EXYNOS5_GPB1(0), 5, S3C_GPIO_SFN(3) }
};
if (pdev->id < 0 || pdev->id > 2) {
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
s3c_gpio_cfgpin_range(exynos4_cfg[pdev->id].addr,
exynos4_cfg[pdev->id].num, exynos4_cfg[pdev->id].bit);
else if (soc_is_exynos5250())
s3c_gpio_cfgpin_range(exynos5_cfg[pdev->id].addr,
exynos5_cfg[pdev->id].num, exynos5_cfg[pdev->id].bit);
#ifdef CONFIG_SND_SOC_BCM4334
/* these are temporary settings, electrical characterics of pcm port should be checked. */
if (soc_is_exynos4412() && pdev->id == 1) {
s3c_gpio_setpull(EXYNOS4_GPC0(0), S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(EXYNOS4_GPC0(0), S5P_GPIO_DRVSTR_LV1);
s3c_gpio_cfgpin(EXYNOS4_GPC0(1), 0);
s3c_gpio_setpull(EXYNOS4_GPC0(2), S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(EXYNOS4_GPC0(2), S5P_GPIO_DRVSTR_LV4);
s3c_gpio_setpull(EXYNOS4_GPC0(3), S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(EXYNOS4_GPC0(3), S5P_GPIO_DRVSTR_LV1);
s3c_gpio_setpull(EXYNOS4_GPC0(4), S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(EXYNOS4_GPC0(4), S5P_GPIO_DRVSTR_LV1);
}
#endif
return 0;
}
static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(5));
break;
case 1:
s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(3));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
break;
case 1:
s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
break;
case 2:
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static int s5pc100_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case 0: /* Dedicated pins */
break;
case 1:
s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2));
break;
case 2:
s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
return 0;
}
static int exynos4_cfg_i2s(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
break;
case 1:
s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
break;
case 2:
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
return 0;
}
void s3c64xx_ide_setup_gpio(void)
{
u32 reg;
reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
/* Independent CF interface, CF chip select configuration */
writel(reg | MEM_SYS_CFG_INDEP_CF |
MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
/* Set XhiDATA[15:0] pins as CF Data[15:0] */
s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
}
void s3c64xx_ide_setup_gpio(void)
{
u32 reg;
reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
writel(reg | MEM_SYS_CFG_INDEP_CF |
MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
}
static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S3C64XX_GPD(0);
break;
case 1:
base = S3C64XX_GPE(0);
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number: %d\n",
pdev->id);
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
return 0;
}
static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S5P6442_GPC0(0);
break;
case 1:
base = S5P6442_GPC1(0);
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
return 0;
}
static int s5p6442_cfg_i2s(struct platform_device *pdev)
{
unsigned int base;
/* configure GPIO for i2s port */
switch (pdev->id) {
case 1:
base = S5P6442_GPC1(0);
break;
case 0:
base = S5P6442_GPC0(0);
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
return 0;
}
static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev)
{
return s3c_gpio_cfgpin_range(S3C64XX_GPE(0), 5, S3C_GPIO_SFN(4));
}
static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
{
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
return 0;
}
static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
{
return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
}
static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev)
{
s3c_gpio_cfgpin_range(S5PC100_GPG3(5), 2, S3C_GPIO_SFN(3));
return 0;
}
static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
{
return s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(4));
}
static int s5pv210_spdif_cfg_gpio(struct platform_device *pdev)
{
s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 2, S3C_GPIO_SFN(3));
return 0;
}
