/*
* until it becomes enabled, this UDC should be completely invisible
* to any USB host.
*/
static int s3c_udc_enable(struct s3c_udc *dev)
{
u32 reg_val;
DEBUG_SETUP("%s: %p\n", __func__, dev);
#if USING_MACH_OTG_PHY
otg_phy_init();
#else
writel(1, S5P_USB_PHY_CONTROL);
writel(0xa0, S3C_USBOTG_PHYPWR); /* Power up */
writel(OTGH_PHY_CLK_VALUE, S3C_USBOTG_PHYCLK);
writel(0x1, S3C_USBOTG_RSTCON);
udelay(50);
writel(0x0, S3C_USBOTG_RSTCON);
udelay(50);
#endif
dev->udc_state = USB_STATE_POWERED;
dev->gadget.speed = USB_SPEED_UNKNOWN;
/* 14. Initialize OTG Link Core. */
writel(GAHBCFG_INIT, S3C_UDC_OTG_GAHBCFG);
writel( 0<<15 // PHY Low Power Clock sel
|1<<14 // Non-Periodic TxFIFO Rewind Enable
|0x5<<10 // Turnaround time
|0<<9|0<<8 // [0:HNP disable, 1:HNP enable][ 0:SRP disable, 1:SRP enable] H1= 1,1
|0<<7 // Ulpi DDR sel
|0<<6 // 0: high speed utmi+, 1: full speed serial
|0<<4 // 0: utmi+, 1:ulpi
|1<<3 // phy i/f 0:8bit, 1:16bit
|0x7<<0, // HS/FS Timeout*
S3C_UDC_OTG_GUSBCFG);
s3c_udc_initialize(dev);
//change proper register instead of S3C_UDC_OTG_GINTMSK
reg_val = readl(S3C_UDC_OTG_GINTMSK);
if(!reg_val)
{
DEBUG_ERROR("[%s] Fail to set GINTMSK 0x%x\n", __func__, reg_val);
return -1;
}
return 0;
}
/*
* until it becomes enabled, this UDC should be completely invisible
* to any USB host.
*/
static int s3c_udc_enable(struct s3c_udc *dev)
{
u32 reg_val;
DEBUG_SETUP("%s: %p\n", __func__, dev);
reg_val = readl(S3C_OTHERS);
reg_val |= (1<<16); // USB_SIG_MASK
writel(reg_val, S3C_OTHERS);
// 1. Initializes OTG Phy.
writel(0x0, S3C_USBOTG_PHYPWR);
writel(0x20, S3C_USBOTG_PHYCLK);
writel(0x1, S3C_USBOTG_RSTCON);
// confirm delay time with thinking pm logic
udelay(50);
writel(0x0, S3C_USBOTG_RSTCON);
udelay(50);
dev->udc_state = USB_STATE_POWERED;
dev->gadget.speed = USB_SPEED_UNKNOWN;
/* 14. Initialize OTG Link Core. */
writel(GAHBCFG_INIT, S3C_UDC_OTG_GAHBCFG);
writel( 0<<15 // PHY Low Power Clock sel
|1<<14 // Non-Periodic TxFIFO Rewind Enable
|0x5<<10 // Turnaround time
|0<<9|0<<8 // [0:HNP disable, 1:HNP enable][ 0:SRP disable, 1:SRP enable] H1= 1,1
|0<<7 // Ulpi DDR sel
|0<<6 // 0: high speed utmi+, 1: full speed serial
|0<<4 // 0: utmi+, 1:ulpi
|1<<3 // phy i/f 0:8bit, 1:16bit
|0x7<<0, // HS/FS Timeout*
S3C_UDC_OTG_GUSBCFG);
s3c_udc_initialize(dev);
//change proper register instead of S3C_UDC_OTG_GINTMSK
reg_val = readl(S3C_UDC_OTG_GINTMSK);
if(!reg_val)
{
DEBUG_ERROR("[%s] Fail to set GINTMSK 0x%x\n", __func__, reg_val);
return -1;
}
return 0;
}