static int __init s5p64x0_gpiolib_init(void)
{
s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
ARRAY_SIZE(s5p64x0_gpio_cfgs));
if (soc_is_s5p6450()) {
samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
ARRAY_SIZE(s5p6450_gpio_2bit));
samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
ARRAY_SIZE(s5p6450_gpio_4bit));
samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
ARRAY_SIZE(s5p6450_gpio_4bit2));
s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
} else {
samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
ARRAY_SIZE(s5p6440_gpio_2bit));
samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
ARRAY_SIZE(s5p6440_gpio_4bit));
samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
ARRAY_SIZE(s5p6440_gpio_4bit2));
s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
}
return 0;
}
/* TODO: cleanup soc_is_* */
static __init int samsung_gpiolib_init(void)
{
/*
* Currently there are two drivers that can provide GPIO support for
* Samsung SoCs. For device tree enabled platforms, the new
* pinctrl-samsung driver is used, providing both GPIO and pin control
* interfaces. For legacy (non-DT) platforms this driver is used.
*/
if (of_have_populated_dt())
return -ENODEV;
samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
if (soc_is_s3c24xx()) {
s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
} else if (soc_is_s3c64xx()) {
samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
ARRAY_SIZE(s3c64xx_gpios_2bit),
S3C64XX_VA_GPIO + 0xE0, 0x20);
samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
ARRAY_SIZE(s3c64xx_gpios_4bit),
S3C64XX_VA_GPIO);
samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
ARRAY_SIZE(s3c64xx_gpios_4bit2));
} else {
WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
return -ENODEV;
}
return 0;
}
/* TODO: cleanup soc_is_* */
static __init int samsung_gpiolib_init(void)
{
struct samsung_gpio_chip *chip;
int i, nr_chips;
int group = 0;
/*
* Currently there are two drivers that can provide GPIO support for
* Samsung SoCs. For device tree enabled platforms, the new
* pinctrl-samsung driver is used, providing both GPIO and pin control
* interfaces. For legacy (non-DT) platforms this driver is used.
*/
if (of_have_populated_dt())
return -ENODEV;
samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
if (soc_is_s3c24xx()) {
s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
} else if (soc_is_s3c64xx()) {
samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
ARRAY_SIZE(s3c64xx_gpios_2bit),
S3C64XX_VA_GPIO + 0xE0, 0x20);
samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
ARRAY_SIZE(s3c64xx_gpios_4bit),
S3C64XX_VA_GPIO);
samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
ARRAY_SIZE(s3c64xx_gpios_4bit2));
} else if (soc_is_s5pv210()) {
group = 0;
chip = s5pv210_gpios_4bit;
nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
for (i = 0; i < nr_chips; i++, chip++) {
if (!chip->config) {
chip->config = &samsung_gpio_cfgs[3];
chip->group = group++;
}
}
samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
#endif
} else {
WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
return -ENODEV;
}
return 0;
}
static int __init s5p64x0_gpiolib_init(void)
{
unsigned int chipid;
chipid = __raw_readl(S5P64X0_SYS_ID);
s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
ARRAY_SIZE(s5p64x0_gpio_cfgs));
if ((chipid & 0xff000) == 0x50000) {
samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
ARRAY_SIZE(s5p6450_gpio_2bit));
samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit,
ARRAY_SIZE(s5p6450_gpio_4bit));
samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2,
ARRAY_SIZE(s5p6450_gpio_4bit2));
s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2,
ARRAY_SIZE(s5p6450_gpio_rbank_4bit2));
} else {
samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit,
ARRAY_SIZE(s5p6440_gpio_2bit));
samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
ARRAY_SIZE(s5p6440_gpio_4bit));
samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
ARRAY_SIZE(s5p6440_gpio_4bit2));
s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
}
return 0;
}
