Exemplo n.º 1
0
static void setup_save(struct host1x_hwctx_handler *p, u32 *ptr)
{
	int pipe, i;
	unsigned int old_restore_count, incr_count;
	struct gpu_info gpu_info;
	struct save_info info = {
		ptr,
		SAVE_BEGIN_V1_SIZE,
		RESTORE_BEGIN_SIZE,
		SAVE_INCRS,
		1
	};

	if (info.ptr) {
		save_begin_v1(p, info.ptr);
		info.ptr += SAVE_BEGIN_V1_SIZE;
	}

	tegra_gpu_get_info(&gpu_info);

	/* save regs for per pixel pipe, this has to be before the global
	 * one. Advance the rest of the pipes' output pointer to match with
	 * the pipe 0's.
	*/
	for (pipe = 1; pipe < gpu_info.num_pixel_pipes; pipe++)
		incr_mem_output_pointer(&info, pipe, RESTORE_BEGIN_SIZE);

	for (pipe = gpu_info.num_pixel_pipes - 1; pipe >= 0; pipe--) {
		old_restore_count = info.restore_count;
		setup_save_regs(&info,
				ctxsave_regs_3d_per_pipe,
				ARRAY_SIZE(ctxsave_regs_3d_per_pipe),
				(unsigned int) pipe);
		/* Advance the rest of the pipes' output pointer to match with
		 * the current pipe's one.
		*/
		incr_count = info.restore_count - old_restore_count;
		for (i = 0; i < pipe; i++)
			incr_mem_output_pointer(&info, (unsigned int) i,
						incr_count);
	}

	/* save regs for global. Use pipe 0 to do the save */
	setup_save_regs(&info,
			ctxsave_regs_3d_global,
			ARRAY_SIZE(ctxsave_regs_3d_global), 0);

	if (info.ptr) {
		save_end_v1(p, info.ptr);
		info.ptr += SAVE_END_V1_SIZE;
	}

	wmb();

	p->save_size = info.save_count + SAVE_END_V1_SIZE;
	p->restore_size = info.restore_count + RESTORE_END_SIZE;
	p->save_incrs = info.save_incrs;
	p->h.save_thresh = p->save_incrs;
	p->restore_incrs = info.restore_incrs;
}
Exemplo n.º 2
0
static void setup_save(struct host1x_hwctx_handler *p, u32 *ptr)
{
	struct save_info info = {
		ptr,
		SAVE_BEGIN_V1_SIZE,
		RESTORE_BEGIN_SIZE,
		SAVE_INCRS,
		1
	};
	int save_end_size = SAVE_END_V1_SIZE;

	if (info.ptr) {
		save_begin_v1(p, info.ptr);
		info.ptr += SAVE_BEGIN_V1_SIZE;
	}

	/* read from set0, write cmds through set0, restore to set0 and 1 */
	switch_gpu(&info, 0, 1, 3);

	/* save regs that are common to both sets */
	setup_save_regs(&info,
			ctxsave_regs_3d_global,
			ARRAY_SIZE(ctxsave_regs_3d_global));

	/* read from set 0, write cmds through set0, restore to set0 */
	switch_gpu(&info, 0, 1, 1);

	/* save set 0 specific regs */
	setup_save_regs(&info,
			ctxsave_regs_3d_perset,
			ARRAY_SIZE(ctxsave_regs_3d_perset));


	/* read from set1, write cmds through set1, restore to set1 */
	switch_gpu(&info, 1, 2, 2);
	/* note offset at which set 1 restore starts */
	restore_set1_offset = info.restore_count;
	/* save set 1 specific regs */
	setup_save_regs(&info,
			ctxsave_regs_3d_perset,
			ARRAY_SIZE(ctxsave_regs_3d_perset));


	/* read from set0, write cmds through set1, restore to set0 and 1 */
	switch_gpu(&info, 0, 2, 3);

	if (info.ptr) {
		save_end_v1(p, info.ptr);
		info.ptr += SAVE_END_V1_SIZE;
	}

	wmb();

	p->save_size = info.save_count + save_end_size;
	p->restore_size = info.restore_count + RESTORE_END_SIZE;
	p->save_incrs = info.save_incrs;
	p->save_thresh = p->save_incrs - SAVE_THRESH_OFFSET;
	p->restore_incrs = info.restore_incrs;
}
Exemplo n.º 3
0
static void __init setup_save(u32 *ptr)
{
	struct save_info info = {
		ptr,
		SAVE_BEGIN_V1_SIZE,
		RESTORE_BEGIN_SIZE,
		SAVE_INCRS,
		1
	};
	int save_end_size = SAVE_END_V1_SIZE;

	BUG_ON(register_sets > 2);

	if (info.ptr) {
		save_begin_v1(info.ptr);
		info.ptr += SAVE_BEGIN_V1_SIZE;
	}

	/* read from set0, write cmds through set0, restore to set0 and 1 */
	if (register_sets == 2)
		switch_gpu(&info, 0, 1, 3);

	/* save regs that are common to both sets */
	setup_save_regs(&info,
			ctxsave_regs_3d_global,
			ARRAY_SIZE(ctxsave_regs_3d_global));

	/* read from set 0, write cmds through set0, restore to set0 */
	if (register_sets == 2)
		switch_gpu(&info, 0, 1, 1);

	/* save set 0 specific regs */
	setup_save_regs(&info,
			ctxsave_regs_3d_perset,
			ARRAY_SIZE(ctxsave_regs_3d_perset));

	if (register_sets == 2) {
		/* read from set1, write cmds through set1, restore to set1 */
		switch_gpu(&info, 1, 2, 2);
		/* note offset at which set 1 restore starts */
		restore_set1_offset = info.restore_count;
		/* save set 1 specific regs */
		setup_save_regs(&info,
				ctxsave_regs_3d_perset,
				ARRAY_SIZE(ctxsave_regs_3d_perset));
	}

	/* read from set0, write cmds through set1, restore to set0 and 1 */
	if (register_sets == 2)
		switch_gpu(&info, 0, 2, 3);

	if (info.ptr) {
		save_end_v1(info.ptr);
		info.ptr += SAVE_END_V1_SIZE;
	}

	wmb();

	save_size = info.save_count + save_end_size;
	nvhost_3dctx_restore_size = info.restore_count + RESTORE_END_SIZE;
	nvhost_3dctx_save_incrs = info.save_incrs;
	nvhost_3dctx_save_thresh = nvhost_3dctx_save_incrs
			- SAVE_THRESH_OFFSET;
	nvhost_3dctx_restore_incrs = info.restore_incrs;
}