/*init global regs for pm */
static void init_gr(void)
{
int val;
/* remap iram to 0x00000000*/
sci_glb_set(REG_AHB_REMAP, BIT(0));
#ifdef CONFIG_NKERNEL
/*force close cp*/
__raw_writel(0x00000001, REG_AHB_CP_SLEEP_CTRL);
#endif
/* AHB_PAUSE */
val = sci_glb_read(REG_AHB_AHB_PAUSE, -1UL);
val &= ~(MCU_CORE_SLEEP | MCU_DEEP_SLEEP_EN | MCU_SYS_SLEEP_EN);
sci_glb_write(REG_AHB_AHB_PAUSE, val, -1UL );
/* AHB_CTL1 */
val = sci_glb_read(REG_AHB_AHB_CTL1, -1UL);
val |= (AHB_CTRL1_EMC_CH_AUTO_GATE_EN |
AHB_CTRL1_ARM_AUTO_GATE_EN |
AHB_CTRL1_AHB_AUTO_GATE_EN |
AHB_CTRL1_MCU_AUTO_GATE_EN |
AHB_CTRL1_ARM_DAHB_SLEEP_EN |
AHB_CTRL1_MSTMTX_AUTO_GATE_EN);
val &= ~AHB_CTRL1_EMC_AUTO_GATE_EN;
sci_glb_write(REG_AHB_AHB_CTL1, val, -1UL );
/* enable XTL auto power down, set bufon_ctrl[17:16] 0 */
val = sci_glb_read(REG_GLB_CLK_EN, -1UL);
val |= MCU_XTLEN_AUTOPD_EN;
val |= BUFON_CTRL_HI;
sci_glb_write(REG_GLB_CLK_EN, val, -1UL );
}
void dsi_print_global_config(void)
{
u32 reg_val0, reg_val1, reg_val2;
reg_val0 = sci_glb_read(REG_AP_AHB_MISC_CKG_EN, 0xffffffff);
reg_val1 = sci_glb_read(DSI_REG_EB, 0xffffffff);
reg_val2 = sci_glb_read(REG_AON_APB_PWR_CTRL, 0xffffffff);
printk("sprdfb: dsi: 0x20E00040 = 0x%x, 0x20E00000 = 0x%x, 0x402E0024 = 0x%x\n",
reg_val0, reg_val1, reg_val2);
}
static void pm_debug_save_ahb_glb_regs(void)
{
debug_status[0] = sci_glb_read(REG_AHB_AHB_STATUS, -1UL);
debug_status[1] = sci_glb_read(REG_AHB_AHB_CTL0, -1UL);
debug_status[2] = sci_glb_read(REG_AHB_AHB_CTL1, -1UL);
debug_status[3] = sci_glb_read(REG_AHB_AHB_STATUS, -1UL);
debug_status[4] = sci_glb_read(REG_GLB_GEN0, -1UL);
debug_status[5] = sci_glb_read(REG_GLB_GEN1, -1UL);
debug_status[6] = sci_glb_read(REG_GLB_STC_DSP_ST, -1UL);
debug_status[7] = sci_glb_read(REG_GLB_BUSCLK, -1UL);
debug_status[8] = sci_glb_read(REG_GLB_CLKDLY, -1UL);
}
static void wait_until_uart1_tx_done(void)
{
u32 tx_fifo_val;
u32 really_done = 0;
u32 timeout = 2000;
/*uart1 owner dsp sel*/
if (sci_glb_read(REG_GLB_PCTRL, -1UL) & (1<<8)/* UART1_SEL */) return ;
tx_fifo_val = __raw_readl(UART_STS1);
tx_fifo_val >>= 8;
tx_fifo_val &= 0xff;
while(tx_fifo_val != 0) {
if (timeout <= 0) break;
udelay(100);
tx_fifo_val = __raw_readl(UART_STS1);
tx_fifo_val >>= 8;
tx_fifo_val &= 0xff;
timeout--;
}
timeout = 30;
really_done = __raw_readl(UART_STS0);
while(!(really_done & UART_TRANSFER_REALLY_OVER)) {
if (timeout <= 0) break;
udelay(100);
really_done = __raw_readl(UART_STS0);
timeout--;
}
}
/* arm core + arm sys */
static void mcu_sleep(void)
{
u32 val;
SAVE_GLOBAL_REG;
disable_audio_module();
disable_ahb_module();
/* FIXME: whether enable emc auto gate or not in mcu sleep
val = sci_glb_read(REG_AHB_AHB_CTL1, -1UL);
val |= AHB_CTRL1_EMC_AUTO_GATE_EN;
sci_glb_write(REG_AHB_AHB_CTL1, val, -1UL );
*/
val = sci_glb_read(REG_AHB_AHB_PAUSE, -1UL);
val &= ~( MCU_CORE_SLEEP | MCU_DEEP_SLEEP_EN | MCU_SYS_SLEEP_EN );
/* FIXME: enable sys sleep in final version
val |= MCU_SYS_SLEEP_EN;
*/
sci_glb_write(REG_AHB_AHB_PAUSE, val, -1UL );
pm_debug_save_ahb_glb_regs( );
cpu_do_idle();
hard_irq_set();
RESTORE_GLOBAL_REG;
}
static void setup_autopd_mode(void)
{
#if 0
//debug only
sci_glb_write(REG_GLB_POWCTL0, 0x01000a20|(1<<23), -1UL);
#endif
#if 1
sci_glb_write(REG_GLB_MM_PWR_CTL, 0x06000320|PD_AUTO_EN, -1UL); /*MM*/
sci_glb_write(REG_GLB_G3D_PWR_CTL, 0x06000320|PD_AUTO_EN, -1UL);/*GPU*/
sci_glb_write(REG_GLB_CEVA_L1RAM_PWR_CTL, 0x04000720/*|PD_AUTO_EN*/, -1UL);
sci_glb_write(REG_GLB_GSM_PWR_CTL, 0x05000520/*|PD_AUTO_EN*/, -1UL);/*GSM*/
sci_glb_write(REG_GLB_TD_PWR_CTL, 0x05000520/*|PD_AUTO_EN*/, -1UL);/*TD*/
sci_glb_write(REG_GLB_PERI_PWR_CTL, 0x03000920/*|PD_AUTO_EN*/, -1UL);
if (sci_glb_read(REG_AHB_CHIP_ID, -1UL) == CHIP_ID_VER_0) {
sci_glb_write(REG_GLB_ARM_SYS_PWR_CTL, 0x02000f20 |PD_AUTO_EN, -1UL);
sci_glb_write(REG_GLB_POWCTL0, 0x07000a20|(1<<23), -1UL );
}else {
sci_glb_write(REG_GLB_ARM_SYS_PWR_CTL, 0x02000f20|PD_AUTO_EN, -1UL);
sci_glb_write(REG_GLB_POWCTL0, 0x07000a20|(1<<23), -1UL);
/* sci_glb_set(REG_GLB_POWCTL1, DSP_ROM_SLP_PD_EN|MCU_ROM_SLP_PD_EN); */
}
#endif
}
static void efuse_reset(void)
{
/* should enable module before soft reset efuse */
WARN_ON(!sci_glb_read(REG_AON_APB_APB_EB0, BIT_EFUSE_EB));
sci_glb_set(REG_AON_APB_APB_RST0, BIT_EFUSE_SOFT_RST);
udelay(5);
sci_glb_clr(REG_AON_APB_APB_RST0, BIT_EFUSE_SOFT_RST);
}
static void print_ahb(void)
{
u32 val = sci_glb_read(REG_AHB_AHB_CTL0, -1UL);
printk("##: REG_AHB_AHB_CTL0 = %08x.\n", val);
if (val & AHB_CTL0_DCAM_EN) printk("AHB_CTL0_DCAM_EN =1.\n");
if (val & AHB_CTL0_CCIR_IN_EN) printk("AHB_CTL0_CCIR_IN_EN =1. CCIR enable\n");
if (val & AHB_CTL0_LCDC_EN) printk("AHB_CTL0_LCDC_EN =1.\n");
if (val & AHB_CTL0_SDIO0_EN) printk("AHB_CTL0_SDIO0_EN =1.\n");
if (val & AHB_CTL0_USBD_EN) printk("AHB_CTL0_USBD_EN =1.\n");
if (val & AHB_CTL0_DMA_EN) printk("AHB_CTL0_DMA_EN =1.\n");
if (val & AHB_CTL0_BM0_EN) printk("AHB_CTL0_BM0_EN =1.\n");
if (val & AHB_CTL0_NFC_EN) printk("AHB_CTL0_NFC_EN =1.\n");
if (val & AHB_CTL0_CCIR_EN) printk("AHB_CTL0_CCIR_EN =1. CCIR clock enable\n");
if (val & AHB_CTL0_DCAM_MIPI_EN) printk("AHB_CTL0_DCAM_MIPI_EN =1.\n");
if (val & AHB_CTL0_BM1_EN) printk("AHB_CTL0_BM1_EN =1.\n");
if (val & AHB_CTL0_ISP_EN) printk("AHB_CTL0_ISP_EN =1.\n");
if (val & AHB_CTL0_VSP_EN) printk("AHB_CTL0_VSP_EN =1.\n");
if (val & AHB_CTL0_ROT_EN) printk("AHB_CTL0_ROT_EN =1.\n");
if (val & AHB_CTL0_BM2_EN) printk("AHB_CTL0_BM2_EN =1.\n");
if (val & AHB_CTL0_BM3_EN) printk("AHB_CTL0_BM3_EN =1.\n");
if (val & AHB_CTL0_BM4_EN) printk("AHB_CTL0_BM4_EN =1.\n");
if (val & AHB_CTL0_SDIO1_EN) printk("AHB_CTL0_SDIO1_EN =1.\n");
if (val & AHB_CTL0_G2D_EN) printk("AHB_CTL0_G2D_EN =1.\n");
if (val & AHB_CTL0_G3D_EN) printk("AHB_CTL0_G3D_EN =1.\n");
if (val & AHB_CTL0_DISPC_EN) printk("AHB_CTL0_DISPC_EN =1.\n");
if (val & AHB_CTL0_EMMC_EN) printk("AHB_CTL0_EMMC_EN =1.\n");
if (val & AHB_CTL0_SDIO2_EN) printk("AHB_CTL0_SDIO2_EN =1.\n");
if (val & AHB_CTL0_SPINLOCK_EN) printk("AHB_CTL0_SPINLOCK_EN =1.\n");
if (val & AHB_CTL0_AHB_ARCH_EB) printk("AHB_CTL0_AHB_ARCH_EB =1. AHB bus HCLK enable\n");
if (val & AHB_CTL0_EMC_EN) printk("AHB_CTL0_EMC_EN =1.\n");
if (val & AHB_CTL0_AXIBUSMON0_EN) printk("AHB_CTL0_AXIBUSMON0_EN =1.\n");
if (val & AHB_CTL0_AXIBUSMON1_EN) printk("AHB_CTL0_AXIBUSMON1_EN =1.\n");
if (val & AHB_CTL0_AXIBUSMON2_EN) printk("AHB_CTL0_AXIBUSMON2_EN =1.\n");
val = sci_glb_read(REG_AHB_AHB_CTL1, -1UL);
printk("##: REG_AHB_AHB_CTL1 = %08x.\n", val);
val = sci_glb_read(REG_AHB_AHB_CTL2, -1UL);
printk("##: REG_AHB_AHB_CTL2 = %08x.\n", val);
if (val & AHB_CTL2_DISPMTX_CLK_EN ) printk("AHB_CTL2_DISPMTX_CLK_EN =1.\n");
if (val & AHB_CTL2_MMMTX_CLK_EN ) printk("AHB_CTL2_MMMTX_CLK_EN =1.\n");
if (val & AHB_CTL2_DISPC_CORE_CLK_EN) printk("AHB_CTL2_DISPC_CORE_CLK_EN=1.\n");
if (val & AHB_CTL2_LCDC_CORE_CLK_EN) printk("AHB_CTL2_LCDC_CORE_CLK_EN=1.\n");
if (val & AHB_CTL2_ISP_CORE_CLK_EN) printk("AHB_CTL2_ISP_CORE_CLK_EN=1.\n");
if (val & AHB_CTL2_VSP_CORE_CLK_EN) printk("AHB_CTL2_VSP_CORE_CLK_EN=1.\n");
if (val & AHB_CTL2_DCAM_CORE_CLK_EN) printk("AHB_CTL2_DCAM_CORE_CLK_EN=1.\n");
val = sci_glb_read(REG_AHB_AHB_CTL3, -1UL);
printk("##: REG_AHB_AHB_CTL3 = %08x.\n", val);
val = sci_glb_read(REG_AHB_MIPI_PHY_CTRL, -1UL);
printk("##: REG_AHB_MIPI_PHY_CTRL= %08x.\n", val);
val = sci_glb_read(REG_AHB_AHB_STATUS, -1UL);
printk("##:REG_AHB_AHB_STATUS = %08x.\n", val);
}
static void aux_clk_config(u32 clk_sel)
{
u32 reg_val;
if(clk_sel < aux_clk_max){
/*select pin function to func 0*/
reg_val = sci_glb_read(clk_cfg_info.aux_pin,-1UL);
reg_val &= ~(0x3 << 4);
sci_glb_write(clk_cfg_info.aux_pin,reg_val,-1UL);
/*enable aux clock*/
sci_glb_set(clk_cfg_info.aux_ena,0x1 << 2);
/*select aux clock source*/
sci_glb_set(clk_cfg_info.aux_sel,clk_sel);
}
}
void __init sci_enable_timer_early(void)
{
/* enable timer & syscnt in global regs */
int i = 0, j = 0;
sci_glb_set(REG_AON_APB_APB_EB0,
BIT_AON_TMR_EB | BIT_AP_SYST_EB | BIT_AP_TMR0_EB);
#if defined CONFIG_LOCAL_TIMERS && !defined CONFIG_HAVE_ARM_ARCH_TIMER
sci_glb_set(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB);
for (i = 0; i < 4; i++) {
#else
sci_glb_clr(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB);
for (i = 0; i < 2; i++) {
#endif
for (j = 0; j < 3; j++) {
__gptimer_ctl(i, j, TIMER_DISABLE, 0);
__raw_writel(TIMER_INT_CLR, TIMER_INT(i, j));
}
}
#if defined(CONFIG_ARCH_SCX30G) || defined(CONFIG_ARCH_SCX35L)
/*timer1 fixed 32768 clk */
sched_clock_source_freq = 32768;
#else /*timer2 clk source is from apb clk */
val = sci_glb_read(REG_AON_CLK_AON_APB_CFG, -1) & 0x3;
if (val == 0x1)
sched_clock_source_freq = 76800000;
else if (val == 0x2)
sched_clock_source_freq = 96000000;
else if (val == 0x3)
sched_clock_source_freq = 128000000;
else
sched_clock_source_freq = 26000000; /*default setting */
#endif
gptimer_clock_source_freq = sched_clock_source_freq;
#if !defined (CONFIG_HAVE_ARM_ARCH_TIMER)
__sched_clock_init(sched_clock_source_freq);
#endif
}
u32 get_sys_cnt(void)
{
u32 val = 0;
val = __raw_readl(SYSCNT_SHADOW_CNT);
return val;
}
static void dispc_print_clk(void)
{
uint32_t reg_val0,reg_val1,reg_val2;
reg_val0 = sci_glb_read(SPRD_AONAPB_BASE+0x4, 0xffffffff);
reg_val1 = sci_glb_read(SPRD_AHB_BASE, 0xffffffff);
reg_val2 = sci_glb_read(SPRD_APBREG_BASE, 0xffffffff);
printk("autotst_dispc:0x402e0004 = 0x%x 0x20d00000 = 0x%x 0x71300000 = 0x%x \n",reg_val0, reg_val1, reg_val2);
reg_val0 = sci_glb_read(SPRD_APBCKG_BASE+0x34, 0xffffffff);
reg_val1 = sci_glb_read(SPRD_APBCKG_BASE+0x30, 0xffffffff);
reg_val2 = sci_glb_read(SPRD_APBCKG_BASE+0x2c, 0xffffffff);
printk("autotst_dispc:0x71200034 = 0x%x 0x71200030 = 0x%x 0x7120002c = 0x%x \n",reg_val0, reg_val1, reg_val2);
}
static int is_dsp_sleep(void)
{
u32 val;
val = sci_glb_read(REG_GLB_STC_DSP_ST, -1UL);
if (GR_EMC_STOP & val)
printk("#####: REG_GLB_STC_DSP_ST[GR_EMC_STOP] is set!\n");
else
printk("#####: REG_GLB_STC_DSP_ST[GR_EMC_STOP] is NOT set!\n");
if (GR_MCU_STOP & val)
printk("#####: REG_GLB_STC_DSP_ST[GR_MCU_STOP] is set!\n");
else
printk("#####: REG_GLB_STC_DSP_ST[GR_MCU_STOP] is NOT set!\n");
if (GR_DSP_STOP & val)
printk("#####: REG_GLB_STC_DSP_ST[DSP_STOP] is set!\n");
else
printk("#####: REG_GLB_STC_DSP_ST[DSP_STOP] is NOT set!\n");
return 0;
}
void check_pd(void)
{
#define CHECK_PD(_val, _reg) { \
val = sci_glb_read(_reg, -1UL); \
if(val != (_val)) \
printk("### setting not same:"#_reg" = %08x !=%08x\n", val, (_val)); \
}
unsigned int val;
CHECK_PD(0x06000320|PD_AUTO_EN, REG_GLB_MM_PWR_CTL);
CHECK_PD(0x06000320|PD_AUTO_EN, REG_GLB_G3D_PWR_CTL);
CHECK_PD(0x04000720, REG_GLB_CEVA_L1RAM_PWR_CTL);
CHECK_PD(0x05000520, REG_GLB_GSM_PWR_CTL);
CHECK_PD(0x05000520, REG_GLB_TD_PWR_CTL);
CHECK_PD(0x03000920, REG_GLB_PERI_PWR_CTL);
if (sci_glb_read(REG_AHB_CHIP_ID, -1UL) == CHIP_ID_VER_0) {
CHECK_PD(0x02000f20|PD_AUTO_EN, REG_GLB_ARM_SYS_PWR_CTL);
CHECK_PD(0x01000a20|(1<<23), REG_GLB_POWCTL0);
}else{
CHECK_PD(0x02000f20|PD_AUTO_EN, REG_GLB_ARM_SYS_PWR_CTL);
CHECK_PD(0x01000a20|(1<<23), REG_GLB_POWCTL0);
}
}
static void dsi_core_and_function(unsigned int addr,unsigned int data)
{
sci_glb_write(addr,(sci_glb_read(addr, 0xffffffff) & data), 0xffffffff);
}
static uint32_t dsi_core_read_function(uint32_t addr, uint32_t offset)
{
return sci_glb_read(addr + offset, 0xffffffff);
}
static __used int sc8825_get_sleep_mod( void ){
int val, ret;
printk("*** REG_GLB_GEN1: 0x%x ***\n", sci_glb_read(REG_GLB_GEN1, -1UL));
printk("*** REG_GLB_STC_DSP_ST: 0x%x ***\n", sci_glb_read(REG_GLB_STC_DSP_ST, -1UL));
printk("*** REG_GLB_BUSCLK: 0x%x ***\n", sci_glb_read(REG_GLB_BUSCLK, -1UL));
printk("*** REG_GLB_CLKDLY: 0x%x ***\n", sci_glb_read(REG_GLB_CLKDLY, -1UL));
val = sci_glb_read(REG_AHB_AHB_CTL0, -1UL);
ret = val & AHB_CTL0_MASK;
val = sci_glb_read(REG_AHB_AHB_CTL2, -1UL);
ret = ret | (val & AHB_CTL0_MASK);
if(ret != 0){
printk("*** AHB_CTL0: 0x%x ***\n", sci_glb_read(REG_AHB_AHB_CTL0, -1UL));
printk("*** AHB_CTL2: 0x%x ***\n", sci_glb_read(REG_AHB_AHB_CTL2, -1UL));
printk("*** %s, ret:0x%x ****\n", __func__, ret);
return DEVICE_AHB;
}
val = sci_glb_read(REG_GLB_GEN0, -1UL);
ret = val & GR_GEN0_MASK;
printk("*** GR_GEN0: 0x%x, ret:0x%x ***\n", sci_glb_read(REG_GLB_GEN0, -1UL), ret);
if(ret == 0){
val = sci_glb_read(REG_GLB_CLK_EN, -1UL);
ret = val & GR_CLK_EN_MASK;
printk("*** GR_CLK_EN: 0x%x, ret:0x%x ***\n", sci_glb_read(REG_GLB_CLK_EN, -1UL), ret);
if(ret == 0){
val = sci_glb_read(REG_GLB_GEN1, -1UL);
ret = val & GR_GEN1_MASK;
printk("*** GR_GEN1: 0x%x, ret:0x%x ***\n", sci_glb_read(REG_GLB_GEN1, -1UL), ret);
if(ret == 0){
return 0;
}else{
return DEVICE_APB;
}
}else{
return DEVICE_APB;
}
}else{
return DEVICE_APB;
}
return 0;
}
/* chip sleep*/
int deep_sleep(void)
{
u32 val, ret = 0;
u32 holding;
wait_until_uart1_tx_done();
SAVE_GLOBAL_REG;
disable_audio_module();
disable_apb_module();
disable_ahb_module();
/* for dsp wake-up */
val = __raw_readl(INT0_IRQ_ENB);
val |= SCI_INTC_IRQ_BIT(IRQ_DSP0_INT);
val |= SCI_INTC_IRQ_BIT(IRQ_DSP1_INT);
__raw_writel(val, INT0_IRQ_ENB);
val = __raw_readl(INT0_FIQ_ENB);
val |= SCI_INTC_IRQ_BIT(IRQ_DSP0_INT);
val |= SCI_INTC_IRQ_BIT(IRQ_DSP1_INT);
__raw_writel(val, INT0_FIQ_ENB);
/* prevent uart1 */
__raw_writel(INT0_IRQ_MASK, INT0_IRQ_DIS);
/*L2X0_POWER_CTRL, auto_clock_gate, standby_mode_enable*/
__raw_writel(0x3, SPRD_L2_BASE+0xF80);
#ifdef FORCE_DISABLE_DSP
/* close debug modules, only for fpga or debug */
/*
dbg_module_close();
*/
dsp_and_modem_force_close();
#endif
/*
* pm_debug_set_wakeup_timer();
*/
/* FIXME: enable emc auto gate in final version
val = sci_glb_read(REG_AHB_AHB_CTL1, -1UL);
val |= AHB_CTRL1_EMC_AUTO_GATE_EN;
sci_glb_write(REG_AHB_AHB_CTL1, val, -1UL);
*/
/*go deepsleep when all PD auto poweroff en*/
val = sci_glb_read(REG_AHB_AHB_PAUSE, -1UL);
val &= ~( MCU_CORE_SLEEP | MCU_DEEP_SLEEP_EN | MCU_SYS_SLEEP_EN );
val |= (MCU_SYS_SLEEP_EN | MCU_DEEP_SLEEP_EN);
sci_glb_write(REG_AHB_AHB_PAUSE, val, -1UL);
/* set entry when deepsleep return*/
save_reset_vector();
set_reset_vector();
/* check globle key registers */
pm_debug_save_ahb_glb_regs( );
/* indicate cpu stopped */
holding = sci_glb_read(REG_AHB_HOLDING_PEN, -1UL);
sci_glb_write(REG_AHB_HOLDING_PEN, (holding | AP_ENTER_DEEP_SLEEP) , -1UL );
save_emc_trainig_data(repower_param);
ret = sp_pm_collapse(0, 1);
hard_irq_set();
/*clear dsp fiq, for dsp wakeup*/
__raw_writel(ICLR_DSP_FRQ0_CLR, SPRD_IPI_ICLR);
__raw_writel(ICLR_DSP_FIQ1_CLR, SPRD_IPI_ICLR);
/*disable dsp fiq*/
val = SCI_INTC_IRQ_BIT(IRQ_DSP0_INT) | SCI_INTC_IRQ_BIT(IRQ_DSP1_INT);
__raw_writel(val , INT0_FIQ_DIS);
/*clear the deep sleep status*/
sci_glb_write(REG_AHB_HOLDING_PEN, (holding & ~AP_ENTER_DEEP_SLEEP), -1UL );
/* FIXME: clear emc auto gate in final version
val = sci_glb_read(REG_AHB_AHB_CTL1, -1UL);
val &= ~AHB_CTRL1_EMC_AUTO_GATE_EN;
sci_glb_write(REG_AHB_AHB_CTL1, val, -1UL);
*/
restore_reset_vector();
RESTORE_GLOBAL_REG;
udelay(5);
if (ret) cpu_init();
return ret;
}
static void print_gr(void)
{
u32 val = sci_glb_read(REG_GLB_GEN0, -1UL);
printk("##: GR_GEN0 = %08x.\n", val);
if (val & GEN0_UART3_EN) printk("GEN0_UART3_EN =1.\n");
if (val & GEN0_SPI2_EN) printk("GEN0_SPI2_EN =1.\n");
if (val & GEN0_TIMER_EN) printk("GEN0_TIMER_EN =1.\n");
if (val & GEN0_SIM0_EN) printk("GEN0_SIM0_EN =1.\n");
if (val & GEN0_I2C_EN) printk("GEN0_I2C_EN =1.\n");
if (val & GEN0_GPIO_EN) printk("GEN0_GPIO_EN =1.\n");
if (val & GEN0_ADI_EN) printk("GEN0_ADI_EN =1.\n");
if (val & GEN0_EFUSE_EN) printk("GEN0_EFUSE_EN =1.\n");
if (val & GEN0_KPD_EN) printk("GEN0_KPD_EN =1.\n");
if (val & GEN0_EIC_EN) printk("GEN0_EIC_EN =1.\n");
if (val & GEN0_I2S0_EN) printk("GEN0_I2S0_EN =1.\n");
if (val & GEN0_PIN_EN) printk("GEN0_PIN_EN =1.\n");
if (val & GEN0_CCIR_MCLK_EN) printk("GEN0_CCIR_MCLK_EN =1.\n");
if (val & GEN0_EPT_EN) printk("GEN0_EPT_EN =1.\n");
if (val & GEN0_SIM1_EN) printk("GEN0_SIM1_EN =1.\n");
if (val & GEN0_SPI0_EN) printk("GEN0_SPI0_EN =1.\n");
if (val & GEN0_SPI1_EN) printk("GEN0_SPI1_EN =1.\n");
if (val & GEN0_SYST_EN) printk("GEN0_SYST_EN =1.\n");
if (val & GEN0_UART0_EN) printk("GEN0_UART0_EN =1.\n");
if (val & GEN0_UART1_EN) printk("GEN0_UART1_EN =1.\n");
if (val & GEN0_UART2_EN) printk("GEN0_UART2_EN =1.\n");
if (val & GEN0_VB_EN) printk("GEN0_VB_EN =1.\n");
if (val & GEN0_EIC_RTC_EN) printk("GEN0_EIC_RTC_EN =1.\n");
if (val & GEN0_I2S1_EN) printk("GEN0_I2S1_EN =1.\n");
if (val & GEN0_KPD_RTC_EN) printk("GEN0_KPD_RTC_EN =1.\n");
if (val & GEN0_SYST_RTC_EN) printk("GEN0_SYST_RTC_EN =1.\n");
if (val & GEN0_TMR_RTC_EN) printk("GEN0_TMR_RTC_EN =1.\n");
if (val & GEN0_I2C1_EN) printk("GEN0_I2C1_EN =1.\n");
if (val & GEN0_I2C2_EN) printk("GEN0_I2C2_EN =1.\n");
if (val & GEN0_I2C3_EN) printk("GEN0_I2C3_EN =1.\n");
val = sci_glb_read(REG_GLB_GEN1, -1UL);
printk("##: REG_GLB_GEN1 = %08x.\n", val);
if (val & BIT_CLK_AUX0_EN ) printk(" CLK_AUX0_EN =1.\n");
if (val & BIT_CLK_AUX1_EN ) printk(" CLK_AUX1_EN =1.\n");
if (val & BIT_AUD_IF_EB ) printk(" AUD_IF_EB =1.\n");
if (val & BIT_AUD_TOP_EB ) printk(" AUD_TOP_EB =1.\n");
if (val & BIT_VBC_EN ) printk(" VBC_EN =1.\n");
if (val & BIT_AUDIF_AUTO_EN ) printk(" AUDIF_AUTO_EN =1.\n");
val = sci_glb_read(REG_GLB_CLK_EN, -1UL);
printk("##: GR_CLK_EN = %08x.\n", val);
if (val & CLK_PWM0_EN) printk("CLK_PWM0_EN =1.\n");
if (val & CLK_PWM1_EN) printk("CLK_PWM1_EN = 1.\n");
if (val & CLK_PWM2_EN) printk("CLK_PWM2_EN = 1.\n");
if (val & CLK_PWM3_EN) printk("CLK_PWM3_EN = 1.\n");
val = sci_glb_read(REG_GLB_BUSCLK, -1UL);
printk("##: GR_BUSCLK_ALM = %08x.\n", val);
if (val & ARM_VB_MCLKON) printk("ARM_VB_MCLKON =1.\n");
if (val & ARM_VB_DA0ON) printk("ARM_VB_DA0ON = 1.\n");
if (val & ARM_VB_DA1ON) printk("ARM_VB_DA1ON = 1.\n");
if (val & ARM_VB_ADCON) printk("ARM_VB_ADCON = 1.\n");
if (val & ARM_VB_ANAON) printk("ARM_VB_ANAON = 1.\n");
if (val & ARM_VB_ACC) printk("ARM_VB_ACC = 1.\n");
val = sci_glb_read(REG_GLB_CLK_GEN5, -1UL);
printk("##: GR_CLK_GEN5 = %08x.\n", val);
if (val & BIT(9)) printk("LDO_USB_PD =1.\n");
val = sci_glb_raw_read(REG_GLB_PCTRL);
printk("##: GLB_PCTL = %08x.\n", val);
if (val & BIT_MCU_MPLL_EN) printk("MCU_MPLL = 1.\n");
if (val & BIT_MCU_GPLL_EN) printk("MCU_GPLL = 1.\n");
if (val & BIT_MCU_DPLL_EN) printk("MCU_DPLL = 1.\n");
if (val & BIT_MCU_TDPLL_EN) printk("MCU_TDPLL = 1.\n");
val = sci_glb_raw_read(REG_GLB_TD_PLL_CTL);
printk("##: GLB_TD_PLL_CTL = %08x.\n", val);
if (!(val & BIT_TDPLL_DIV2OUT_FORCE_PD)) printk("clk_384m = 1.\n");
if (!(val & BIT_TDPLL_DIV3OUT_FORCE_PD)) printk("clk_256m = 1.\n");
if (!(val & BIT_TDPLL_DIV4OUT_FORCE_PD)) printk("clk_192m = 1.\n");
if (!(val & BIT_TDPLL_DIV5OUT_FORCE_PD)) printk("clk_153p6m = 1.\n");
val = sci_glb_read(REG_GLB_POWCTL1, -1UL);
printk("##: GR_POWCTL1 = %08x.\n", val);
val = sci_glb_read(REG_GLB_M_PLL_CTL0, -1UL);
printk("##: REG_GLB_M_PLL_CTL0 = %08x.\n", val);
val = sci_glb_read(REG_GLB_MM_PWR_CTL, -1UL);
printk("##: REG_GLB_MM_PWR_CTL = %08x.\n", val);
val = sci_glb_read(REG_GLB_CEVA_L1RAM_PWR_CTL, -1UL);
printk("##: REG_GLB_CEVA_L1RAM_PWR_CTL = %08x.\n", val);
val = sci_glb_read(REG_GLB_GSM_PWR_CTL, -1UL);
printk("##: REG_GLB_GSM_PWR_CTL = %08x.\n", val);
val = sci_glb_read(REG_GLB_TD_PWR_CTL, -1UL);
printk("##: GR_TD_PWR_CTRL = %08x.\n", val);
val = sci_glb_read(REG_GLB_PERI_PWR_CTL, -1UL);
printk("##: GR_PERI_PWR_CTRL = %08x.\n", val);
val = sci_glb_read(REG_GLB_ARM_SYS_PWR_CTL, -1UL);
printk("##: GR_ARM_SYS_PWR_CTRL = %08x.\n", val);
val = sci_glb_read(REG_GLB_G3D_PWR_CTL, -1UL);
printk("##: GR_G3D_PWR_CTRL = %08x.\n", val);
}
static void __inline __dma_clk_enable(void)
{
if (!sci_glb_read(REG_AP_AHB_AHB_EB, BIT_DMA_EB)) {
sci_glb_set(REG_AP_AHB_AHB_EB, BIT_DMA_EB);
}
}
static void print_debug_info(void)
{
unsigned int ahb_eb, apb_eb0, cp_slp_status0, cp_slp_status1, ldo_pd_ctrl,
ap_apb_eb, apb_pwrstatus0, apb_pwrstatus1, apb_pwrstatus2,
apb_pwrstatus3, mpll_cfg, dpll_cfg, emc_clk_cfg,
apb_slp_status, ap_sys_auto_sleep_cfg;
#if defined(CONFIG_ARCH_SCX15)
unsigned int ldo_dcdc_pd_ctrl;
#endif
ahb_eb = sci_glb_read(REG_AP_AHB_AHB_EB, -1UL);
ap_sys_auto_sleep_cfg = sci_glb_read(REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG, -1UL);
ap_apb_eb = sci_glb_read(REG_AP_APB_APB_EB, -1UL);
apb_eb0 = sci_glb_read(REG_AON_APB_APB_EB0, -1UL);
cp_slp_status0 = sci_glb_read(REG_PMU_APB_CP_SLP_STATUS_DBG0, -1UL);
cp_slp_status1 = sci_glb_read(REG_PMU_APB_CP_SLP_STATUS_DBG1, -1UL);
apb_pwrstatus0 = sci_glb_read(REG_PMU_APB_PWR_STATUS0_DBG, -1UL);
apb_pwrstatus1 = sci_glb_read(REG_PMU_APB_PWR_STATUS1_DBG, -1UL);
apb_pwrstatus2 = sci_glb_read(REG_PMU_APB_PWR_STATUS2_DBG, -1UL);
apb_pwrstatus3 = sci_glb_read(REG_PMU_APB_PWR_STATUS3_DBG, -1UL);
apb_slp_status = __raw_readl(REG_PMU_APB_SLEEP_STATUS);
mpll_cfg = sci_glb_read(REG_AON_APB_MPLL_CFG, -1UL);
dpll_cfg = sci_glb_read(REG_AON_APB_DPLL_CFG, -1UL);
emc_clk_cfg = sci_glb_read(REG_AON_CLK_EMC_CFG, -1UL);
ldo_pd_ctrl = sci_adi_read(ANA_REG_GLB_LDO_PD_CTRL);
#if defined(CONFIG_ARCH_SCX15)
ldo_dcdc_pd_ctrl = sci_adi_read(ANA_REG_GLB_LDO_DCDC_PD);
#endif
printk("###---- REG_AP_AHB_AHB_EB : 0x%08x\n", ahb_eb);
printk("###---- REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG : 0x%08x\n", ap_sys_auto_sleep_cfg);
printk("###---- REG_AP_APB_APB_EB : 0x%08x\n", ap_apb_eb);
printk("###---- REG_AON_APB_APB_EB0 : 0x%08x\n", apb_eb0);
printk("###---- REG_PMU_APB_CP_SLP_STATUS_DBG0 : 0x%08x\n", cp_slp_status0);
printk("###---- REG_PMU_APB_CP_SLP_STATUS_DBG1 : 0x%08x\n", cp_slp_status1);
printk("###---- REG_PMU_APB_PWR_STATUS0_DBG : 0x%08x\n", apb_pwrstatus0);
printk("###---- REG_PMU_APB_PWR_STATUS1_DBG : 0x%08x\n", apb_pwrstatus1);
printk("###---- REG_PMU_APB_PWR_STATUS2_DBG : 0x%08x\n", apb_pwrstatus2);
printk("###---- REG_PMU_APB_PWR_STATUS3_DBG : 0x%08x\n", apb_pwrstatus3);
printk("###---- REG_PMU_APB_SLEEP_STATUS : 0x%08x\n", apb_slp_status);
printk("###---- REG_AON_APB_MPLL_CFG : 0x%08x\n", mpll_cfg);
printk("###---- REG_AON_APB_DPLL_CFG : 0x%08x\n", dpll_cfg);
printk("###---- REG_AON_CLK_EMC_CFG : 0x%08x\n", emc_clk_cfg);
printk("###---- ANA_REG_GLB_LDO_PD_CTRL : 0x%08x\n", ldo_pd_ctrl);
#if defined(CONFIG_ARCH_SCX15)
printk("###---- ANA_REG_GLB_LDO_DCDC_PD_CTRL : 0x%08x\n", ldo_dcdc_pd_ctrl);
#endif
if (apb_eb0 & BIT_GPU_EB)
printk("###---- BIT_GPU_EB still set ----###\n");
if (apb_eb0 & BIT_MM_EB)
printk("###---- BIT_MM_EB still set ----###\n");
if (apb_eb0 & BIT_CA7_DAP_EB)
printk("###---- BIT_CA7_DAP_EB still set ----###\n");
if (ahb_eb & BIT_GSP_EB)
printk("###---- BIT_GSP_EB still set ----###\n");
if (ahb_eb & BIT_DISPC1_EB)
printk("###---- BIT_DISPC1_EB still set ----###\n");
if (ahb_eb & BIT_DISPC0_EB)
printk("###---- BIT_DISPC0_EB still set ----###\n");
if (ahb_eb & BIT_SDIO0_EB)
printk("###---- SDIO0_EB still set ----###\n");
if (ahb_eb & BIT_SDIO1_EB)
printk("###---- SDIO1_EB still set ----###\n");
if (ahb_eb & BIT_SDIO2_EB)
printk("###---- BIT_SDIO2_EB still set ----###\n");
if (ahb_eb & BIT_USB_EB)
printk("###---- BIT_USB_EB still set ----###\n");
if (ahb_eb & BIT_DMA_EB)
printk("###---- BIT_DMA_EB still set ----###\n");
if (ahb_eb & BIT_NFC_EB)
printk("###---- BIT_NFC_EB still set ----###\n");
if (ahb_eb & BIT_EMMC_EB)
printk("###---- BIT_EMMC_EB still set ----###\n");
#if defined(CONFIG_ARCH_SCX15)
if (ahb_eb & BIT_ZIPDEC_EB)
printk("###---- BIT_ZIPDEC_EB still set ----###\n");
if (ahb_eb & BIT_ZIPENC_EB)
printk("###---- BIT_ZIPENC_EB still set ----###\n");
if (ahb_eb & BIT_NANDC_ECC_EB)
printk("###---- BIT_NANDC_ECC_EB still set ----###\n");
if (ahb_eb & BIT_NANDC_2X_EB)
printk("###---- BIT_NANDC_2X_EB still set ----###\n");
if (ahb_eb & BIT_NANDC_EB)
printk("###---- BIT_NANDC_EB still set ----###\n");
#endif
/*A-die*/
if (!(ldo_pd_ctrl & BIT_DCDC_WPA_PD))
printk("###---- BIT_DCDC_WPA_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_CLSG_PD))
printk("###---- BIT_LDO_CLSG_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_USB_PD))
printk("###---- BIT_LDO_USB_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_CAMMOT_PD))
printk("###---- BIT_LDO_CAMMOT_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_CAMIO_PD))
printk("###---- BIT_LDO_CAMIO_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_CAMD_PD))
printk("###---- BIT_LDO_CAMD_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_CAMA_PD))
printk("###---- BIT_LDO_CAMA_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_SIM2_PD))
printk("###---- BIT_LDO_SIM2_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_SIM1_PD))
printk("###---- BIT_LDO_SIM1_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_SIM0_PD))
printk("###---- BIT_LDO_SIM0_PD power on! ----###\n");
if (!(ldo_pd_ctrl & BIT_LDO_SD_PD))
printk("###---- BIT_LDO_SD_PD power on! ----###\n");
#if defined(CONFIG_ARCH_SCX15)
if (!(ldo_dcdc_pd_ctrl & BIT_BG_PD))
printk("###---- BIT_BG_PD power on! ----###\n");
if (!(ldo_dcdc_pd_ctrl & BIT_LDO_CON_PD))
printk("###---- BIT_LDO_CON_PD power on! ----###\n");
if (!(ldo_dcdc_pd_ctrl & BIT_LDO_DCXO_PD))
printk("###---- BIT_LDO_DCXO_PD power on! ----###\n");
if (!(ldo_dcdc_pd_ctrl & BIT_LDO_EMMCIO_PD))
printk("###---- BIT_LDO_EMMCIO_PD power on! ----###\n");
if (!(ldo_dcdc_pd_ctrl & BIT_LDO_EMMCCORE_PD))
printk("###---- BIT_LDO_EMMCCORE_PD power on! ----###\n");
#endif
#if defined(CONFIG_ARCH_SCX15)
if (ap_apb_eb & BIT_UART4_EB)
printk("###---- BIT_UART4_EB set! ----###\n");
if (ap_apb_eb & BIT_UART3_EB)
printk("###---- BIT_UART3_EB set! ----###\n");
if (ap_apb_eb & BIT_UART2_EB)
printk("###---- BIT_UART2_EB set! ----###\n");
if (ap_apb_eb & BIT_UART1_EB)
printk("###---- BIT_UART1_EB set! ----###\n");
if (ap_apb_eb & BIT_UART0_EB)
printk("###---- BIT_UART0_EB set! ----###\n");
if (ap_apb_eb & BIT_I2C4_EB)
printk("###---- BIT_I2C4_EB set! ----###\n");
if (ap_apb_eb & BIT_I2C3_EB)
printk("###---- BIT_I2C3_EB set! ----###\n");
if (ap_apb_eb & BIT_I2C2_EB)
printk("###---- BIT_I2C2_EB set! ----###\n");
if (ap_apb_eb & BIT_I2C1_EB)
printk("###---- BIT_I2C1_EB set! ----###\n");
if (ap_apb_eb & BIT_I2C0_EB)
printk("###---- BIT_I2C0_EB set! ----###\n");
if (ap_apb_eb & BIT_IIS3_EB)
printk("###---- BIT_IIS3_EB set! ----###\n");
if (ap_apb_eb & BIT_IIS2_EB)
printk("###---- BIT_IIS2_EB set! ----###\n");
if (ap_apb_eb & BIT_IIS1_EB)
printk("###---- BIT_IIS1_EB set! ----###\n");
if (ap_apb_eb & BIT_IIS0_EB)
printk("###---- BIT_IIS0_EB set! ----###\n");
#endif
}
void dispc_print_clk(void)
{
printk("sprdfb: 0x20900200 = 0x%x\n", sci_glb_read(SPRD_AHB_BASE + 0x200));
printk("sprdfb: 0x20900208 = 0x%x\n", sci_glb_read(SPRD_AHB_BASE + 0x208));
printk("sprdfb: 0x20900220 = 0x%x\n", sci_glb_read(SPRD_AHB_BASE + 0x220));
}