static int arasan_sdhci_probe(struct udevice *dev)
{
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
u32 caps;
int ret;
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
SDHCI_QUIRK_BROKEN_R1B;
#ifdef CONFIG_ZYNQ_HISPD_BROKEN
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
#endif
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width,
caps, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
CONFIG_ZYNQ_SDHCI_MIN_FREQ, host->version,
host->quirks, 0);
host->mmc = &plat->mmc;
if (ret)
return ret;
host->mmc->priv = host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
}
static int s5p_sdhci_probe(struct udevice *dev)
{
struct s5p_sdhci_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
int ret;
ret = sdhci_get_config(gd->fdt_blob, dev->of_offset, host);
if (ret)
return ret;
ret = do_sdhci_init(host);
if (ret)
return ret;
ret = sdhci_setup_cfg(&plat->cfg, host, 52000000, 400000);
if (ret)
return ret;
host->mmc = &plat->mmc;
host->mmc->priv = host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
}
static int arasan_sdhci_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
struct rockchip_sdhc *prv = dev_get_priv(dev);
struct sdhci_host *host = &prv->host;
int max_frequency, ret;
struct clk clk;
max_frequency = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"max-frequency", 0);
ret = clk_get_by_index(dev, 0, &clk);
if (!ret) {
ret = clk_set_rate(&clk, max_frequency);
if (IS_ERR_VALUE(ret))
printf("%s clk set rate fail!\n", __func__);
} else {
printf("%s fail to get clk\n", __func__);
}
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
host->max_clk = max_frequency;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
host->mmc = &plat->mmc;
if (ret)
return ret;
host->mmc->priv = &prv->host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
}
static int k3_arasan_sdhci_probe(struct udevice *dev)
{
struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
struct power_domain sdhci_pwrdmn;
struct clk clk;
unsigned long clock;
int ret;
ret = power_domain_get_by_index(dev, &sdhci_pwrdmn, 0);
if (ret) {
dev_err(dev, "failed to get power domain\n");
return ret;
}
ret = power_domain_on(&sdhci_pwrdmn);
if (ret) {
dev_err(dev, "Power domain on failed\n");
return ret;
}
ret = clk_get_by_index(dev, 0, &clk);
if (ret) {
dev_err(dev, "failed to get clock\n");
return ret;
}
clock = clk_get_rate(&clk);
if (IS_ERR_VALUE(clock)) {
dev_err(dev, "failed to get rate\n");
return clock;
}
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
SDHCI_QUIRK_BROKEN_R1B;
host->max_clk = clock;
ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
K3_ARASAN_SDHCI_MIN_FREQ);
host->mmc = &plat->mmc;
if (ret)
return ret;
host->mmc->priv = host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
return sdhci_probe(dev);
}
static int arasan_sdhci_probe(struct udevice *dev)
{
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct arasan_sdhci_priv *priv = dev_get_priv(dev);
struct sdhci_host *host;
int ret;
host = priv->host;
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
SDHCI_QUIRK_BROKEN_R1B |
SDHCI_QUIRK_USE_ACMD12;
#ifdef CONFIG_ZYNQ_HISPD_BROKEN
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
#endif
if (priv->no_1p8)
host->quirks |= SDHCI_QUIRK_NO_1_8_V;
ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
host->mmc = &plat->mmc;
if (ret)
return ret;
host->mmc->priv = host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
#if defined(CONFIG_ARCH_ZYNQMP)
host->set_delay = arasan_sdhci_set_tapdelay;
host->platform_execute_tuning = arasan_sdhci_execute_tuning;
#endif
if (priv->pwrseq) {
debug("Unsupported mmcpwrseq for %s\n", dev->name);
return 0;
}
ret = sdhci_probe(dev);
if (ret)
return ret;
return mmc_init(&plat->mmc);
}
static int sdhci_cdns_probe(struct udevice *dev)
{
DECLARE_GLOBAL_DATA_PTR;
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
struct sdhci_host *host = dev_get_priv(dev);
fdt_addr_t base;
int ret;
base = devfdt_get_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
if (!plat->hrs_addr)
return -ENOMEM;
host->name = dev->name;
host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
host->ops = &sdhci_cdns_ops;
host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
sdhci_cdns_mmc_ops = sdhci_ops;
#ifdef MMC_SUPPORTS_TUNING
sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
#endif
ret = mmc_of_parse(dev, &plat->cfg);
if (ret)
return ret;
ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
if (ret)
return ret;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
if (ret)
return ret;
upriv->mmc = &plat->mmc;
host->mmc = &plat->mmc;
host->mmc->priv = host;
return sdhci_probe(dev);
}
static int xenon_sdhci_probe(struct udevice *dev)
{
struct xenon_sdhci_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct xenon_sdhci_priv *priv = dev_get_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
int ret;
host->mmc = &plat->mmc;
host->mmc->priv = host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
/* Set quirks */
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;
/* Set default timing */
priv->timing = MMC_TIMING_LEGACY;
/* Disable auto clock gating during init */
xenon_mmc_set_acg(host, false);
/* Enable slot */
xenon_mmc_enable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
/*
* Set default power on SoC PHY PAD register (currently only
* available on the Armada 3700)
*/
if (priv->pad_ctrl_reg)
armada_3700_soc_pad_voltage_set(host);
host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;
switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
1)) {
case 8:
host->host_caps |= MMC_MODE_8BIT;
break;
case 4:
host->host_caps |= MMC_MODE_4BIT;
break;
case 1:
break;
default:
printf("Invalid \"bus-width\" value\n");
return -EINVAL;
}
host->ops = &xenon_sdhci_ops;
host->max_clk = XENON_MMC_MAX_CLK;
ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
if (ret)
return ret;
ret = sdhci_probe(dev);
if (ret)
return ret;
/* Enable parallel transfer */
xenon_mmc_enable_parallel_tran(host, XENON_MMC_SLOT_ID_HYPERION);
/* Disable tuning functionality of this slot */
xenon_mmc_disable_tuning(host, XENON_MMC_SLOT_ID_HYPERION);
/* Enable auto clock gating after init */
xenon_mmc_set_acg(host, true);
xenon_mask_cmd_conflict_err(host);
return ret;
}
