int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 cfg = in_le32(&gur->rcwsr[28]); int i; switch (sd) { #ifdef CONFIG_SYS_FSL_SRDS_1 case FSL_SRDS_1: cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; break; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 case FSL_SRDS_2: cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; break; #endif default: printf("invalid SerDes%d\n", sd); break; } /* Is serdes enabled at all? */ if (cfg == 0) return -ENODEV; for (i = 0; i < SRDS_MAX_LANES; i++) { if (serdes_get_prtcl(sd, cfg, i) == device) return i; } return -ENODEV; }
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 cfg; int lane; memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask; cfg >>= sd_prctl_shift; printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); if (!is_serdes_prtcl_valid(sd, cfg)) printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) debug("Unknown SerDes lane protocol %d\n", lane_prtcl); else { serdes_prtcl_map[lane_prtcl] = 1; #ifdef CONFIG_FSL_MC_ENET wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl); #endif } } }
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) { ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u64 serdes_prtcl_map = 0; u32 cfg; int lane; cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; /* Is serdes enabled at all? */ if (!cfg) { printf("SERDES%d is not enabled\n", sd + 1); return 0; } cfg >>= sd_prctl_shift; printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); if (!is_serdes_prtcl_valid(sd, cfg)) printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); serdes_prtcl_map |= (1ULL << lane_prtcl); } return serdes_prtcl_map; }
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u64 serdes_prtcl_map = 0; u32 cfg; int lane; cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; cfg >>= sd_prctl_shift; printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); if (!is_serdes_prtcl_valid(sd, cfg)) printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); serdes_prtcl_map |= (1ULL << lane_prtcl); } /* Set the first bit to indicate serdes has been initialized */ serdes_prtcl_map |= (1ULL << NONE); return serdes_prtcl_map; }
int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 cfg = in_be32(&gur->rcwsr[4]); int i; switch (sd) { case FSL_SRDS_1: cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL; cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; break; case FSL_SRDS_2: cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL; cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; break; #ifdef CONFIG_SYS_FSL_SRDS_3 case FSL_SRDS_3: cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL; cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; break; #endif #ifdef CONFIG_SYS_FSL_SRDS_4 case FSL_SRDS_4: cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL; cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; break; #endif default: printf("invalid SerDes%d\n", sd); break; } /* Is serdes enabled at all? */ if (unlikely(cfg == 0)) return -ENODEV; for (i = 0; i < SRDS_MAX_LANES; i++) { if (serdes_get_prtcl(sd, cfg, i) == device) return i; } return -ENODEV; }
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 cfg; int lane; memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; cfg >>= sd_prctl_shift; printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); if (!is_serdes_prtcl_valid(sd, cfg)) printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) debug("Unknown SerDes lane protocol %d\n", lane_prtcl); else { serdes_prtcl_map[lane_prtcl] = 1; #ifdef CONFIG_FSL_MC_ENET switch (lane_prtcl) { case QSGMII_A: wriop_init_dpmac(sd, 5, (int)lane_prtcl); wriop_init_dpmac(sd, 6, (int)lane_prtcl); wriop_init_dpmac(sd, 7, (int)lane_prtcl); wriop_init_dpmac(sd, 8, (int)lane_prtcl); break; case QSGMII_B: wriop_init_dpmac(sd, 1, (int)lane_prtcl); wriop_init_dpmac(sd, 2, (int)lane_prtcl); wriop_init_dpmac(sd, 3, (int)lane_prtcl); wriop_init_dpmac(sd, 4, (int)lane_prtcl); break; case QSGMII_C: wriop_init_dpmac(sd, 13, (int)lane_prtcl); wriop_init_dpmac(sd, 14, (int)lane_prtcl); wriop_init_dpmac(sd, 15, (int)lane_prtcl); wriop_init_dpmac(sd, 16, (int)lane_prtcl); break; case QSGMII_D: wriop_init_dpmac(sd, 9, (int)lane_prtcl); wriop_init_dpmac(sd, 10, (int)lane_prtcl); wriop_init_dpmac(sd, 11, (int)lane_prtcl); wriop_init_dpmac(sd, 12, (int)lane_prtcl); break; default: if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8) wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], (int)lane_prtcl); if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16) wriop_init_dpmac(sd, sgmii_dpmac[ lane_prtcl], (int)lane_prtcl); break; } #endif } } }