void mtk_uart_init (U32 uartclk, U32 baudrate)
{
//#define AP_PERI_GLOBALCON_RST0 (PERI_CON_BASE+0x0)
#define AP_PERI_GLOBALCON_PDN0 (0x10000084)
/* uartclk != 0, means use custom bus clock; uartclk == 0, means use defaul bus clk */
if(0 == uartclk){ // default bus clk
//uartclk = mtk_get_bus_freq()*1000/4;
uartclk = UART_SRC_CLK;
}
mtk_serial_set_current_uart(CFG_UART_META);
//PDN_Power_CONA_DOWN(PDN_PERI_UART1, 0);
//UART_CLR_BITS(1 << 0, AP_PERI_GLOBALCON_RST0); /* Release UART1 reset signal */
//UART_SET_BITS(1 << 24, AP_PERI_GLOBALCON_PDN0); /* Power on UART1 */
//UART_CLR_BITS(1 << 10, AP_PERI_GLOBALCON_PDN0); /* Power on UART1 */
mtk_uart_power_on(CFG_UART_META);
UART_SET_BITS(UART_FCR_FIFO_INIT, UART_FCR(g_uart)); /* clear fifo */
UART_WRITE16(UART_NONE_PARITY | UART_WLS_8 | UART_1_STOP, UART_LCR(g_uart));
serial_setbrg(uartclk, CFG_META_BAUDRATE);
mtk_serial_set_current_uart(CFG_UART_LOG);
//PDN_Power_CONA_DOWN(PDN_PERI_UART4, 0);
//UART_SET_BITS(1 << 12, APMCU_CG_CLR0);
//UART_CLR_BITS(1 << 3, AP_PERI_GLOBALCON_RST0); /* Release UART2 reset signal */
//UART_SET_BITS(1 << 27, AP_PERI_GLOBALCON_PDN0); /* Power on UART2 */
//UART_CLR_BITS(1 << 11, AP_PERI_GLOBALCON_PDN0); /* Power on UART2 */
mtk_uart_power_on(CFG_UART_LOG);
UART_SET_BITS(UART_FCR_FIFO_INIT, UART_FCR(g_uart)); /* clear fifo */
UART_WRITE16(UART_NONE_PARITY | UART_WLS_8 | UART_1_STOP, UART_LCR(g_uart));
serial_setbrg(uartclk, baudrate);
}
/* Initialize the UART, with...some settings. */
int serial_init(void)
{
xdfuart_writel(CR,0x17); /* RX/TX enabled & reset */
xdfuart_writel(MR,0x20); /* 8 bit, no parity */
serial_setbrg();
return 0;
}
void serial_init(void)
{
volatile u8 *uart_fcr = (volatile u8 *)(UART_BASE + OFF_FCR);
volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
volatile u8 *uart_ier = (volatile u8 *)(UART_BASE + OFF_IER);
volatile u8 *uart_sircr = (volatile u8 *)(UART_BASE + OFF_SIRCR);
/* Disable port interrupts while changing hardware */
*uart_ier = 0;
/* Disable UART unit function */
*uart_fcr = ~UART_FCR_UUE;
/* Set both receiver and transmitter in UART mode (not SIR) */
*uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
*uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
/* Set baud rate */
serial_setbrg();
/* Enable UART unit, enable and clear FIFO */
*uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
static int mxc_serial_init(void)
{
__REG(UART_PHYS + UCR1) = 0x0;
__REG(UART_PHYS + UCR2) = 0x0;
while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
__REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP;
__REG(UART_PHYS + UCR4) = 0x8000;
__REG(UART_PHYS + UESC) = 0x002b;
__REG(UART_PHYS + UTIM) = 0x0;
__REG(UART_PHYS + UTS) = 0x0;
/* keep the DCE DTE setting */
__REG(UART_PHYS + UFCR) = __REG(UART_PHYS + UFCR) & UFCR_DCEDTE;
serial_setbrg();
__REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
__REG(UART_PHYS + UCR1) = UCR1_UARTEN;
return 0;
}
static int jz_serial_init(void)
{
#ifdef CONFIG_BURNER
uart = (struct jz_uart *)(UART0_BASE + gd->arch.gi->uart_idx * 0x1000);
#else
uart = (struct jz_uart *)(UART0_BASE + CONFIG_SYS_UART_INDEX * 0x1000);
#endif
/* Disable port interrupts while changing hardware */
writeb(0, &uart->dlhr_ier);
/* Disable UART unit function */
writeb(~UART_FCR_UUE, &uart->iir_fcr);
/* Set both receiver and transmitter in UART mode (not SIR) */
writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr);
/*
* Set databits, stopbits and parity.
* (8-bit data, 1 stopbit, no parity)
*/
writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr);
/* Set baud rate */
serial_setbrg();
/* Enable UART unit, enable and clear FIFO */
writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS,
&uart->iir_fcr);
return 0;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
/* UART must be enabled before writing to any config registers */
uart->con |= (UART_EN);
#ifdef CONFIG_CONSOLE_UART1
/* infrared disabled */
uart->con |= UART_SIRD;
#endif
/* loopback disabled */
uart->con &= ~(UART_LBE);
/* modem lines and tx/rx polarities */
uart->con &= ~(UART_MXP | UART_TXP | UART_RXP);
/* FIFO enable, N81 */
uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1);
/* set baudrate */
serial_setbrg ();
/* enable rx interrupt */
uart->inten |= UART_RI;
return (0);
}
int serial_init(void)
{
/* Disable port interrupts while changing hardware */
writeb(0, &uart->dlhr_ier);
/* Disable UART unit function */
writeb(~UART_FCR_UUE, &uart->iir_fcr);
/* Set both receiver and transmitter in UART mode (not SIR) */
writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr);
/*
* Set databits, stopbits and parity.
* (8-bit data, 1 stopbit, no parity)
*/
writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr);
/* Set baud rate */
serial_setbrg();
/* Enable UART unit, enable and clear FIFO */
writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS,
&uart->iir_fcr);
return 0;
}
int serial_init( void )
{
unsigned int aunGPIOTxD[] = { 0, 8, 40, 44 };
unsigned int aunGPIORxD[] = { 1, 9, 41, 45 };
cCharsAvailable = 0;
/* configure TxD and RxD pins for their special function */
set_gpio_cfg_reg_val( aunGPIOTxD[ CONSOLE ],
NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_OUTPUT );
set_gpio_cfg_reg_val( aunGPIORxD[ CONSOLE ],
NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_INPUT );
/* configure serial engine */
*get_ser_reg_addr_channel( NS9750_SER_CTRL_A, CONSOLE ) =
NS9750_SER_CTRL_A_CE |
NS9750_SER_CTRL_A_STOP |
NS9750_SER_CTRL_A_WLS_8;
serial_setbrg();
*get_ser_reg_addr_channel( NS9750_SER_CTRL_B, CONSOLE ) =
NS9750_SER_CTRL_B_RCGT;
return 0;
}
int serial_init (void)
{
/* and we have to set CLC register*/
CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
/* initialy we are in async mode */
pAsc->asc_con = ASCCON_M_8ASYNC;
/* select input port */
pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
/* TXFIFO's filling level */
SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
ASCTXFCON_TXFITLOFF, DANUBEASC_TXFIFO_FL);
/* enable TXFIFO */
SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
/* RXFIFO's filling level */
SET_BITFIELD(pAsc->asc_rxfcon, ASCRXFCON_RXFITLMASK,
ASCRXFCON_RXFITLOFF, DANUBEASC_RXFIFO_FL);
/* enable RXFIFO */
SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
/* set baud rate */
serial_setbrg();
/* enable error signals & Receiver enable */
SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_SETREN);
return 0;
}
int serial_init (void)
{
/* make any port initializations specific to this port */
#ifdef CONFIG_DBGU
*AT91C_PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; /* PA 31 & 30 */
*AT91C_PMC_PCER = 1 << AT91C_ID_SYS; /* enable clock */
#endif
#ifdef CONFIG_USART0
*AT91C_PIOA_PDR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0;
*AT91C_PMC_PCER |= 1 << AT91C_ID_USART0; /* enable clock */
#endif
#ifdef CONFIG_USART1
*AT91C_PIOB_PDR = AT91C_PB21_TXD1 | AT91C_PB20_RXD1;
*AT91C_PMC_PCER |= 1 << AT91C_ID_USART1; /* enable clock */
#endif
serial_setbrg ();
us->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX;
us->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
us->US_MR =
(AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS |
AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT);
us->US_IMR = ~0ul;
return (0);
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
void serial_init(bd_t *bd)
{
const char *baudrate;
if ((baudrate = getenv(bd, "baudrate")) != 0)
bd->bi_baudrate = simple_strtoul(baudrate, NULL, 10);
serial_setbrg(bd, bd->bi_baudrate);
}
/**
* on_baudrate() - Update the actual baudrate when the env var changes
*
* This will check for a valid baudrate and only apply it if valid.
*/
static int on_baudrate(const char *name, const char *value, enum env_op op,
int flags)
{
int i;
int baudrate;
switch (op) {
case env_op_create:
case env_op_overwrite:
/*
* Switch to new baudrate if new baudrate is supported
*/
baudrate = simple_strtoul(value, NULL, 10);
/* Not actually changing */
if (gd->baudrate == baudrate)
return 0;
for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
if (baudrate == baudrate_table[i])
break;
}
if (i == ARRAY_SIZE(baudrate_table)) {
if ((flags & H_FORCE) == 0)
printf("## Baudrate %d bps not supported\n",
baudrate);
return 1;
}
if ((flags & H_INTERACTIVE) != 0) {
printf("## Switch baudrate to %d"
" bps and press ENTER ...\n", baudrate);
udelay(50000);
}
gd->baudrate = baudrate;
#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2)
gd->bd->bi_baudrate = baudrate;
#endif
serial_setbrg();
udelay(50000);
if ((flags & H_INTERACTIVE) != 0)
while (1) {
if (getc() == '\r')
break;
}
return 0;
case env_op_delete:
printf("## Baudrate may not be deleted\n");
return 1;
default:
return 0;
}
}
/*
* Function purpose:
* UART initialization
*/
int serial_init(void)
{
/* Switch the Uart's pin from default GPIO into uart function pins for UART0/UART1 */
pGpioReg->CTRL_UR_LPC_SF &= ~(GPIO_UR0_ALL | GPIO_UR1_ALL);
serial_setbrg();
return 0;
}
int serial_init (void)
{
#ifdef CONFIG_INCA_IP
/* we have to set PMU.EN13 bit to enable an ASC device*/
INCAASC_PMU_ENABLE(13);
#endif
/* and we have to set CLC register*/
CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
/* initialy we are in async mode */
pAsc->asc_con = ASCCON_M_8ASYNC;
/* select input port */
pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
#ifdef ASC_FIFO_PRESENT
/* TXFIFO's filling level */
SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
/* enable TXFIFO */
SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
/* RXFIFO's filling level */
SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
/* enable RXFIFO */
SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
#endif
/* enable error signals */
SET_BIT(pAsc->asc_con, ASCCON_FEN);
SET_BIT(pAsc->asc_con, ASCCON_OEN);
#ifdef CONFIG_INCA_IP
/* acknowledge ASC interrupts */
ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
/* disable ASC interrupts */
ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
#endif
#ifdef ASC_FIFO_PRESENT
/* set FIFOs into the transparent mode */
SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
#endif
/* set baud rate */
serial_setbrg();
/* set the options */
serial_setopt();
return 0;
}
static int atmel_serial_init(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
atmel_serial_init_internal(usart);
serial_setbrg();
atmel_serial_activate(usart);
return 0;
}
void
serial_init(ulong cpu_clock, int baudrate)
{
cma_mbio_serial *mbsp = (cma_mbio_serial *)CMA_MB_SERIAL_BASE;
cma_mbio_reg_write(&mbsp->ser_ier, 0x00); /* turn off interrupts */
serial_setbrg(cpu_clock, baudrate);
cma_mbio_reg_write(&mbsp->ser_lcr, 0x03); /* 8 data, 1 stop, no parity */
cma_mbio_reg_write(&mbsp->ser_mcr, 0x03); /* RTS/DTR */
cma_mbio_reg_write(&mbsp->ser_fcr, 0x07); /* Clear & enable FIFOs */
}
/* Symbol for common u-boot code to call. */
int serial_init(void)
{
serial_initialize();
serial_setbrg();
uart_lsr_clear();
#ifdef CONFIG_DEBUG_SERIAL
cache_count = 0;
memset(cached_lsr, 0x00, sizeof(cached_lsr));
memset(cached_rbr, 0x00, sizeof(cached_rbr));
#endif
return 0;
}
int serial_init(void)
{
*SCSCR = (SCR_RE | SCR_TE);
*SCSMR = 0;
*SCSMR = 0;
*SCFCR = (FCR_RFRST | FCR_TFRST);
*SCFCR;
*SCFCR = 0;
serial_setbrg();
return 0;
}
int serial_init(void)
{
writew((SCR_RE | SCR_TE), SCSCR);
writew(0, SCSMR);
writew(0, SCSMR);
writew((FCR_RFRST | FCR_TFRST), SCFCR);
readw(SCFCR);
writew(0, SCFCR);
serial_setbrg();
return 0;
}
int serial_init (void)
{
serial_setgpio();
OUTREG8( (DEBUG_UART_BASE + UART_UIER_OFFSET), 0 );
CLRREG8( (DEBUG_UART_BASE + UART_UFCR_OFFSET), UFCR_UME );
CLRREG8( (DEBUG_UART_BASE + UART_UISR_OFFSET), (UISR_RCVEIR|UISR_XMITIR) );
SETREG8( (DEBUG_UART_BASE + UART_ULCR_OFFSET), (ULCR_WLS_8BITS|ULCR_SBLS_1BIT) );
serial_setbrg();
SETREG8( (DEBUG_UART_BASE + UART_UFCR_OFFSET), (UFCR_FME | UFCR_RFRT | UFCR_TFRT | UFCR_UME | UFCR_RDTR_15) );
return 0;
}
static int sh_serial_init(void)
{
sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
sci_out(&sh_sci, SCSMR, 0);
sci_out(&sh_sci, SCSMR, 0);
sci_out(&sh_sci, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
sci_in(&sh_sci, SCFCR);
sci_out(&sh_sci, SCFCR, 0);
serial_setbrg();
return 0;
}
static int lpc2292_serial_init(void)
{
unsigned long pinsel0;
serial_setbrg ();
pinsel0 = GET32(PINSEL0);
pinsel0 &= ~(0x00000003);
pinsel0 |= 5;
PUT32(PINSEL0, pinsel0);
return (0);
}
int serial_init(void)
{
usart3_writel(CR, USART3_BIT(RSTRX) | USART3_BIT(RSTTX));
serial_setbrg();
usart3_writel(CR, USART3_BIT(RXEN) | USART3_BIT(TXEN));
usart3_writel(MR, (USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
| USART3_BF(PAR, USART3_PAR_NONE)
| USART3_BF(NBSTOP, USART3_NBSTOP_1)));
return 0;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
#if CONFIG_SERIAL1 == 1
uart = (UART *)UART0_BASE;
#elif CONFIG_SERIAL1 == 2
uart = (UART *)UART1_BASE;
#else
#error CONFIG_SERIAL1 not equal to 1 or 2
#endif
serial_setbrg ();
return (0);
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
static int s3c64xx_serial_init(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
/* reset and enable FIFOs, set triggers to the maximum */
uart->UFCON = 0xff;
uart->UMCON = 0;
/* 8N1 */
uart->ULCON = 3;
/* No interrupts, no DMA, pure polling */
uart->UCON = 5;
serial_setbrg();
return 0;
}
static int mpc5xx_serial_init(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
serial_setbrg();
#if defined(CONFIG_5xx_CONS_SCI1)
/* 10-Bit, 1 start bit, 8 data bit, no parity, 1 stop bit */
immr->im_qsmcm.qsmcm_scc1r1 = SCI_M_10;
immr->im_qsmcm.qsmcm_scc1r1 = SCI_TE | SCI_RE;
#else
immr->im_qsmcm.qsmcm_scc2r1 = SCI_M_10;
immr->im_qsmcm.qsmcm_scc2r1 = SCI_TE | SCI_RE;
#endif
return 0;
}
int serial_init(void)
{
uint32_t val;
#ifdef CONFIG_MACH_QCA956x
uart_gpio_init_qca956x();
#else
uart_gpio_init_qca953x();
#endif
serial_setbrg();
ath_uart_wr(OFS_DATA_FORMAT, 0x3);
ath_uart_wr(OFS_INTR_ENABLE, 0);
return 0;
}
int serial_init(void)
{
u32 cr;
/* Disable UART */
REG_WR(DBGUART_BASE + UARTDBGCR, 0);
/* Mask interrupts */
REG_WR(DBGUART_BASE + UARTDBGIMSC, 0);
/* Set default baudrate */
serial_setbrg();
/* Enable UART */
cr = TXE | RXE | UARTEN;
REG_WR(DBGUART_BASE + UARTDBGCR, cr);
return 0;
}
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
int i;
int cf_stat = 0;
/* Check whether CF card is inserted */
*pFIO_EDGE = FIO_EDGE_CF_BITS;
*pFIO_POLAR = FIO_POLAR_CF_BITS;
for (i = 0; i < 0x300; i++)
asm("nop;");
if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
cf_stat = 0;
} else {
cf_stat = 1;
}
*pFIO_EDGE = FIO_EDGE_BITS;
*pFIO_POLAR = FIO_POLAR_BITS;
if (cf_stat) {
printf("Booting from COMPACT flash\n");
for (i = 0; i < 0x1000; i++)
asm("nop;");
for (i = 0; i < 0x1000; i++)
asm("nop;");
for (i = 0; i < 0x1000; i++)
asm("nop;");
serial_setbrg();
ide_init();
setenv("bootargs", "");
setenv("bootcmd",
"fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
} else {
printf("Booting from FLASH\n");
}
return 0;
}
int serial_init(void)
{
u32 uart_cs;
#if (SOC_TYPE & QCA_AR933X_SOC)
/*
* Set GPIO10 (UART_SO) as output and enable UART,
* BIT(15) in GPIO_FUNCTION_1 register must be written with 1
*/
qca_soc_reg_read_set(QCA_GPIO_OE_REG, GPIO10);
qca_soc_reg_read_set(QCA_GPIO_FUNC_1_REG,
QCA_GPIO_FUNC_1_UART_EN_MASK | BIT(15));
#else
#error "Missing GPIO configuration for HS UART"
#endif
/*
* High-Speed UART controller configuration:
* - no DMA
* - no interrupt
* - no parity
* - DCE mode
* - no flow control
* - set RX ready oride
* - set TX ready oride
*/
uart_cs = (0 << QCA_HSUART_CS_DMA_EN_SHIFT) |
(0 << QCA_HSUART_CS_HOST_INT_EN_SHIFT) |
(1 << QCA_HSUART_CS_RX_READY_ORIDE_SHIFT) |
(1 << QCA_HSUART_CS_TX_READY_ORIDE_SHIFT) |
(QCA_HSUART_CS_PAR_MODE_NO_VAL << QCA_HSUART_CS_PAR_MODE_SHIFT) |
(QCA_HSUART_CS_IFACE_MODE_DCE_VAL << QCA_HSUART_CS_IFACE_MODE_SHIFT) |
(QCA_HSUART_CS_FLOW_MODE_NO_VAL << QCA_HSUART_CS_FLOW_MODE_SHIFT);
qca_soc_reg_write(QCA_HSUART_CS_REG, uart_cs);
serial_setbrg();
return 0;
}
