Exemplo n.º 1
0
void NES_mapper230::MemoryWrite(uint32 addr, uint8 data)
{
  if(rom_switch)
  {
    set_CPU_bank4((data & 0x07)*2+0);
    set_CPU_bank5((data & 0x07)*2+1);
  }
  else
  {
    if(data & 0x40)
    {
      set_mirroring(NES_PPU::MIRROR_VERT);
    }
    else
    {
      set_mirroring(NES_PPU::MIRROR_HORIZ);
    }
    if(data & 0x20)
    {
      set_CPU_bank4((data & 0x1F)*2+16);
      set_CPU_bank5((data & 0x1F)*2+17);
      set_CPU_bank6((data & 0x1F)*2+16);
      set_CPU_bank7((data & 0x1F)*2+17);
    }
    else
    {
      set_CPU_bank4((data & 0x1E)*2+16);
      set_CPU_bank5((data & 0x1E)*2+17);
      set_CPU_bank6((data & 0x1E)*2+18);
      set_CPU_bank7((data & 0x1E)*2+19);
    }
  }
}
Exemplo n.º 2
0
// Coded by rinao
void NES_mapper188::MemoryWrite(uint32 addr, uint8 data)
{
  if (data)
  {
    if (data & 0x10)
    {
      data &= 0x07;
      set_CPU_bank4(data*2);
      set_CPU_bank5(data*2+1);
    }
    else
    {
      set_CPU_bank4(data*2+16);
      set_CPU_bank5(data*2+17);
    }
  }
  else
  {
    if (num_8k_ROM_banks == 0x10)
    {
      set_CPU_bank4(14);
      set_CPU_bank5(15);
    }
    else
    {
      set_CPU_bank4(16);
      set_CPU_bank5(17);
    }
  }
  //data &= num_8k_ROM_banks-1;
  //set_CPU_banks(data*2,(data*2)+1,num_8k_ROM_banks-2,num_8k_ROM_banks-1);
}
Exemplo n.º 3
0
void NES_mapper94::MemoryWrite(uint32 addr, uint8 data)
{
  if((addr & 0xFFF0) == 0xFF00)
  {
    uint8 bank = (data & 0x1C) >> 2;
    set_CPU_bank4(bank*2+0);
    set_CPU_bank5(bank*2+1);
  }
Exemplo n.º 4
0
void NES_mapper91::MemoryWriteSaveRAM(uint32 addr, uint8 data)
{
  switch(addr & 0xF00F)
  {
    case 0x6000:
      {
        set_PPU_bank0(data*2+0);
        set_PPU_bank1(data*2+1);
      }
      break;

    case 0x6001:
      {
        set_PPU_bank2(data*2+0);
        set_PPU_bank3(data*2+1);
      }
      break;

    case 0x6002:
      {
        set_PPU_bank4(data*2+0);
        set_PPU_bank5(data*2+1);
      }
      break;

    case 0x6003:
      {
        set_PPU_bank6(data*2+0);
        set_PPU_bank7(data*2+1);
      }
      break;

    case 0x7000:
      {
        set_CPU_bank4(data);
      }
      break;

    case 0x7001:
      {
        set_CPU_bank5(data);
      }
      break;

    case 0x7002:
      {
        irq_counter = data;
      }
      break;

    case 0x7003:
      {
        irq_enabled = data;
      }
      break;
   }
}
Exemplo n.º 5
0
/////////////////////////////////////////////////////////////////////
// Mapper 91
void NES_mapper91::Reset()
{
  // set CPU bank pointers
  set_CPU_bank4(num_8k_ROM_banks-2);
  set_CPU_bank5(num_8k_ROM_banks-1);
  set_CPU_bank6(num_8k_ROM_banks-2);
  set_CPU_bank7(num_8k_ROM_banks-1);

  // set PPU bank pointers
  if(num_1k_VROM_banks)
  {
    set_PPU_banks(0,0,0,0,0,0,0,0);
  }
}
Exemplo n.º 6
0
void NES_mapper66::MemoryWrite(uint32 addr, uint8 data)
{
  uint8 chr_bank = data & 0x0F;
  uint8 prg_bank = (data & 0xF0) >> 4;

  set_CPU_bank4(prg_bank*4+0);
  set_CPU_bank5(prg_bank*4+1);
  set_CPU_bank6(prg_bank*4+2);
  set_CPU_bank7(prg_bank*4+3);

  set_PPU_bank0(chr_bank*8+0);
  set_PPU_bank1(chr_bank*8+1);
  set_PPU_bank2(chr_bank*8+2);
  set_PPU_bank3(chr_bank*8+3);
  set_PPU_bank4(chr_bank*8+4);
  set_PPU_bank5(chr_bank*8+5);
  set_PPU_bank6(chr_bank*8+6);
  set_PPU_bank7(chr_bank*8+7);
}
Exemplo n.º 7
0
void NES_mapper86::MemoryWriteSaveRAM(uint32 addr, uint8 data)
{
  if(addr == 0x6000)
  {
    uint8 chr_bank = data & 0x03 | (data & 0x40) >> 4;
    uint8 prg_bank = (data & 0x30) >> 4;

    set_CPU_bank4(prg_bank*4+0);
    set_CPU_bank5(prg_bank*4+1);
    set_CPU_bank6(prg_bank*4+2);
    set_CPU_bank7(prg_bank*4+3);

    set_PPU_bank0(chr_bank*8+0);
    set_PPU_bank1(chr_bank*8+1);
    set_PPU_bank2(chr_bank*8+2);
    set_PPU_bank3(chr_bank*8+3);
    set_PPU_bank4(chr_bank*8+4);
    set_PPU_bank5(chr_bank*8+5);
    set_PPU_bank6(chr_bank*8+6);
    set_PPU_bank7(chr_bank*8+7);
  }
Exemplo n.º 8
0
/////////////////////////////////////////////////////////////////////
// Mapper 64
void NES_mapper64::Reset()
{
    // set CPU bank pointers
    set_CPU_bank4(num_8k_ROM_banks-1);
    set_CPU_bank5(num_8k_ROM_banks-1);
    set_CPU_bank6(num_8k_ROM_banks-1);
    set_CPU_bank7(num_8k_ROM_banks-1);

    // set PPU bank pointers
    if(num_1k_VROM_banks)
    {
        set_PPU_banks(0,1,2,3,4,5,6,7);
    }

    irq_latch = 0;
    irq_counter = 0;
    irq_enabled = 0;

    regs[0] = 0;
    regs[1] = 0;
    regs[2] = 0;
}
Exemplo n.º 9
0
void NES_mapper17::MemoryWriteLow(uint32 addr, uint8 data)
{
  switch(addr)
  {
    case 0x42FE:
      {
        if((data & 0x10) == 0)
        {
          set_mirroring(0,0,0,0);
        }
        else
        {
          set_mirroring(1,1,1,1);
        }
      }
      break;

    case 0x42FF:
      {
        if((data & 0x10) == 0)
        {
          set_mirroring(NES_PPU::MIRROR_VERT);
        }
        else
        {
          set_mirroring(NES_PPU::MIRROR_HORIZ);
        }
      }
      break;

    case 0x4501:
      {
        irq_enabled = 0;
      }
      break;

    case 0x4502:
      {
        irq_latch = (irq_latch & 0xFF00) | data;
      }
      break;

    case 0x4503:
      {
        irq_latch = (irq_latch & 0x00FF) | ((uint32)data << 8);
        irq_counter = irq_latch;
        irq_enabled = 1;
      }
      break;

    case 0x4504:
      {
        set_CPU_bank4(data);
      }
      break;

    case 0x4505:
      {
        set_CPU_bank5(data);
      }
      break;

    case 0x4506:
      {
        set_CPU_bank6(data);
      }
      break;

    case 0x4507:
      {
        set_CPU_bank7(data);
      }
      break;

    case 0x4510:
      {
        set_PPU_bank0(data);
      }
      break;

    case 0x4511:
      {
        set_PPU_bank1(data);
      }
      break;

    case 0x4512:
      {
        set_PPU_bank2(data);
      }
      break;

    case 0x4513:
      {
        set_PPU_bank3(data);
      }
      break;

    case 0x4514:
      {
        set_PPU_bank4(data);
      }
      break;

    case 0x4515:
      {
        set_PPU_bank5(data);
      }
      break;

    case 0x4516:
      {
        set_PPU_bank6(data);
      }
      break;

    case 0x4517:
      {
        set_PPU_bank7(data);
      }
      break;
  }
}
Exemplo n.º 10
0
void NES_mapper24::MemoryWrite(uint32 addr, uint8 data)
{
  switch(addr & 0xF003)
  {
    case 0x8000:
      {
        set_CPU_bank4(data*2+0);
        set_CPU_bank5(data*2+1);
      }
      break;

    //DCR
    case 0x9000:
    case 0x9001:
    case 0x9002:
    case 0xA000:
    case 0xA001:
    case 0xA002:
    case 0xB000:
    case 0xB001:
    case 0xB002:
      parent_NES->apu->Write(addr, data);
      break;

    case 0xB003:
      {
        data = data & 0x0C;
        if(data == 0x00)
        {
          set_mirroring(NES_PPU::MIRROR_VERT);
        }
        else if(data == 0x04)
        {
          set_mirroring(NES_PPU::MIRROR_HORIZ);
        }
        else if(data == 0x08)
        {
          set_mirroring(0,0,0,0);
        }
        else if(data == 0x0C)
        {
          set_mirroring(1,1,1,1);
        }
      }
      break;

    case 0xC000:
      {
        set_CPU_bank6(data);
      }
      break;

    case 0xD000:
      {
        set_PPU_bank0(data);
      }
      break;

    case 0xD001:
      {
        set_PPU_bank1(data);
      }
      break;

    case 0xD002:
      {
        set_PPU_bank2(data);
      }
      break;

    case 0xD003:
      {
        set_PPU_bank3(data);
      }
      break;

    case 0xE000:
      {
        set_PPU_bank4(data);
      }
      break;

    case 0xE001:
      {
        set_PPU_bank5(data);
      }
      break;

    case 0xE002:
      {
        set_PPU_bank6(data);
      }
      break;

    case 0xE003:
      {
        set_PPU_bank7(data);
      }
      break;

    case 0xF000:
      {
        irq_latch = data;
      }
      break;

    case 0xF001:
      {
        irq_enabled = data & 0x03;
        if(irq_enabled & 0x02)
        {
          irq_counter = irq_latch;
        }
      }
      break;

    case 0xF002:
      {
        if(irq_enabled & 0x01)
        {
          irq_enabled |= 0x02;
        }
        else
        {
          irq_enabled &= 0x01;
        }
      }
      break;
  }
}
Exemplo n.º 11
0
void NES_mapper69::MemoryWrite(uint32 addr, uint8 data)
{
  switch(addr & 0xE000)
  {
    case 0x8000:
      {
        regs[0] = data;
      }
      break;

    case 0xA000:
      {
        switch(regs[0] & 0x0F)
        {
          case 0x00:
            {
              set_PPU_bank0(data);
            }
            break;

          case 0x01:
            {
              set_PPU_bank1(data);
            }
            break;

          case 0x02:
            {
              set_PPU_bank2(data);
            }
            break;

          case 0x03:
            {
              set_PPU_bank3(data);
            }
            break;

          case 0x04:
            {
              set_PPU_bank4(data);
            }
            break;

          case 0x05:
            {
              set_PPU_bank5(data);
            }
            break;

          case 0x06:
            {
              set_PPU_bank6(data);
            }
            break;

          case 0x07:
            {
              set_PPU_bank7(data);
            }
            break;

          case 0x08:
            {
              if(!patch)
              {
                if(!(data & 0x40))
                {
                  set_CPU_bank3(data);
                }
              }
            }
            break;

          case 0x09:
            {
              set_CPU_bank4(data);
            }
            break;

          case 0x0A:
            {
              set_CPU_bank5(data);
            }
            break;

          case 0x0B:
            {
              set_CPU_bank6(data);
            }
            break;

          case 0x0C:
            {
              data &= 0x03;
              if(data == 0)
              {
                set_mirroring(NES_PPU::MIRROR_VERT);
              }
              else if(data == 1)
              {
                set_mirroring(NES_PPU::MIRROR_HORIZ);
              }
              else if(data == 2)
              {
                set_mirroring(0,0,0,0);
              }
              else
              {
                set_mirroring(1,1,1,1);
              }
            }
            break;

          case 0x0D:
            {
              irq_enabled = data;
            }
            break;

          case 0x0E:
            {
              irq_counter = (irq_counter & 0xFF00) | data;
            }
            break;

          case 0x0F:
            {
              irq_counter = (irq_counter & 0x00FF) | (data << 8);
            }
            break;
        }
      }
      break;

    case 0xC000:
    case 0xE000:
      {
        parent_NES->apu->ExWrite(addr, data);
      }
      break;
  }
}
Exemplo n.º 12
0
void NES_mapper16::MemoryWrite3(uint32 addr, uint8 data)
{
  switch(addr)
  {
    case 0x8000:
    case 0x8001:
    case 0x8002:
    case 0x8003:
      {
        regs[0] = data & 0x01;
        set_CPU_bank4(regs[0]*0x20+regs[2]*2+0);
        set_CPU_bank5(regs[0]*0x20+regs[2]*2+1);
      }
      break;

    case 0x8004:
    case 0x8005:
    case 0x8006:
    case 0x8007:
      {
        regs[1] = data & 0x01;
        set_CPU_bank6(regs[1]*0x20+0x1E);
        set_CPU_bank7(regs[1]*0x20+0x1F);
      }
      break;

    case 0x8008:
      {
        regs[2] = data;
        set_CPU_bank4(regs[0]*0x20+regs[2]*2+0);
        set_CPU_bank5(regs[0]*0x20+regs[2]*2+1);
        set_CPU_bank6(regs[1]*0x20+0x1E);
        set_CPU_bank7(regs[1]*0x20+0x1F);
      }
      break;

    case 0x8009:
      {
        data &= 0x03;
        if(data == 0)
        {
          set_mirroring(NES_PPU::MIRROR_VERT);
        }
        else if(data == 1)
        {
          set_mirroring(NES_PPU::MIRROR_HORIZ);
        }
        else if(data == 2)
        {
          set_mirroring(0,0,0,0);
        }
        else
        {
          set_mirroring(1,1,1,1);
        }
      }
      break;

    case 0x800A:
      {
        irq_enabled = data & 0x01;
        irq_counter = irq_latch;
      }
      break;

    case 0x800B:
      {
        irq_latch = (irq_latch & 0xFF00) | data;
      }
      break;

    case 0x800C:
      {
         irq_latch = ((uint32)data << 8) | (irq_latch & 0x00FF);
      }
      break;

    case 0x800D:
      {
        //write protect
      }
      break;
  }
}
Exemplo n.º 13
0
void NES_mapper16::MemoryWrite2(uint32 addr, uint8 data)
{
  switch(addr & 0x000F)
  {
    case 0x0000:
      {
        set_PPU_bank0(data);
      }
      break;

    case 0x0001:
      {
        set_PPU_bank1(data);
      }
      break;

    case 0x0002:
      {
        set_PPU_bank2(data);
      }
      break;

    case 0x0003:
      {
        set_PPU_bank3(data);
      }
      break;

    case 0x0004:
      {
        set_PPU_bank4(data);
      }
      break;

    case 0x0005:
      {
        set_PPU_bank5(data);
      }
      break;

    case 0x0006:
      {
        set_PPU_bank6(data);
      }
      break;

    case 0x0007:
      {
        set_PPU_bank7(data);
      }
      break;

    case 0x0008:
      {
        set_CPU_bank4(data*2+0);
        set_CPU_bank5(data*2+1);
      }
      break;

    case 0x0009:
      {
        data &= 0x03;
        if(data == 0)
        {
          set_mirroring(NES_PPU::MIRROR_VERT);
        }
        else if(data == 1)
        {
          set_mirroring(NES_PPU::MIRROR_HORIZ);
        }
        else if(data == 2)
        {
          set_mirroring(0,0,0,0);
        }
        else
        {
          set_mirroring(1,1,1,1);
        }
      }
      break;

    case 0x000A:
      {
        irq_enabled = data & 0x01;
        irq_counter = irq_latch;
      }
      break;

    case 0x000B:
      {
        irq_latch = (irq_latch & 0xFF00) | data;
      }
      break;

    case 0x000C:
      {
         irq_latch = ((uint32)data << 8) | (irq_latch & 0x00FF);
      }
      break;

    case 0x000D:
      {
        if(data == 0x80)
        {
          // reset
          eeprom_addr = 0x00;
          eeprom_mode = 0x00;
          eeprom_wbit = 0x00;
          eeprom_rbit = 0x00;
        }
        else if(eeprom_cmd[3] == 0x00 && eeprom_cmd[2] == 0x20 &&
                eeprom_cmd[1] == 0x60 && eeprom_cmd[0] == 0x40 && data == 0x00)
        {
          // reset ?
        }
        else if(eeprom_cmd[3] == 0x00 && eeprom_cmd[2] == 0x40 &&
                eeprom_cmd[1] == 0x60 && eeprom_cmd[0] == 0x20 && data == 0x00)
        {
          // start
          eeprom_wbit = 0x01;
          eeprom_rbit = 0x01;
          eeprom_data = 0;
          eeprom_mode = 0;
        }
        else if (eeprom_cmd[0] == 0x60 && data == 0xE0)
        {
          if(!eeprom_mode)
          {
            // sync
            eeprom_wbit = 0x01;
            eeprom_rbit = 0x01;
            eeprom_data = 0;
            eeprom_mode = 1;
            eeprom_status = 0x00;
            //memset(serial_out, eeprom_status | barcode_status, 0x2000);
            serial_out[0] = eeprom_status | barcode_status;
          }
          else
          {
            // read
            eeprom_data = parent_NES->ReadSaveRAM(eeprom_addr);
            if(eeprom_data & eeprom_rbit)
            {
              eeprom_status = 0x10;
              //memset(serial_out, eeprom_status | barcode_status, 0x2000);
              serial_out[0] = eeprom_status | barcode_status;
            }
            else
            {
              eeprom_status = 0x00;
              //memset(serial_out, eeprom_status | barcode_status, 0x2000);
              serial_out[0] = eeprom_status | barcode_status;
            }
            eeprom_rbit <<= 1;
            eeprom_wbit = 0x00;
          }
        }
        else if(eeprom_cmd[1] == 0x00 && eeprom_cmd[0] == 0x20 && data == 0x00)
        {
          // write 0
          eeprom_data &= 0xFF - eeprom_wbit;
          if(eeprom_wbit == 0x80)
          {
            if(eeprom_mode)
            {
              parent_NES->WriteSaveRAM(eeprom_addr, eeprom_data);
            }
            else
            {
              eeprom_addr = eeprom_data & 0x7F;
            }
            eeprom_wbit = 0x00;
          }
          else
          {
            eeprom_wbit <<= 1;
          }
          eeprom_rbit = 0x00;
        }
        else if(eeprom_cmd[3] == 0x00 && eeprom_cmd[2] == 0x40 &&
                eeprom_cmd[1] == 0x60 && eeprom_cmd[0] == 0x40 && data == 0x00)
        {
          // write 1
          eeprom_data |= eeprom_wbit;
          if(eeprom_wbit == 0x80)
          {
            if(eeprom_mode)
            {
              parent_NES->WriteSaveRAM(eeprom_addr, eeprom_data);
            }
            else
            {
              eeprom_addr = eeprom_data & 0x7F;
            }
            eeprom_wbit = 0x00;
          }
          else
          {
            eeprom_wbit <<= 1;
          }
          eeprom_rbit = 0x00;
        }
        eeprom_cmd[3] = eeprom_cmd[2];
        eeprom_cmd[2] = eeprom_cmd[1];
        eeprom_cmd[1] = eeprom_cmd[0];
        eeprom_cmd[0] = data;
      }
      break;
  }
}
Exemplo n.º 14
0
void NES_mapper21::MemoryWrite(uint32 addr, uint8 data)
{
    // regs[0] ... 1K VROM bank at PPU $0000
    // regs[1] ... 1K VROM bank at PPU $0400
    // regs[2] ... 1K VROM bank at PPU $0800
    // regs[3] ... 1K VROM bank at PPU $0C00
    // regs[4] ... 1K VROM bank at PPU $1000
    // regs[5] ... 1K VROM bank at PPU $1400
    // regs[6] ... 1K VROM bank at PPU $1800
    // regs[7] ... 1K VROM bank at PPU $1C00
    // regs[8] ... $8000 Switching Mode

    switch (addr & 0xF0CF)
    {
    case 0x8000:
    {
        if(regs[8] & 0x02)
        {
            set_CPU_bank6(data);
        }
        else
        {
            set_CPU_bank4(data);
        }
    }
    break;

    case 0xA000:
    {
        set_CPU_bank5(data);
    }
    break;

    case 0x9000:
    {
        data &= 0x03;
        if(data == 0)
        {
            set_mirroring(NES_PPU::MIRROR_VERT);
        }
        else if(data == 1)
        {
            set_mirroring(NES_PPU::MIRROR_HORIZ);
        }
        else if(data == 2)
        {
            set_mirroring(0,0,0,0);
        }
        else
        {
            set_mirroring(1,1,1,1);
        }
    }
    break;

    case 0x9002:
    case 0x9080:
    {
        regs[8] = data;
    }
    break;

    case 0xB000:
    {
        regs[0] = (regs[0] & 0xF0) | (data & 0x0F);
        set_PPU_bank0(regs[0]);
    }
    break;

    case 0xB002:
    case 0xB040:
    {
        regs[0] = (regs[0] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank0(regs[0]);
    }
    break;

    case 0xB001:
    case 0xB004:
    case 0xB080:
    {
        regs[1] = (regs[1] & 0xF0) | (data & 0x0F);
        set_PPU_bank1(regs[1]);
    }
    break;

    case 0xB003:
    case 0xB006:
    case 0xB0C0:
    {
        regs[1] = (regs[1] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank1(regs[1]);
    }
    break;

    case 0xC000:
    {
        regs[2] = (regs[2] & 0xF0) | (data & 0x0F);
        set_PPU_bank2(regs[2]);
    }
    break;

    case 0xC002:
    case 0xC040:
    {
        regs[2] = (regs[2] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank2(regs[2]);
    }
    break;

    case 0xC001:
    case 0xC004:
    case 0xC080:
    {
        regs[3] = (regs[3] & 0xF0) | (data & 0x0F);
        set_PPU_bank3(regs[3]);
    }
    break;

    case 0xC003:
    case 0xC006:
    case 0xC0C0:
    {
        regs[3] = (regs[3] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank3(regs[3]);
    }
    break;

    case 0xD000:
    {
        regs[4] = (regs[4] & 0xF0) | (data & 0x0F);
        set_PPU_bank4(regs[4]);
    }
    break;

    case 0xD002:
    case 0xD040:
    {
        regs[4] = (regs[4] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank4(regs[4]);
    }
    break;

    case 0xD001:
    case 0xD004:
    case 0xD080:
    {
        regs[5] = (regs[5] & 0xF0) | (data & 0x0F);
        set_PPU_bank5(regs[5]);
    }
    break;

    case 0xD003:
    case 0xD006:
    case 0xD0C0:
    {
        regs[5] = (regs[5] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank5(regs[5]);
    }
    break;

    case 0xE000:
    {
        regs[6] = (regs[6] & 0xF0) | (data & 0x0F);
        set_PPU_bank6(regs[6]);
    }
    break;

    case 0xE002:
    case 0xE040:
    {
        regs[6] = (regs[6] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank6(regs[6]);
    }
    break;

    case 0xE001:
    case 0xE004:
    case 0xE080:
    {
        regs[7] = (regs[7] & 0xF0) | (data & 0x0F);
        set_PPU_bank7(regs[7]);
    }
    break;

    case 0xE003:
    case 0xE006:
    case 0xE0C0:
    {
        regs[7] = (regs[7] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank7(regs[7]);
    }
    break;

    case 0xF000:
    {
        irq_latch = (irq_latch & 0xF0) | (data & 0x0F);
    }
    break;

    case 0xF002:
    case 0xF040:
    {
        irq_latch = (irq_latch & 0x0F) | ((data & 0x0F) << 4);
    }
    break;

    case 0xF003:
    case 0xF0C0:
    {
        irq_enabled = (irq_enabled & 0x01) * 3;
    }
    break;

    case 0xF004:
    case 0xF080:
    {
        irq_enabled = data & 0x03;
        if(irq_enabled & 0x02)
        {
            irq_counter = irq_latch;
        }
    }
    break;
    }
}
Exemplo n.º 15
0
void NES_mapper64::MemoryWrite(uint32 addr, uint8 data)
{
    switch(addr & 0xF003)
    {
    case 0x8000:
    {
        regs[0] = data & 0x0F;
        regs[1] = data & 0x40;
        regs[2] = data & 0x80;
    }
    break;

    case 0x8001:
    {
        switch(regs[0])
        {
        case 0x00:
        {
            if(regs[2])
            {
                set_PPU_bank4(data+0);
                set_PPU_bank5(data+1);
            }
            else
            {
                set_PPU_bank0(data+0);
                set_PPU_bank1(data+1);
            }
        }
        break;

        case 0x01:
        {
            if(regs[2])
            {
                set_PPU_bank6(data+0);
                set_PPU_bank7(data+1);
            }
            else
            {
                set_PPU_bank2(data+0);
                set_PPU_bank3(data+1);
            }
        }
        break;

        case 0x02:
        {
            if(regs[2])
            {
                set_PPU_bank0(data);
            }
            else
            {
                set_PPU_bank4(data);
            }
        }
        break;

        case 0x03:
        {
            if(regs[2])
            {
                set_PPU_bank1(data);
            }
            else
            {
                set_PPU_bank5(data);
            }
        }
        break;

        case 0x04:
        {
            if(regs[2])
            {
                set_PPU_bank2(data);
            }
            else
            {
                set_PPU_bank6(data);
            }
        }
        break;

        case 0x05:
        {
            if(regs[2])
            {
                set_PPU_bank3(data);
            }
            else
            {
                set_PPU_bank7(data);
            }
        }
        break;

        case 0x06:
        {
            if(regs[1])
            {
                set_CPU_bank5(data);
            }
            else
            {
                set_CPU_bank4(data);
            }
        }
        break;

        case 0x07:
        {
            if(regs[1])
            {
                set_CPU_bank6(data);
            }
            else
            {
                set_CPU_bank5(data);
            }
        }
        break;

        case 0x08:
        {
            //if(regs[2])
            //{
            //  set_PPU_bank5(data);
            //}
            //else
            {
                set_PPU_bank1(data);
            }
        }
        break;

        case 0x09:
        {
            //if(regs[2])
            //{
            //  set_PPU_bank7(data);
            //}
            //else
            {
                set_PPU_bank3(data);
            }
        }
        break;

        case 0x0F:
        {
            if(regs[1])
            {
                set_CPU_bank4(data);
            }
            else
            {
                set_CPU_bank6(data);
            }
        }
        break;
        }
    }
    break;

    case 0xA000:
    {
        if(!(data & 0x01))
        {
            set_mirroring(NES_PPU::MIRROR_VERT);
        }
        else
        {
            set_mirroring(NES_PPU::MIRROR_HORIZ);
        }
    }
    break;

    case 0xC000:
    {
        irq_latch = data;
        irq_counter = irq_latch;
    }
    break;

    case 0xC001:
    {
        irq_counter = irq_latch;
    }
    break;

    case 0xE000:
    {
        irq_enabled = 0;
        irq_counter = irq_latch;
    }
    break;

    case 0xE001:
    {
        irq_enabled = 1;
        irq_counter = irq_latch;
    }
    break;
    }
}
Exemplo n.º 16
0
void NES_mapper237::MemoryWrite(uint32 addr, uint8 data)
{
    if(addr & 0x4000)
    {
        if((addr & 0x0030) == 0x00)
        {
            set_CPU_bank4((addr&0x07)*2+0);
            set_CPU_bank5((addr&0x07)*2+1);
            set_CPU_bank6(num_8k_ROM_banks-2);
            set_CPU_bank7(num_8k_ROM_banks-1);
        }
        else if((addr & 0x0030) == 0x10)
        {
            for(uint32 i = 0; i < 0x2000; i++)
            {
                wram[i+0x0000] = ROM_banks[((addr&0x07)*2+0)*0x2000+(i&0x1ff0)+0x0d]; // 0x0b?
                wram[i+0x2000] = ROM_banks[((addr&0x07)*2+1)*0x2000+(i&0x1ff0)+0x0d]; // 0x0b?
                wram[i+0x4000] = ROM_banks[(num_8k_ROM_banks-2)*0x2000+(i&0x1ff0)+0x0d]; // 0x0b?
                wram[i+0x6000] = ROM_banks[(num_8k_ROM_banks-1)*0x2000+(i&0x1ff0)+0x0d]; // 0x0b?
            }
            nes6502_context *context;
            context = nes6502_get_current_context ();

            context->mem_page[4] = wram + 0x0000;
            context->mem_page[5] = wram + 0x2000;
            context->mem_page[6] = wram + 0x4000;
            context->mem_page[7] = wram + 0x6000;

            nes6502_setcontext();
        }
        else if((addr & 0x0030) == 0x20)
        {
            set_CPU_bank4((addr&0x06)*2+0);
            set_CPU_bank5((addr&0x06)*2+1);
            set_CPU_bank6((addr&0x06)*2+2);
            set_CPU_bank7((addr&0x06)*2+3);
        }
        else if((addr & 0x0030) == 0x30)
        {
            set_CPU_bank4((addr&0x07)*2+0);
            set_CPU_bank5((addr&0x07)*2+1);
            set_CPU_bank6((addr&0x07)*2+0);
            set_CPU_bank7((addr&0x07)*2+1);
        }
    }
    else
    {
        if(addr & 0x0020)
        {
            set_mirroring(NES_PPU::MIRROR_VERT);
        }
        else
        {
            set_mirroring(NES_PPU::MIRROR_HORIZ);
        }
        set_PPU_bank0((addr&0x07)*8+0);
        set_PPU_bank1((addr&0x07)*8+1);
        set_PPU_bank2((addr&0x07)*8+2);
        set_PPU_bank3((addr&0x07)*8+3);
        set_PPU_bank4((addr&0x07)*8+4);
        set_PPU_bank5((addr&0x07)*8+5);
        set_PPU_bank6((addr&0x07)*8+6);
        set_PPU_bank7((addr&0x07)*8+7);
    }
}
Exemplo n.º 17
0
void NES_mapper65::MemoryWrite(uint32 addr, uint8 data)
{
    switch(addr)
    {
    case 0x8000:
    {
        set_CPU_bank4(data);
    }
    break;

    case 0x9000:
    {
        if(!patch)
        {
            if(data & 0x40)
            {
                set_mirroring(NES_PPU::MIRROR_VERT);
            }
            else
            {
                set_mirroring(NES_PPU::MIRROR_HORIZ);
            }
        }
    }
    break;

    case 0x9001:
    {
        if(patch)
        {
            if(data & 0x80)
            {
                set_mirroring(NES_PPU::MIRROR_HORIZ);
            }
            else
            {
                set_mirroring(NES_PPU::MIRROR_VERT);
            }
        }
    }
    break;

    case 0x9003:
    {
        if(!patch)
        {
            irq_enabled = data & 0x80;
        }
    }
    break;

    case 0x9004:
    {
        if(!patch)
        {
            irq_counter = irq_latch;
        }
    }
    break;

    case 0x9005:
    {
        if(patch)
        {
            irq_counter = (uint8)(data << 1);
            irq_enabled = data;
        }
        else
        {
            irq_latch = (irq_latch & 0x00FF) | ((uint32)data << 8);
        }
    }
    break;

    case 0x9006:
    {
        if(patch)
        {
            irq_enabled = 1;
        }
        else
        {
            irq_latch = (irq_latch & 0xFF00) | data;
        }
    }
    break;

    case 0xB000:
    {
        set_PPU_bank0(data);
    }
    break;

    case 0xB001:
    {
        set_PPU_bank1(data);
    }
    break;

    case 0xB002:
    {
        set_PPU_bank2(data);
    }
    break;

    case 0xB003:
    {
        set_PPU_bank3(data);
    }
    break;

    case 0xB004:
    {
        set_PPU_bank4(data);
    }
    break;

    case 0xB005:
    {
        set_PPU_bank5(data);
    }
    break;

    case 0xB006:
    {
        set_PPU_bank6(data);
    }
    break;

    case 0xB007:
    {
        set_PPU_bank7(data);
    }
    break;

    case 0xA000:
    {
        set_CPU_bank5(data);
    }
    break;

    case 0xC000:
    {
        set_CPU_bank6(data);
    }
    break;
    }
}
Exemplo n.º 18
0
void NES_mapper25::MemoryWrite(uint32 addr, uint8 data)
{
  // regs[0] ... 1K VROM bank at PPU $0000
  // regs[1] ... 1K VROM bank at PPU $0400
  // regs[2] ... 1K VROM bank at PPU $0800
  // regs[3] ... 1K VROM bank at PPU $0C00
  // regs[4] ... 1K VROM bank at PPU $1000
  // regs[5] ... 1K VROM bank at PPU $1400
  // regs[6] ... 1K VROM bank at PPU $1800
  // regs[7] ... 1K VROM bank at PPU $1C00
  // regs[8] ... 8K ROM bank at CPU $8000
  // regs[9] ... 8K ROM bank at CPU $C000
  // regs[10] .. ROM Swap flag

  switch(addr & 0xF000)
  {
    case 0x8000:
      {
        if(regs[10] & 0x02)
        {
          regs[9] = data;
          set_CPU_bank6(data);
        }
        else
        {
          regs[8] = data;
          set_CPU_bank4(data);
        }
      }
      break;

    case 0xA000:
      {
        set_CPU_bank5(data);
      }
      break;
  }

  switch(addr & 0xF00F)
  {
    case 0x9000:
      {
        data &= 0x03;
        if(data == 0)
        {
          set_mirroring(NES_PPU::MIRROR_VERT);
        }
        else if(data == 1)
        {
          set_mirroring(NES_PPU::MIRROR_HORIZ);
        }
        else if(data == 2)
        {
          set_mirroring(0,0,0,0);
        }
        else
        {
          set_mirroring(1,1,1,1);
        }
      }
      break;

    case 0x9001:
    case 0x9004:
      {
        if((regs[10] & 0x02) != (data & 0x02))
        {
          uint8 swap = regs[8];
          regs[8] = regs[9];
          regs[9] = swap;
          set_CPU_bank4(regs[8]);
          set_CPU_bank6(regs[9]);
        }
        regs[10] = data;
      }
      break;

    case 0xB000:
      {
        regs[0] = (regs[0] & 0xF0) | (data & 0x0F);
        set_PPU_bank0(regs[0]);
      }
      break;

    case 0xB001:
    case 0xB004:
      {
        regs[1] = (regs[1] & 0xF0) | (data & 0x0F);
        set_PPU_bank1(regs[1]);
      }
      break;

    case 0xB002:
    case 0xB008:
      {
        regs[0] = (regs[0] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank0(regs[0]);
      }
      break;

    case 0xB003:
    case 0xB00C:
      {
        regs[1] = (regs[1] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank1(regs[1]);
      }
      break;

    case 0xC000:
      {
        regs[2] = (regs[2] & 0xF0) | (data & 0x0F);
        set_PPU_bank2(regs[2]);
      }
      break;

    case 0xC001:
    case 0xC004:
      {
        regs[3] = (regs[3] & 0xF0) | (data & 0x0F);
        set_PPU_bank3(regs[3]);
      }
      break;

    case 0xC002:
    case 0xC008:
      {
        regs[2] = (regs[2] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank2(regs[2]);
      }
      break;

    case 0xC003:
    case 0xC00C:
      {
        regs[3] = (regs[3] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank3(regs[3]);
      }
      break;

    case 0xD000:
      {
        regs[4] = (regs[4] & 0xF0) | (data & 0x0F);
        set_PPU_bank4(regs[4]);
      }
      break;

    case 0xD001:
    case 0xD004:
      {
        regs[5] = (regs[5] & 0xF0) | (data & 0x0F);
        set_PPU_bank5(regs[5]);
      }
      break;

    case 0xD002:
    case 0xD008:
      {
        regs[4] = (regs[4] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank4(regs[4]);
      }
      break;

    case 0xD003:
    case 0xD00C:
      {
        regs[5] = (regs[5] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank5(regs[5]);
      }
      break;

    case 0xE000:
      {
        regs[6] = (regs[6] & 0xF0) | (data & 0x0F);
        set_PPU_bank6(regs[6]);
      }
      break;

    case 0xE001:
    case 0xE004:
      {
        regs[7] = (regs[7] & 0xF0) | (data & 0x0F);
        set_PPU_bank7(regs[7]);
      }
      break;

    case 0xE002:
    case 0xE008:
      {
        regs[6] = (regs[6] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank6(regs[6]);
      }
      break;

    case 0xE003:
    case 0xE00C:
      {
        regs[7] = (regs[7] & 0x0F) | ((data & 0x0F) << 4);
        set_PPU_bank7(regs[7]);
      }
      break;

    case 0xF000:
      {
        irq_latch = (irq_latch & 0xF0) | (data & 0x0F);
      }
      break;

    case 0xF001:
    case 0xF004:
      {
        irq_enabled = data & 0x03;
        if(irq_enabled & 0x02)
        {
          irq_counter = irq_latch;
        }
      }
      break;

    case 0xF002:
    case 0xF008:
      {
        irq_latch = (irq_latch & 0x0F) | ((data & 0x0F) << 4);
      }
      break;

    case 0xF003:
    case 0xF00C:
      {
        irq_enabled = (irq_enabled & 0x01) * 3;
      }
      break;
  }
}