/* DolphinDOS parallel byte transfer - A866 */
uint8_t dolphin_putc(uint8_t data, uint8_t with_eoi) {
set_clock(1);
/* wait until DATA is high */
while (!IEC_DATA) // A870
if (iec_check_atn())
return -1;
if (with_eoi) {
/* signal EOI by waiting for a pulse on DATA */
while (IEC_DATA) // A87C
if (iec_check_atn())
return -1;
while (!IEC_DATA) // A883
if (iec_check_atn())
return -1;
}
/* send byte - A88A */
parallel_write(data);
parallel_send_handshake();
set_clock(0);
/* wait until DATA is low */
while (IEC_DATA) // A89A
if (iec_check_atn())
return -1;
return 0;
}
int16_t uload3_get_byte(void) {
uint8_t result;
/* initial handshake */
set_clock(0);
while (IEC_DATA && IEC_ATN) ;
if (!IEC_ATN)
return -1;
fastloader_setup();
disable_interrupts();
/* wait for start signal */
set_clock(1);
wait_data(1, NO_ATNABORT);
/* receive data */
result = generic_save_2bit(&uload3_get_def);
/* wait until the C64 releases the bus */
delay_us(20);
enable_interrupts();
fastloader_teardown();
return result;
}
static int
intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
struct i2c_adapter *adapter,
struct i2c_msg *msgs,
int num)
{
struct intel_gpio *gpio = container_of(adapter,
struct intel_gpio,
adapter);
int ret;
gma_intel_i2c_reset(dev_priv->dev);
intel_i2c_quirk_set(dev_priv, true);
set_data(gpio, 1);
set_clock(gpio, 1);
udelay(I2C_RISEFALL_TIME);
ret = adapter->algo->master_xfer(adapter, msgs, num);
set_data(gpio, 1);
set_clock(gpio, 1);
intel_i2c_quirk_set(dev_priv, false);
return ret;
}
/* Used by the FC3 C part */
void clk_data_handshake(void) {
set_clock(0);
while (IEC_DATA && IEC_ATN) ;
if (!IEC_ATN)
return;
set_clock(1);
while (!IEC_DATA && IEC_ATN) ;
}
uint8_t epyxcart_send_byte(uint8_t byte) {
uint8_t result = 0;
fastloader_setup();
disable_interrupts();
/* clear bus */
set_data(1);
set_clock(1);
delay_us(3);
/* wait for start signal */
wait_data(1, ATNABORT);
if (!IEC_ATN) {
result = 1;
goto exit;
}
/* transmit data */
generic_load_2bit(&epyxcart_send_def, byte);
/* data hold time */
delay_us(20);
exit:
disable_interrupts();
fastloader_teardown();
return result;
}
static void sync_clock_to_slave(Clock *c, Clock *slave)
{
double clock = get_clock(c);
double slave_clock = get_clock(slave);
if (!isnan(slave_clock) && (isnan(clock) || fabs(clock - slave_clock) > AV_NOSYNC_THRESHOLD))
set_clock(c, slave_clock, slave->serial);
}
void turbodisk_buffer(uint8_t *data, uint8_t length) {
unsigned int pair;
uint32_t ticks;
llfl_setup();
/* wait for handshake */
while (IEC_DATA) ;
set_clock(1);
llfl_wait_data(1, NO_ATNABORT);
ticks = 70;
while (length--) {
uint8_t byte = *data++;
ticks += 120;
for (pair = 0; pair < 4; pair++) {
ticks += 240;
llfl_set_clock_at(ticks, byte & 0x80, NO_WAIT);
llfl_set_data_at (ticks, byte & 0x40, WAIT);
ticks += 50;
byte <<= 2;
}
ticks += 100;
}
ticks += 110;
llfl_set_clock_at(ticks, 0, NO_WAIT);
llfl_set_data_at( ticks, 1, WAIT);
delay_us(5);
llfl_teardown();
}
static uint8_t fc3_oldfreeze_send(const uint8_t byte,
const generic_2bit_t *timingdef,
unsigned int busytime) {
fastloader_setup();
disable_interrupts();
/* clear busy */
set_clock(1);
set_data(1);
delay_us(15);
if (!IEC_ATN)
goto exit;
/* wait for start signal */
wait_clock(1, ATNABORT);
if (!IEC_ATN)
goto exit;
/* transmit data */
generic_load_2bit(timingdef, byte);
/* re-enable busy signal */
set_clock_at(busytime, 1, NO_WAIT);
set_data_at (busytime, 0, WAIT);
delay_us(1); // a little settle time for clock
exit:
enable_interrupts();
fastloader_teardown();
return !IEC_ATN;
}
TIMESTAMP collector::commit(TIMESTAMP t0, TIMESTAMP t1)
{
TIMESTAMP dt = (TIMESTAMP)get_interval();
if ( dt==0 || ( t1==next_t && next_t!=TS_NEVER ) )
{
char buffer[4096];
size_t eos = sprintf(buffer,"INSERT INTO `%s` (t", get_table());
int n;
for ( n=0 ; n<n_aggregates ; n++ )
eos += sprintf(buffer+eos,",`%s`",names[n]);
eos += sprintf(buffer+eos,") VALUES (from_unixtime(%lli)",gl_globalclock);
for ( n=0 ; n<n_aggregates ; n++ )
eos += sprintf(buffer+eos,",%g",list[n].get_value());
sprintf(buffer+eos,"%s",")");
if ( !db->query(buffer) )
exception("unable to add data to '%s' - %s", get_table(), mysql_error(mysql));
else
gl_verbose("%s: sample added to '%s' ok", get_name(), get_table());
// check limit
if ( get_limit()>0 && db->get_last_index()>=get_limit() )
{
gl_verbose("%s: limit of %d records reached", get_name(), get_limit());
next_t = TS_NEVER;
}
else
{
next_t = (dt==0 ? TS_NEVER : (TIMESTAMP)(t1/dt+1)*dt);
}
set_clock(t1);
}
return TS_NEVER;
}
uint8_t jiffy_receive(iec_bus_t *busstate) {
uint8_t result;
fastloader_setup();
disable_interrupts();
/* Initial handshake - wait for rising clock, but emulate ATN-ACK */
set_clock(1);
set_data(1);
do {
wait_clock(1, ATNABORT);
if (!IEC_ATN)
set_data(0);
} while (!IEC_CLOCK);
/* receive byte */
result = generic_save_2bit(&jiffy_receive_def);
/* read EOI info */
*busstate = read_bus_at(670);
/* exit with data low */
set_data_at(730, 0, WAIT);
delay_us(10);
enable_interrupts();
fastloader_teardown();
return result;
}
void kernel_start(void){
/* Initialisation de l'écran et du curseur */
efface_ecran();
place_curseur(0,0);
/* Initialisation des interruptions */
masque_IRQ(0, false);
init_traitant_IT(32, traitant_IT_32);
/* Initialisation de l'horloge */
set_clock();
/* Initialisation des processus */
cree_processus("idle", NULL, ELU);
cree_processus("proc_proc1", proc1, ACTIVABLE);
cree_processus("proc_proc2", proc2, ACTIVABLE);
cree_processus("proc_proc3", proc3, ACTIVABLE);
processus_elu = tab_processus[0];
/* Démarrage du processus par defaut */
idle();
while(1) {
hlt();
}
}
int board_early_init_f(void)
{
setup_iomux_unused_nc();
setup_iomux_unused_boot();
setup_iomux_sd();
setup_iomux_led();
setup_iomux_pinheader();
set_clock();
return 0;
}
void ffplayer::UpdateVideoPts(PInfo pYuvInfo)
{
//转换为UI上显示的时间
m_curTime = pYuvInfo->frameInfo.iTimestampObsolute*av_q2d(m_pFormatCtx->streams[m_videoStream]->time_base);
m_curPTS = pYuvInfo->frameInfo.iTimestampObsolute;//没转换的
m_lastserial = pYuvInfo->frameInfo.serial;
set_clock(&m_vidclk, m_curTime, m_lastserial);
m_iLastSystemTime = ::GetTickCount();
}
void dreamload_send_byte(uint8_t byte) {
unsigned int i;
for (i=0; i<2; i++) {
/* send bits 0,1 to bus */
set_clock(byte & 1);
set_data (byte & 2);
/* wait until ATN is low */
while (IEC_ATN) ;
/* send bits 2,3 to bus */
set_clock(byte & 4);
set_data (byte & 8);
/* wait until ATN is high */
while (!IEC_ATN) ;
/* move upper nibble down */
byte >>= 4;
}
}
/*
* Get the TOD clock running.
*/
static u64 __init reset_tod_clock(void)
{
u64 time;
etr_reset();
if (store_clock(&time) == 0)
return time;
/* TOD clock not running. Set the clock to Unix Epoch. */
if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0)
panic("TOD clock not operational.");
return TOD_UNIX_EPOCH;
}
/*
* Get the TOD clock running.
*/
static void __init reset_tod_clock(void)
{
u64 time;
if (store_clock(&time) == 0)
return;
/* TOD clock not running. Set the clock to Unix Epoch. */
if (set_clock(TOD_UNIX_EPOCH) != 0 || store_clock(&time) != 0)
disabled_wait(0);
sched_clock_base_cc = TOD_UNIX_EPOCH;
S390_lowcore.last_update_clock = sched_clock_base_cc;
}
static int
intel_i2c_quirk_xfer(struct intel_gmbus *bus,
struct i2c_msg *msgs,
int num)
{
struct drm_i915_private *dev_priv = bus->dev_priv;
int ret;
intel_i2c_reset(dev_priv->dev);
intel_i2c_quirk_set(dev_priv, true);
set_data(bus, 1);
set_clock(bus, 1);
udelay(I2C_RISEFALL_TIME);
ret = i2c_bit_algo.master_xfer(&bus->adapter, msgs, num);
set_data(bus, 1);
set_clock(bus, 1);
intel_i2c_quirk_set(dev_priv, false);
return ret;
}
static void geos_send_generic(uint8_t byte, const generic_2bit_t *timingdef, unsigned int holdtime_us) {
fastloader_setup();
/* initial handshake */
set_clock(1);
set_data(1);
wait_clock(0, NO_ATNABORT);
/* send data */
generic_load_2bit(timingdef, byte);
/* hold time */
delay_us(holdtime_us);
fastloader_teardown();
}
uint8_t jiffy_send(uint8_t value, uint8_t eoi, uint8_t loadflags) {
unsigned int loadmode = loadflags & 0x80;
unsigned int skipeoi = loadflags & 0x7f;
fastloader_setup();
disable_interrupts();
/* Initial handshake */
set_data(1);
set_clock(1);
delay_us(3);
if (loadmode) {
/* LOAD mode: start marker is data low */
while (!IEC_DATA) ; // wait until data actually is high again
wait_data(0, ATNABORT);
} else {
/* single byte mode: start marker is data high */
wait_data(1, ATNABORT);
}
/* transmit data */
generic_load_2bit(&jiffy_send_def, value);
/* Send EOI info */
if (!skipeoi) {
if (eoi) {
set_clock_at(520, 1, NO_WAIT);
set_data_at (520, 0, WAIT);
} else {
/* LOAD mode also uses this for the final byte of a block */
set_clock_at(520, 0, NO_WAIT);
set_data_at (520, 1, WAIT);
}
/* wait until data is low */
delay_us(3); // allow for slow rise time
while (IEC_DATA && IEC_ATN) ;
}
/* hold time */
delay_us(10);
enable_interrupts();
fastloader_teardown();
return !IEC_ATN;
}
void rgbled_refresh() {
uint8_t i;
for (i = 0; i < FILL_LEVELS; i++) {
uint8_t data_pin = 0;
uint8_t addr_pin = 0;
uint8_t led_no = 0;
uint8_t comp_no = 0;
while (1) {
refresh_func();
if (data_pin == 8 || (addr_pin * 8 + data_pin) == LEDS_COUNT * 3) {
set_clock(addr_pin);
data_pin = 0;
addr_pin++;
}
if (comp_no == 3) {
comp_no = 0;
led_no++;
}
if (led_no >= LEDS_COUNT)
break;
if (comp_no == 0) {
if (i >= led_states[led_no].r_cycles)
set_data_pin(data_pin, 0x01);
else
set_data_pin(data_pin, 0x00);
} else if (comp_no == 1) {
if (i >= led_states[led_no].g_cycles)
set_data_pin(data_pin, 0x01);
else
set_data_pin(data_pin, 0x00);
} else if (comp_no == 2) {
if (i >= led_states[led_no].b_cycles)
set_data_pin(data_pin, 0x01);
else
set_data_pin(data_pin, 0x00);
}
data_pin++;
comp_no++;
}
}
}
void turbodisk_byte(uint8_t value) {
llfl_setup();
/* wait for handshake */
while (IEC_DATA) ;
set_clock(1);
llfl_wait_data(1, NO_ATNABORT);
/* transmit data */
llfl_generic_load_2bit(&turbodisk_byte_def, value);
/* exit with clock low, data high */
llfl_set_clock_at(1470, 0, NO_WAIT);
llfl_set_data_at( 1470, 1, WAIT);
delay_us(5);
llfl_teardown();
}
/**
* intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg
* @dev: DRM device
* @output: driver specific output device
* @reg: GPIO reg to use
* @name: name for this bus
*
* Creates and registers a new i2c bus with the Linux i2c layer, for use
* in output probing and control (e.g. DDC or SDVO control functions).
*
* Possible values for @reg include:
* %GPIOA
* %GPIOB
* %GPIOC
* %GPIOD
* %GPIOE
* %GPIOF
* %GPIOG
* %GPIOH
* see PRM for details on how these different busses are used.
*/
struct intel_i2c_chan *intel_i2c_create(struct drm_device *dev, const u32 reg,
const char *name)
{
struct intel_i2c_chan *chan;
chan = kzalloc(sizeof(struct intel_i2c_chan), GFP_KERNEL);
if (!chan)
goto out_free;
chan->drm_dev = dev;
chan->reg = reg;
snprintf(chan->adapter.name, I2C_NAME_SIZE, "intel drm %s", name);
chan->adapter.owner = THIS_MODULE;
#ifndef I2C_HW_B_INTELFB
#define I2C_HW_B_INTELFB I2C_HW_B_I810
#endif
chan->adapter.id = I2C_HW_B_INTELFB;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &dev->pdev->dev;
chan->algo.setsda = set_data;
chan->algo.setscl = set_clock;
chan->algo.getsda = get_data;
chan->algo.getscl = get_clock;
chan->algo.udelay = 20;
chan->algo.timeout = usecs_to_jiffies(2200);
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
if(i2c_bit_add_bus(&chan->adapter))
goto out_free;
/* JJJ: raise SCL and SDA? */
set_data(chan, 1);
set_clock(chan, 1);
udelay(20);
return chan;
out_free:
kfree(chan);
return NULL;
}
/**
* intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg
* @dev: DRM device
* @output: driver specific output device
* @reg: GPIO reg to use
* @name: name for this bus
* @slave_addr: slave address (if fixed)
*
* Creates and registers a new i2c bus with the Linux i2c layer, for use
* in output probing and control (e.g. DDC or SDVO control functions).
*
* Possible values for @reg include:
* %GPIOA
* %GPIOB
* %GPIOC
* %GPIOD
* %GPIOE
* %GPIOF
* %GPIOG
* %GPIOH
* see PRM for details on how these different busses are used.
*/
struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg,
const char *name)
{
struct intel_i2c_chan *chan;
chan = kzalloc(sizeof(struct intel_i2c_chan), GFP_KERNEL);
if (!chan)
goto out_free;
chan->drm_dev = dev;
chan->reg = reg;
snprintf(chan->adapter.name, I2C_NAME_SIZE, "intel drm %s", name);
chan->adapter.owner = THIS_MODULE;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &dev->pdev->dev;
chan->algo.setsda = set_data;
chan->algo.setscl = set_clock;
chan->algo.getsda = get_data;
chan->algo.getscl = get_clock;
chan->algo.udelay = 20;
chan->algo.timeout = usecs_to_jiffies(2200);
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
if(i2c_bit_add_bus(&chan->adapter))
goto out_free;
intel_i2c_reset_gmbus(dev);
/* JJJ: raise SCL and SDA? */
intel_i2c_quirk_set(dev, true);
set_data(chan, 1);
set_clock(chan, 1);
intel_i2c_quirk_set(dev, false);
udelay(20);
return &chan->adapter;
out_free:
kfree(chan);
return NULL;
}
void ar6_1581_send_byte(uint8_t byte) {
fastloader_setup();
disable_interrupts();
/* wait for handshake */
set_clock(1);
wait_data(1, NO_ATNABORT);
/* transmit data */
generic_load_2bit(&ar6_1581_send_def, byte);
/* exit with clock low, data high */
set_clock_at(375, 0, NO_WAIT);
set_data_at( 375, 1, WAIT);
/* short delay to make sure bus has settled */
delay_us(10);
enable_interrupts();
fastloader_teardown();
}
TIMESTAMP database::commit(TIMESTAMP t0, TIMESTAMP t1)
{
set_clock();
if ( get_sync_interval()>0 )
{
gld_clock ts(t1);
int mod = ts.get_localtimestamp()%(TIMESTAMP)get_sync_interval();
if ( strcmp(get_on_sync(),"")!=0 && mod==0 )
{
int mod1 = t1%86400, mod2 = ts.get_timestamp()%86400, mod3 = ts.get_localtimestamp()%86400;
gld_clock ts(t0);
char buffer[64];
gl_verbose("%s running on_init script '%s' at %s", get_name(), get_on_sync(), ts.to_string(buffer,sizeof(buffer))?buffer:"(unknown time)");
int res = run_script(get_on_sync());
if ( res<=0 )
exception("on_init script '%s' failed at line %d: %s", get_on_sync(), -res, get_last_error());
}
return -(t1+get_sync_interval()-mod);
}
return TS_NEVER;
}
void n0sdos_send_byte(uint8_t byte) {
llfl_setup();
disable_interrupts();
/* wait for handshake */
set_clock(1);
set_data(1);
llfl_wait_clock(1, NO_ATNABORT);
/* transmit data */
llfl_generic_load_2bit(&n0sdos_send_def, byte);
/* exit with clock high, data low */
llfl_set_clock_at(380, 1, NO_WAIT);
llfl_set_data_at( 380, 0, WAIT);
/* C64 sets clock low at 42.5us, make sure we exit later than that */
delay_us(6);
enable_interrupts();
llfl_teardown();
}
uint8_t ar6_1581p_get_byte(void) {
uint8_t result;
fastloader_setup();
disable_interrupts();
set_clock(1);
/* wait for handshake */
while (IEC_DATA) ;
wait_data(1, NO_ATNABORT);
/* receive data */
result = generic_save_2bit(&ar6_1581p_get_def);
/* exit with clock low */
set_clock_at(530, 0, WAIT);
enable_interrupts();
fastloader_teardown();
return result;
}
/*!
* \brief Boot the kernel.
* - Set priorities
* - Set clock
* - Set os frequency,
* - Start allocator
* - Create the idle process. Allocator though will
* not give heap though before pkernel_run().
*
* \param __kmsize The pkernels size (aka the idle process stack size).
* \param clk The CPU clock used by application.
* \param os_f The OS freq requested by application.
*
* \return 0(proc_idle's pid) on success.
*/
int kinit (size_t kmsize, clock_t clk, clock_t os_f)
{
pid_t pid;
kSetPriority(kPendSV_IRQn, OS_PENDSV_PRI);
kSetPriority(kSysTick_IRQn, OS_SYSTICK_PRI);
set_clock (clk); // Set kernel's knowledge for clocking and freq
set_freq (os_f);
alloc_init (); // Init the Stack allocation table.
// Make the idle proc
pid = proc_newproc ((process_ptr_t)&proc_idle, kmsize, 0, 0);
/*
* \note
* We make sure that we are outside off ANY process (cur_pid=-1)
* so the idle's proc[0].tcb.sp remains untouched by PendSV until
* our first context_switch from idle.
*/
proc_set_current_pid(-1);
return (int)pid; // Must be 0 (idle's pid)
}
void oaktrail_lvds_i2c_init(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_intel_i2c_chan *chan;
chan = kzalloc(sizeof(struct psb_intel_i2c_chan), GFP_KERNEL);
if (!chan)
return;
chan->drm_dev = dev;
chan->reg = dev_priv->lpc_gpio_base;
strncpy(chan->adapter.name, "gma500 LPC", I2C_NAME_SIZE - 1);
chan->adapter.owner = THIS_MODULE;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &dev->pdev->dev;
chan->algo.setsda = set_data;
chan->algo.setscl = set_clock;
chan->algo.getsda = get_data;
chan->algo.getscl = get_clock;
chan->algo.udelay = 100;
chan->algo.timeout = usecs_to_jiffies(2200);
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
set_data(chan, 1);
set_clock(chan, 1);
udelay(50);
if (i2c_bit_add_bus(&chan->adapter)) {
kfree(chan);
return;
}
gma_encoder->ddc_bus = chan;
}
/// osc_pad_t::impl_t implementation
osc_pad_t::impl_t::impl_t(piw::clockdomain_ctl_t *cd, const piw::cookie_t &c,
const std::string &send_host, const std::string &send_port, const std::string &recv_port) :
root_t(0), up_(0),
server_( new osc_server_t(recv_port)), client_(new osc_client_t(send_host,send_port)),
view_(new live_model::live_view_t(model_,0,50,0,25))
{
connect(c);
cd->sink(this,"oscinput");
tick_enable(true);
set_clock(this);
light_wire_ = pic::ref(new light_wire_t(this));
connect_wire(light_wire_.ptr(), light_wire_->source());
client_->osc_startup();
server_->osc_startup();
server_->registerHandler(new clip_info_handler_t(light_wire_.ptr()));
server_->registerHandler(new track_info_handler_t(light_wire_.ptr()));
server_->registerHandler(new name_clip_handler_t(view(), client_));
server_->registerHandler(new armed_handler_t(view(), client_));
server_->registerHandler(new startup_handler_t(light_wire_.ptr()));
server_->registerHandler(new shutdown_handler_t(light_wire_.ptr()));
client_->send(new live_name_clip_message_t());
}