void bootblock_mainboard_init(void)
{
set_clock_sources();
/* Set up the pads required to load romstage. */
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
soc_configure_funits(funits, ARRAY_SIZE(funits));
/* PMIC */
i2c_init(I2CPWR_BUS);
pmic_init(I2CPWR_BUS);
/* TPM */
i2c_init(I2C3_BUS);
/* EC */
i2c_init(I2C2_BUS);
/*
* Set power detect override for GPIO, audio & sdmmc3 rails.
* GPIO rail override is required to put it into 1.8V mode.
*/
pmc_override_pwr_det(PMC_GPIO_RAIL_AO_MASK | PMC_AUDIO_RAIL_AO_MASK |
PMC_SDMMC3_RAIL_AO_MASK, PMC_GPIO_RAIL_AO_DISABLE |
PMC_AUDIO_RAIL_AO_DISABLE |
PMC_SDMMC3_RAIL_AO_DISABLE);
}
void bootblock_mainboard_init(void)
{
set_clock_sources();
/* Set up controllers and pads to load romstage. */
soc_configure_funits(funits, ARRAY_SIZE(funits));
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
i2c_init(I2CPWR_BUS);
pmic_init(I2CPWR_BUS);
}
void bootblock_mainboard_init(void)
{
set_clock_sources();
soc_configure_funits(funits, ARRAY_SIZE(funits));
i2c_init(I2CPWR_BUS);
pmic_init(I2CPWR_BUS);
/* Foster has no TPM yet. This is for future TPM. */
i2c_init(I2C3_BUS);
}
static void mainboard_init(device_t dev)
{
set_clock_sources();
clock_external_output(1); /* For external MAX98090 audio codec. */
/*
* Confirmed by NVIDIA hardware team, we need to take ALL audio devices
* conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
* of reset and clock-enabled, otherwise reading AHUB devices (In our
* case, I2S/APBIF/AUDIO<XBAR>) will hang.
*
* Note that CLK_H_MEM (MC) and CLK_H_EMC should be already either
* initialized by BootROM, or in romstage SDRAM initialization.
*/
clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
CLK_L_HOST1X | CLK_L_PWM,
CLK_H_I2C2 | CLK_H_PMC | CLK_H_USB3,
CLK_U_CSITE | CLK_U_SDMMC3,
CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF |
CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 |
CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2,
CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0,
CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 |
CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 |
CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
CLK_X_AFC5);
usb_setup_utmip((void*)TEGRA_USBD_BASE);
/* USB2 is the camera, we don't need it in firmware */
usb_setup_utmip((void*)TEGRA_USB3_BASE);
setup_pinmux();
i2c_init(0);
i2c_init(1);
i2c_init(3);
setup_kernel_info();
clock_init_arm_generic_timer();
setup_ec_spi();
#if CONFIG_ELOG
elog_init();
elog_add_boot_reason();
#endif
}
void bootblock_mainboard_init(void)
{
set_clock_sources();
/* Set up the pads required to load romstage. */
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
i2c_init(4);
pmic_init(4);
tegra_spi_init(4);
}
static void mainboard_init(device_t dev)
{
set_clock_sources();
clock_external_output(1); /* For external MAX98090 audio codec. */
/*
* Confirmed by NVIDIA hardware team, we need to take ALL audio devices
* conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
* of reset and clock-enabled, otherwise reading AHUB devices (In our
* case, I2S/APBIF/AUDIO<XBAR>) will hang.
*/
clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
CLK_L_HOST1X | CLK_L_PWM,
CLK_H_EMC | CLK_H_I2C2 | CLK_H_PMC |
CLK_H_MEM | CLK_H_USB2 | CLK_H_USB3,
CLK_U_CSITE | CLK_U_SDMMC3,
CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF |
CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 |
CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2,
CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0,
CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 |
CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 |
CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
CLK_X_AFC5);
usb_setup_utmip((void*)TEGRA_USBD_BASE);
usb_setup_utmip((void*)TEGRA_USB2_BASE);
usb_setup_utmip((void*)TEGRA_USB3_BASE);
setup_pinmux();
i2c_init(0);
i2c_init(1);
i2c_init(3);
setup_kernel_info();
clock_init_arm_generic_timer();
setup_ec_spi();
}
void bootblock_mainboard_init(void)
{
set_clock_sources();
clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
CLK_H_I2C5 | CLK_H_APBDMA,
0, CLK_V_MSELECT, 0, 0);
// Board ID GPIOs, bits 0-3.
gpio_input(GPIO(Q3));
gpio_input(GPIO(T1));
gpio_input(GPIO(X1));
gpio_input(GPIO(X4));
// I2C5 (PMU) clock.
pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
// I2C5 (PMU) data.
pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
i2c_init(4);
pmic_init(4);
/* SPI4 data out (MOSI) */
pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
PINMUX_PULL_UP);
/* SPI4 data in (MISO) */
pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
PINMUX_PULL_UP);
/* SPI4 clock */
pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
/* SPI4 chip select 0 */
pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
tegra_spi_init(4);
}
