static void
arm_macosx_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
/* We actually don't have any software float registers, so lets remove
the float info printer so we don't crash on "info float" commands. */
(gdbarch_tdep (gdbarch))->fp_model = ARM_FLOAT_NONE;
set_gdbarch_print_float_info (gdbarch, NULL);
set_gdbarch_stab_reg_to_regnum (gdbarch, arm_macosx_stab_reg_to_regnum);
set_gdbarch_skip_trampoline_code (gdbarch, macosx_skip_trampoline_code);
set_gdbarch_in_solib_return_trampoline (gdbarch,
macosx_in_solib_return_trampoline);
set_gdbarch_fetch_pointer_argument (gdbarch, arm_fetch_pointer_argument);
set_gdbarch_num_regs (gdbarch, ARM_MACOSX_NUM_REGS);
set_gdbarch_dbx_make_msymbol_special (gdbarch, arm_macosx_dbx_make_msymbol_special);
}
static void
arm_macosx_init_abi_v6 (struct gdbarch_info info, struct gdbarch *gdbarch)
{
/* Set the floating point model to be VFP and also initialize the
stab register number converter. */
(gdbarch_tdep (gdbarch))->fp_model = ARM_FLOAT_VFP;
set_gdbarch_stab_reg_to_regnum (gdbarch, arm_macosx_stab_reg_to_regnum);
set_gdbarch_skip_trampoline_code (gdbarch, macosx_skip_trampoline_code);
set_gdbarch_in_solib_return_trampoline (gdbarch,
macosx_in_solib_return_trampoline);
set_gdbarch_fetch_pointer_argument (gdbarch, arm_fetch_pointer_argument);
set_gdbarch_num_regs (gdbarch, ARM_V6_MACOSX_NUM_REGS);
set_gdbarch_num_pseudo_regs (gdbarch, ARM_MACOSX_NUM_VFP_PSEUDO_REGS);
set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_register_read);
set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_register_write);
set_gdbarch_dbx_make_msymbol_special (gdbarch, arm_macosx_dbx_make_msymbol_special);
}
void
amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* AMD64 generally uses `fxsave' instead of `fsave' for saving its
floating-point registers. */
tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
/* AMD64 has an FPU and 16 SSE registers. */
tdep->st0_regnum = AMD64_ST0_REGNUM;
tdep->num_xmm_regs = 16;
/* This is what all the fuss is about. */
set_gdbarch_long_bit (gdbarch, 64);
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 64);
/* In contrast to the i386, on AMD64 a `long double' actually takes
up 128 bits, even though it's still based on the i387 extended
floating-point format which has only 80 significant bits. */
set_gdbarch_long_double_bit (gdbarch, 128);
set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
set_gdbarch_register_name (gdbarch, amd64_register_name);
set_gdbarch_register_type (gdbarch, amd64_register_type);
/* Register numbers of various important registers. */
set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
/* APPLE LOCAL: Add the frame pointer register so it can be modified
in expressions. */
set_gdbarch_deprecated_fp_regnum (gdbarch, AMD64_RBP_REGNUM); /* %rbp */
/* The "default" register numbering scheme for AMD64 is referred to
as the "DWARF Register Number Mapping" in the System V psABI.
The preferred debugging format for all known AMD64 targets is
actually DWARF2, and GCC doesn't seem to support DWARF (that is
DWARF-1), but we provide the same mapping just in case. This
mapping is also used for stabs, which GCC does support. */
set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
/* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
be in use on any of the supported AMD64 targets. */
/* Call dummy code. */
set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
set_gdbarch_frame_align (gdbarch, amd64_frame_align);
set_gdbarch_frame_red_zone_size (gdbarch, 128);
set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p);
set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
set_gdbarch_return_value (gdbarch, amd64_return_value);
set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
/* Avoid wiring in the MMX registers for now. */
set_gdbarch_num_pseudo_regs (gdbarch, 0);
tdep->mm0_regnum = -1;
set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id);
frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer);
frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer);
frame_base_set_default (gdbarch, &amd64_frame_base);
/* If we have a register mapping, enable the generic core file support. */
if (tdep->gregset_reg_offset)
set_gdbarch_regset_from_core_section (gdbarch,
amd64_regset_from_core_section);
/* APPLE LOCAL: A handy little function. */
set_gdbarch_fetch_pointer_argument (gdbarch, amd64_fetch_pointer_argument);
}
