/*!
* This function is called for module initialization.
* It sets up the DVFS hardware.
* It sets default values for DVFS thresholds and counters. The default
* values was chosen from a set of different reasonable values. They was tested
* and the default values in the driver gave the best results.
* More work should be done to find optimal values.
*
* @return 0 if successful; non-zero otherwise.
*
*/
static int init_dvfs_controller(void)
{
u32 i, reg;
/* setup LTR0 */
reg = __raw_readl(MXC_CCM_LTR0);
reg = (reg & ~(MXC_CCM_LTR0_DIV3CK_MASK)) | DVFS_DIV3CK;
__raw_writel(reg, MXC_CCM_LTR0);
/* set up LTR1 */
reg = __raw_readl(MXC_CCM_LTR1);
reg = (reg & ~(MXC_CCM_LTR1_PNCTHR_MASK | MXC_CCM_LTR1_LTBRSR_MASK));
reg = reg | DVFS_PNCTHR | DVFS_LTBRSR;
__raw_writel(reg, MXC_CCM_LTR1);
/* setup LTR2 */
reg = __raw_readl(MXC_CCM_LTR2);
reg = (reg & ~(MXC_CCM_LTR2_EMAC_MASK)) | DVFS_EMAC;
__raw_writel(reg, MXC_CCM_LTR2);
/* Set general purpose weights to 0 */
for (i = 0; i < 16; i++)
set_gp_weight(i, ltr_gp_weight[i]);
/* ARM interrupt, mask load buf full interrupt */
reg = __raw_readl(MXC_CCM_PMCR0);
reg |= MXC_CCM_PMCR0_DVFIS | MXC_CCM_PMCR0_LBMI;
__raw_writel(reg, MXC_CCM_PMCR0);
return 0;
}
/*!
* This function is called for module initialization.
* It sets up the DVFS hardware.
* It sets default values for DVFS thresholds and counters. The default
* values was chosen from a set of different reasonable values. They was tested
* and the default values in the driver gave the best results.
* More work should be done to find optimal values.
*
* @return 0 if successful; non-zero otherwise.
*
*/
static int init_dvfs_controller(void)
{
u32 i, reg;
/* Configure 2 MC13783 DVFS pins */
mxc_request_iomux(MX31_PIN_DVFS0, OUTPUTCONFIG_FUNC, INPUTCONFIG_NONE);
mxc_request_iomux(MX31_PIN_DVFS1, OUTPUTCONFIG_FUNC, INPUTCONFIG_NONE);
/* Configure MC13783 voltage ready input pin */
mxc_request_iomux(MX31_PIN_GPIO1_5, OUTPUTCONFIG_GPIO,
INPUTCONFIG_FUNC);
/* setup LTR0 */
reg = __raw_readl(MXC_CCM_LTR0);
reg = (reg & ~(MXC_CCM_LTR0_CONFIG_MASK)) | MXC_CCM_LTR0_CONFIG_VAL;
__raw_writel(reg, MXC_CCM_LTR0);
/* set up LTR1 */
reg = __raw_readl(MXC_CCM_LTR1);
reg = (reg & ~(MXC_CCM_LTR1_CONFIG_MASK)) | MXC_CCM_LTR1_CONFIG_VAL;
__raw_writel(reg, MXC_CCM_LTR1);
/* setup LTR2 */
reg = __raw_readl(MXC_CCM_LTR2);
reg = (reg & ~(MXC_CCM_LTR2_EMAC_MASK)) | DVFS_EMAC;
__raw_writel(reg, MXC_CCM_LTR2);
/* Set general purpose weights to 0 */
for (i = 0; i < 16; i++) {
set_gp_weight(i, ltr_gp_weight[i]);
}
/* ARM interrupt, mask load buf full interrupt */
reg = __raw_readl(MXC_CCM_PMCR0);
reg |= MXC_CCM_PMCR0_DVFIS | MXC_CCM_PMCR0_LBMI;
__raw_writel(reg, MXC_CCM_PMCR0);
/* configuring EMI Handshake and PLL relock disable */
reg = __raw_readl(MXC_CCM_PMCR1);
reg |= MXC_CCM_PMCR1_PLLRDIS;
reg |= MXC_CCM_PMCR1_EMIRQ_EN;
__raw_writel(reg, MXC_CCM_PMCR1);
return 0;
}
