void __init arch_init_irq(void)
{
unsigned int i;
set_irq_priority();
/* clear interrupt counter for VPE0 and VPE1 */
if (isRT6855A)
tc_outl(CR_INTC_ITR, (1 << 18) | (1 << 10));
/* Disable all hardware interrupts */
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
/* Initialize IRQ action handlers */
for (i = 0; i < NR_IRQS; i++) {
#ifdef CONFIG_MIPS_TC3262
/*
* Only MT is using the software interrupts currently, so we just
* leave them uninitialized for other processors.
*/
if (cpu_has_mipsmt) {
if ((i == SI_SWINT1_INT0) || (i == SI_SWINT1_INT1) ||
(i == SI_SWINT_INT0) || (i == SI_SWINT_INT1)) {
set_irq_chip(i, &mips_mt_cpu_irq_controller);
continue;
}
}
if ((i == SI_TIMER_INT) || (i == SI_TIMER1_INT))
set_irq_chip_and_handler(i, &tc3162_irq_chip,
handle_percpu_irq);
else
set_irq_chip_and_handler(i, &tc3162_irq_chip,
handle_level_irq);
#else
set_irq_chip_and_handler(i, &tc3162_irq_chip,
handle_level_irq);
#endif
}
#ifdef CONFIG_MIPS_TC3262
if (cpu_has_veic || cpu_has_vint) {
write_c0_status((read_c0_status() & ~ST0_IM ) |
(STATUSF_IP0 | STATUSF_IP1));
/* register irq dispatch functions */
for (i = 0; i < NR_IRQS; i++)
set_vi_handler(i, irq_dispatch_tab[i]);
} else {
change_c0_status(ST0_IM, ALLINTS);
}
#else
/* Enable all interrupts */
change_c0_status(ST0_IM, ALLINTS);
#endif
#ifdef CONFIG_MIPS_MT_SMP
vsmp_int_init();
#endif
}
/*************************************************************************
* Function Name: PDB_init
* Parameters: none
* Return: none
* Description: PDB module initialization
*************************************************************************/
void PDB_init(void)
{
pdb_timer_config_t pdbUserConfig;
PDB_HAL_Init(PDB0_BASE_PTR);
PDB_HAL_SetAdcPreTriggerOutputEnable(PDB0_BASE_PTR, 0, (1U<<0)|(1U<<1), true);
PDB_HAL_SetAdcPreTriggerEnable(PDB0_BASE_PTR, 0, (1U<<0)|(1U<<1), true);
PDB_HAL_SetAdcPreTriggerBackToBackEnable(PDB0_BASE_PTR, 0, (1U<<1), true);
PDB_HAL_SetAdcPreTriggerDelayValue(PDB0_BASE_PTR, 0, 0, (PWM_MODULO / 6));
// Set load register mode
pdbUserConfig.loadValueMode = kPdbLoadValueImmediately;
// Select PDB external trigger source, it is from FTM0
pdbUserConfig.triggerInput = kPdbTrigger8;
PDB_HAL_ConfigTimer(PDB0_BASE_PTR,&pdbUserConfig);
PDB_HAL_Enable(PDB0_BASE_PTR);
PDB_HAL_SetTimerModulusValue(PDB0_BASE_PTR, 0x7fff);
PDB_HAL_SetLoadValuesCmd(PDB0_BASE_PTR);
// Set load register mode
pdbUserConfig.clkPreDiv = kPdbClkPreDivBy1;
pdbUserConfig.loadValueMode = kPdbLoadValueAtNextTrigger;
// Select PDB external trigger source, it is from FTM0
pdbUserConfig.triggerInput = kPdbTrigger8;
pdbUserConfig.seqErrIntEnable = true;
pdbUserConfig.clkPreMultFactor = kPdbClkPreMultFactorAs1;
PDB_HAL_ConfigTimer(PDB0_BASE_PTR,&pdbUserConfig);
PDB_HAL_SetLoadValuesCmd(PDB0_BASE_PTR);
enable_irq(g_pdbIrqId[0]);
set_irq_priority(g_pdbIrqId[0], ISR_PRIORITY_PDB0);
}
/* adc_init()
* Calibrates and initializes adc to perform single conversions and generate
* DMA requests at the end of the conversion
*
* */
void adc_init(void)
{
// Enable clocks
SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK; // ADC0 clock
// Calibrate ADC
adc_cal();
// Configure ADC
ADC0_CFG1 = 0; // Reset register
ADC0_CFG1 = (ADC_CFG1_MODE(3) | // 12 bits mode see table
ADC_CFG1_ADICLK(0)| // Input Bus Clock (20-25 MHz out of reset (FEI mode))
ADC_CFG1_ADIV(1)|ADC_CFG1_ADLSMP_MASK) ; // Clock divide by 2 (10-12.5 MHz)
ADC0_SC1A |= ADC_SC1_AIEN_MASK; // Interrupt enable
ADC0_CFG2=ADC_CFG2_ADHSC_MASK |ADC_CFG2_MUXSEL_MASK; //high speed conversion
ADC0_SC3=ADC_SC3_AVGE_MASK|ADC_SC3_AVGS(3);//hardware avg- 32 sampels
//ADC0_CV1=250;
enable_irq(INT_ADC0-16);
set_irq_priority(INT_ADC0-16,2);
//ADC0_SC2 |= ADC_SC2_DMAEN_MASK; // DMA Enable
//ADC0_SC2=ADC_SC2_ADTRG_MASK; //hardware triger
//ADC0_SC3 = 0; // Reset SC3
//ADC0_SC1A = ADC_SC1_ADCH(x); //adx chnner see table
ADC0_SC1A = ADC_SC1_ADCH(7)|ADC_SC1_AIEN_MASK;
}
/*
*******************************************************************************
* void SpiNVICEnable(SPI_MemMapPtr base)
*******************************************************************************
* Input : base : Pointer to SPI0/ SPI1 /SPI2 Register Base
* Output : void
* Description : Enable NVIC interrupt for respective SPI module
*******************************************************************************
*/
void SpiNVICEnable(SPI_MemMapPtr base)
{
if(SPI0_BASE_PTR == base)
{
set_irq_priority (INT_SPI0-16, 3);
enable_irq(INT_SPI0-16) ;
}
if(SPI1_BASE_PTR == base)
{
set_irq_priority (INT_SPI1-16, 3);
enable_irq(INT_SPI1-16) ;
}
if(SPI2_BASE_PTR == base)
{
set_irq_priority (INT_SPI2-16, 3);
enable_irq(INT_SPI2-16) ;
}
}//End of SpiClockEnable
/*************************************************************************
* Function Name: FTM2_init
* Parameters: none
* Return: none
* Description: FlexTimer 2 initialization
*************************************************************************/
void FTM2_init(void)
{
FTM_HAL_SetWriteProtectionCmd(FTM2_BASE_PTR, false);//false: Write-protection is disabled
FTM_HAL_Enable(FTM2_BASE_PTR, true);//true: all registers including FTM-specific registers are available
FTM_HAL_SetMod(FTM2_BASE_PTR, (uint16_t)0xffff);// Free running timer
FTM_HAL_SetClockSource(FTM2_BASE_PTR, kClock_source_FTM_SystemClk);//clock The FTM peripheral clock selection\n
FTM_HAL_SetClockPs(FTM2_BASE_PTR, kFtmDividedBy2); // system clock, divide by 2
FTM_HAL_EnableChnInt(FTM2_BASE_PTR, 0);//Enables the FTM peripheral timer channel(n) interrupt.
FTM_HAL_SetChnMSnBAMode(FTM2_BASE_PTR, 0, 1);//Sets the FTM peripheral timer channel mode.
INT_SYS_EnableIRQ(FTM2_IRQn);
set_irq_priority(FTM2_IRQn, ISR_PRIORITY_SLOW_TIMER);
}
static void prvSetupHardware( void )
{
/* Enable the interrupt on SW1. */
taskDISABLE_INTERRUPTS();
PORTE_PCR26 = PORT_PCR_MUX( 1 ) | PORT_PCR_IRQC( 0xA ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
enable_irq( mainGPIO_E_VECTOR );
/* The interrupt calls an interrupt safe API function - so its priority must
be equal to or lower than configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY. */
set_irq_priority( mainGPIO_E_VECTOR, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
/* Configure the LED outputs. */
vParTestInitialise();
}
void UltaSoincConfig(){
enable_irq(INT_PORTD-16); // Enable Interrupts
set_irq_priority (INT_PORTD-16,1); // Interrupt priority = 0 = max
PORTD_PCR2 = PORT_PCR_MUX(1);//|PORT_PCR_PS_MASK;//| PORT_PCR_PE_MASK ;
PORTD_PCR3 = PORT_PCR_MUX(1);
//PORTD_PCR2 |=PORT_PCR_IRQC(0xc);
GPIOD_PDDR &= (~PORT_LOC(2)||~PORT_LOC(3));
PORTD_ISFR |= 0xc; // clear interrupt flag bit of PTD6
GPIOD_PDDR |= PORT_LOC(1);
GPIOD_PSOR=0x2;
}
/**
* @brief: init MMA8451 INT1 interrupt pin
* @note: PTA14
* PULL UP
* Interrupt on falling edge
*
*/
void init_MMA8451_interrupt(void)
{
INT_ISR_FPTR isr;
// PTA14 -- MMA8451 INT1
// ALT1
/* PORTA_PCR14: ISF=0, MUX=1, IQRC=0x0A(1010), PE=1, PS=1 */
/*zga: in kl25, this pin is connected from chip to mcu*/
/*But in our cup design, pta5 is used as interrupt pin*/
// PORTA_PCR14 = 0x000A0103;
//GPIOA_PDDR &= ~(1<<14);
PORTA_PCR5 = 0x000A0103;
GPIOA_PDDR &= ~(1<<5);
isr = _int_install_isr(LDD_ivIndex_INT_PORTA, MMA8451_INT1_isr_service, NULL);
ASSERT_PARAM(isr != NULL);
// ENABLE PTE5 Falling interrupt
enable_irq(30);
set_irq_priority(30, 2);
}
static void prvSetupHardware( void )
{
/* Enable the interrupt on SW1. */
PORTE_PCR26 = PORT_PCR_MUX( 1 ) | PORT_PCR_IRQC( 0xA ) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
enable_irq( mainGPIO_E_VECTOR );
/* The interrupt calls an interrupt safe API function - so its priority must
be equal to or lower than configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY. */
set_irq_priority( mainGPIO_E_VECTOR, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
/* Set PTA10, PTA11, PTA28, and PTA29 (connected to LED's) for GPIO
functionality. */
PORTA_PCR10 = ( 0 | PORT_PCR_MUX( 1 ) );
PORTA_PCR11 = ( 0 | PORT_PCR_MUX( 1 ) );
PORTA_PCR28 = ( 0 | PORT_PCR_MUX( 1 ) );
PORTA_PCR29 = ( 0 | PORT_PCR_MUX( 1 ) );
/* Change PTA10, PTA29 to outputs. */
GPIOA_PDDR=GPIO_PDDR_PDD( mainTASK_CONTROLLED_LED | mainTIMER_CONTROLLED_LED );
/* Start with LEDs off. */
GPIOA_PTOR = ~0U;
}
void vEMACInit( void )
{
int iData;
extern int periph_clk_khz;
const unsigned portCHAR ucMACAddress[] =
{
configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5
};
/* Enable the ENET clock. */
SIM_SCGC2 |= SIM_SCGC2_ENET_MASK;
/* Allow concurrent access to MPU controller to avoid bus errors. */
MPU_CESR = 0;
prvInitialiseDescriptors();
/* Reset and enable. */
ENET_ECR = ENET_ECR_RESET_MASK;
/* Wait at least 8 clock cycles */
vTaskDelay( 2 );
/* Start the MII interface*/
mii_init( 0, periph_clk_khz / 1000L );
/* Configure the transmit interrupt. */
set_irq_priority( emacTX_INTERRUPT_NO, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
enable_irq( emacTX_INTERRUPT_NO );
/* Configure the receive interrupt. */
set_irq_priority( emacRX_INTERRUPT_NO, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
enable_irq( emacRX_INTERRUPT_NO );
/* Configure the error interrupt. */
set_irq_priority( emacERROR_INTERRUPT_NO, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
enable_irq( emacERROR_INTERRUPT_NO );
/* Configure the pins to the PHY - RMII mode used. */
PORTB_PCR0 = PORT_PCR_MUX( 4 ); /* RMII0_MDIO / MII0_MDIO. */
PORTB_PCR1 = PORT_PCR_MUX( 4 ); /* RMII0_MDC / MII0_MDC */
PORTA_PCR14 = PORT_PCR_MUX( 4 ); /* RMII0_CRS_DV / MII0_RXDV */
PORTA_PCR12 = PORT_PCR_MUX( 4 ); /* RMII0_RXD1 / MII0_RXD1 */
PORTA_PCR13 = PORT_PCR_MUX( 4 ); /* RMII0_RXD0/MII0_RXD0 */
PORTA_PCR15 = PORT_PCR_MUX( 4 ); /* RMII0_TXEN/MII0_TXEN */
PORTA_PCR16 = PORT_PCR_MUX( 4 ); /* RMII0_TXD0/MII0_TXD0 */
PORTA_PCR17 = PORT_PCR_MUX( 4 ); /* RMII0_TXD1/MII0_TXD1 */
/* Is there communication with the PHY? */
do
{
vTaskDelay( emacLINK_DELAY );
iData = 0xFFFF;
mii_read( 0, configPHY_ADDRESS, PHY_PHYIDR1, &iData );
} while( iData == 0xFFFF );
/* Start to auto negotiate. */
mii_write( 0, configPHY_ADDRESS, PHY_BMCR, ( PHY_BMCR_AN_RESTART | PHY_BMCR_AN_ENABLE ) );
/* Wait for auto negotiate to complete. */
do
{
vTaskDelay( emacLINK_DELAY );
mii_read( 0, configPHY_ADDRESS, PHY_BMSR, &iData );
} while( !( iData & PHY_BMSR_AN_COMPLETE ) );
/* A link has been established. What was negotiated? */
iData = 0;
mii_read( 0, configPHY_ADDRESS, emacPHY_STATUS, &iData );
/* Clear the Individual and Group Address Hash registers */
ENET_IALR = 0;
ENET_IAUR = 0;
ENET_GALR = 0;
ENET_GAUR = 0;
/* Set the Physical Address for the selected ENET */
enet_set_address( 0, ucMACAddress );
ENET_RCR = ENET_RCR_MAX_FL( UIP_BUFSIZE ) | ENET_RCR_MII_MODE_MASK | ENET_RCR_CRCFWD_MASK | ENET_RCR_RMII_MODE_MASK;
/* Clear the control registers. */
ENET_TCR = 0;
if( iData & emacPHY_DUPLEX_STATUS )
{
/* Full duplex */
ENET_RCR &= ( unsigned long )~ENET_RCR_DRT_MASK;
ENET_TCR |= ENET_TCR_FDEN_MASK;
}
else
{
/* Half duplex */
ENET_RCR |= ENET_RCR_DRT_MASK;
ENET_TCR &= (unsigned portLONG)~ENET_TCR_FDEN_MASK;
}
if( iData & emacPHY_SPEED_STATUS )
{
/* 10Mbps */
ENET_RCR |= ENET_RCR_RMII_10T_MASK;
}
ENET_ECR = ENET_ECR_EN1588_MASK;
/* Store and forward checksum. */
ENET_TFWR = ENET_TFWR_STRFWD_MASK;
/* Set Rx Buffer Size */
ENET_MRBR = ( unsigned short ) UIP_BUFSIZE;
/* Point to the start of the circular Rx buffer descriptor queue */
ENET_RDSR = ( unsigned long ) &( xRxDescriptors[ 0 ] );
/* Point to the start of the circular Tx buffer descriptor queue */
ENET_TDSR = ( unsigned long ) &( xTxDescriptors[ 0 ] );
/* Clear all ENET interrupt events */
ENET_EIR = ( unsigned long ) -1;
/* Enable interrupts. */
ENET_EIMR = 0
/*rx irqs*/
| ENET_EIMR_RXF_MASK/* only for complete frame, not partial buffer descriptor | ENET_EIMR_RXB_MASK*/
/*xmit irqs*/
| ENET_EIMR_TXF_MASK/* only for complete frame, not partial buffer descriptor | ENET_EIMR_TXB_MASK*/
/*enet irqs*/
| ENET_EIMR_UN_MASK | ENET_EIMR_RL_MASK | ENET_EIMR_LC_MASK | ENET_EIMR_BABT_MASK | ENET_EIMR_BABR_MASK | ENET_EIMR_EBERR_MASK
;
/* Enable the MAC itself. */
ENET_ECR |= ENET_ECR_ETHEREN_MASK;
/* Indicate that there have been empty receive buffers produced */
ENET_RDAR = ENET_RDAR_RDAR_MASK;
}
/*
* LPLD_ENET_Init
* ENET模块初始化，包括PHY收发器初始化，MAC初始化，BD初始化
*
* 参数:
* *MACAddress--MAC地址指针
*
* 输出:
* 无
*/
void LPLD_ENET_Init(const uint8* MACAddress)
{
uint16 usData;
//使能ENET时钟
SIM_SCGC2 |= SIM_SCGC2_ENET_MASK;
//允许并发访问MPU控制器
MPU_CESR = 0;
//缓冲区描述符初始化
LPLD_ENET_BDInit();
//复位ENET
ENET_ECR = ENET_ECR_RESET_MASK;
//等待至少8个时钟周期
for( usData = 0; usData < 10; usData++ )
{
asm( "NOP" );
}
//初始化MII接口
LPLD_ENET_MiiInit(periph_clk_khz/1000/*MHz*/);
//使能中断并设置优先级
set_irq_priority (76, 6);
enable_irq(76); //ENET发送中断
set_irq_priority (77, 6);
enable_irq(77); //ENET接收中断
//set_irq_priority (78, 6);
//enable_irq(78); //ENET错误及其他中断
//使能GPIO引脚复用功能
PORTB_PCR0 = PORT_PCR_MUX(4); //GPIO;//RMII0_MDIO/MII0_MDIO
PORTB_PCR1 = PORT_PCR_MUX(4); //GPIO;//RMII0_MDC/MII0_MDC
PORTA_PCR14 = PORT_PCR_MUX(4); //RMII0_CRS_DV/MII0_RXDV
PORTA_PCR12 = PORT_PCR_MUX(4); //RMII0_RXD1/MII0_RXD1
PORTA_PCR13 = PORT_PCR_MUX(4); //RMII0_RXD0/MII0_RXD0
PORTA_PCR15 = PORT_PCR_MUX(4); //RMII0_TXEN/MII0_TXEN
PORTA_PCR16 = PORT_PCR_MUX(4); //RMII0_TXD0/MII0_TXD0
PORTA_PCR17 = PORT_PCR_MUX(4); //RMII0_TXD1/MII0_TXD1
//等待PHY收发器复位完成
do
{
LPLD_ENET_Delay( ENET_LINK_DELAY );
usData = 0xffff;
LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_PHYIDR1, &usData );
} while( usData == 0xffff );
#ifdef PHY_PRINT_REG
printf("PHY_PHYIDR1=0x%X\r\n",usData);
LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_PHYIDR2, &usData );
printf("PHY_PHYIDR2=0x%X\r\n",usData);
LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_ANLPAR, &usData );
printf("PHY_ANLPAR=0x%X\r\n",usData);
LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_ANLPARNP, &usData );
printf("PHY_ANLPARNP=0x%X\r\n",usData);
LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_PHYSTS, &usData );
printf("PHY_PHYSTS=0x%X\r\n",usData);
LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_MICR, &usData );
printf("PHY_MICR=0x%X\r\n",usData);
LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_MISR, &usData );
printf("PHY_MISR=0x%X\r\n",usData);
#endif
//开始自动协商
LPLD_ENET_MiiWrite(CFG_PHY_ADDRESS, PHY_BMCR, ( PHY_BMCR_AN_RESTART | PHY_BMCR_AN_ENABLE ) );
#ifdef PHY_PRINT_REG
LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_BMCR, &usData );
printf("PHY_BMCR=0x%X\r\n",usData);
#endif
//等待自动协商完成
do
{
LPLD_ENET_Delay( ENET_LINK_DELAY );
LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_BMSR, &usData );
} while( !( usData & PHY_BMSR_AN_COMPLETE ) );
#ifdef PHY_PRINT_REG
printf("PHY_BMSR=0x%X\r\n",usData);
#endif
//根据协商结果设置ENET模块
LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_STATUS, &usData );
#ifdef PHY_PRINT_REG
printf("PHY_STATUS=0x%X\r\n",usData);
#endif
//清除单独和组地址哈希寄存器
ENET_IALR = 0;
ENET_IAUR = 0;
ENET_GALR = 0;
ENET_GAUR = 0;
//设置ENET模块MAC地址
LPLD_ENET_SetAddress(MACAddress);
//设置接收控制寄存器，最大长度、RMII模式、接收CRC校验等
ENET_RCR = ENET_RCR_MAX_FL(CFG_ENET_MAX_PACKET_SIZE) | ENET_RCR_MII_MODE_MASK | ENET_RCR_CRCFWD_MASK | ENET_RCR_RMII_MODE_MASK;
//清除发送接收控制
ENET_TCR = 0;
//通讯方式设置
if( usData & PHY_DUPLEX_STATUS )
{
//全双工
ENET_RCR &= (unsigned long)~ENET_RCR_DRT_MASK;
ENET_TCR |= ENET_TCR_FDEN_MASK;
}
else
{
//半双工
ENET_RCR |= ENET_RCR_DRT_MASK;
ENET_TCR &= (unsigned long)~ENET_TCR_FDEN_MASK;
}
//通信速率设置
if( usData & PHY_SPEED_STATUS )
{
//10Mbps
ENET_RCR |= ENET_RCR_RMII_10T_MASK;
}
//使用非增强型缓冲区描述符
ENET_ECR = 0;
//设置接收缓冲区长度
ENET_MRBR = (unsigned short) CFG_ENET_RX_BUFFER_SIZE;
//指向环形接收缓冲区描述符序列的头地址
ENET_RDSR = ( unsigned long ) &( xENETRxDescriptors[ 0 ] );
//指向环形发送缓冲区描述符序列的头地址
ENET_TDSR = ( unsigned long ) xENETTxDescriptors;
//清除ENET中断事件
ENET_EIR = ( unsigned long ) -1;
//使能中断
ENET_EIMR = 0
| ENET_EIMR_RXF_MASK //接收中断
| ENET_EIMR_TXF_MASK //发送中断
//ENET中断
| ENET_EIMR_UN_MASK | ENET_EIMR_RL_MASK | ENET_EIMR_LC_MASK | ENET_EIMR_BABT_MASK | ENET_EIMR_BABR_MASK | ENET_EIMR_EBERR_MASK
| ENET_EIMR_RXB_MASK
;
//使能ENET模块
ENET_ECR |= ENET_ECR_ETHEREN_MASK;
//表明接收缓冲区为空
ENET_RDAR = ENET_RDAR_RDAR_MASK;
}
/*************************************************************************
* Function Name: ADC0_init
* Parameters: none
* Return: none
* Description: ADC0 module initialization
*************************************************************************/
int ADC0_init(void)
{
long tmp=0;
long tmp1=0;
long tmp2=0;
register uint16 i = 0, numLoops = ((uint16) 1 << TWO_POWER_N_SAMPLES);
tADC_CALIB adc0_calib;
#if FSL_FEATURE_ADC16_HAS_HW_AVERAGE
adc16_hw_average_config_t userHwAverageConfig;
#endif
/* ADC calibration */
adcUserConfig.clkSrc = kAdc16ClkSrcOfBusClk;
adcUserConfig.resolution = kAdc16ResolutionBitOfSingleEndAs12;
adcUserConfig.clkDividerMode =kAdc16ClkDividerOf1;
adcUserConfig.highSpeedEnable = true;
adcUserConfig.hwTriggerEnable = false;
// high-speed mode, 2 extra ADC clock cycles; 6 ADCK cycles sample time
adcUserConfig.longSampleCycleMode = kAdc16LongSampleCycleOf6;
adcUserConfig.refVoltSrc = kAdc16RefVoltSrcOfVref;
ADC16_HAL_ConfigConverter(ADC0_BASE_PTR, &adcUserConfig);
/* calibration loop */
while ((i++) < numLoops)
{
/* The input channel, conversion mode continuous function, compare */
/* function, resolution mode, and differential/single-ended mode are */
/* all ignored during the calibration function. */
adcChnConfig.chnIdx = (adc16_chn_t)ADC_CHANNEL_DISABLED;
#if FSL_FEATURE_ADC16_HAS_DIFF_MODE
adcChnConfig.diffConvEnable = false;
#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
adcChnConfig.convCompletedIntEnable = false;
ADC16_HAL_ConfigChn(ADC0_BASE_PTR, 0, &adcChnConfig);
#if FSL_FEATURE_ADC16_HAS_HW_AVERAGE
// Use hardware average to increase stability of the measurement.
userHwAverageConfig.hwAverageEnable = true;
userHwAverageConfig.hwAverageCountMode = kAdc16HwAverageCountOf4;
ADC16_HAL_ConfigHwAverage(ADC0_BASE_PTR, &userHwAverageConfig);
#endif // FSL_FEATURE_ADC16_HAS_HW_AVERAGE
ADC16_HAL_SetAutoCalibrationCmd(ADC0_BASE_PTR, true);
while (!ADC16_HAL_GetChnConvCompletedFlag(ADC0_BASE_PTR, 0));
if (ADC16_HAL_GetAutoCalibrationFailedFlag(ADC0_BASE_PTR))
{
ADC16_HAL_SetAutoCalibrationCmd(ADC0_BASE_PTR, true);
return 1;
}
tmp+= (short int) ADC16_HAL_GetOffsetValue(ADC0_BASE_PTR);
tmp1+= ADC16_HAL_GetAutoPlusSideGainValue(ADC0_BASE_PTR);
tmp2+= ADC16_HAL_GetAutoMinusSideGainValue(ADC0_BASE_PTR);
}
adc0_calib.OFS = tmp >> TWO_POWER_N_SAMPLES;
tmp1 = tmp1&(~0x8000);
tmp1 = tmp1 >> TWO_POWER_N_SAMPLES;
adc0_calib.PG = (tmp1|0x8000);
tmp2 = tmp2&(~0x8000);
tmp2 = tmp2 >> TWO_POWER_N_SAMPLES;
adc0_calib.MG = (tmp2|0x8000);
//ADC0->PG = adc0_calib.PG;
//ADC0->MG = adc0_calib.MG;
//ADC0->OFS = adc0_calib.OFS;
ADC16_HAL_SetPlusSideGainValue(ADC0_BASE_PTR, adc0_calib.PG);
ADC16_HAL_SetMinusSideGainValue(ADC0_BASE_PTR, adc0_calib.MG);
ADC16_HAL_SetOffsetValue(ADC0_BASE_PTR, adc0_calib.OFS);
/* End of ADC calibration */
enable_irq(ADC0_IRQn);
set_irq_priority(ADC0_IRQn, ISR_PRIORITY_ADC0);
// Bus clock / 1 (24 MHz), 12-bit, Bus clock source
// high-speed mode, 2 extra ADC clock cycles; 6 ADCK cycles sample time
// high-speed mode, 2 extra ADC clock cycles; 6 ADCK cycles sample time
adcUserConfig.clkSrc = kAdc16ClkSrcOfBusClk;
adcUserConfig.resolution = kAdc16ResolutionBitOfSingleEndAs12;
adcUserConfig.clkDividerMode =kAdc16ClkDividerOf1;
adcUserConfig.highSpeedEnable = true;
adcUserConfig.lowPowerEnable = false;
adcUserConfig.longSampleTimeEnable = false;
adcUserConfig.asyncClkEnable = false;
adcUserConfig.continuousConvEnable = false;
adcUserConfig.hwTriggerEnable = true;
adcUserConfig.longSampleCycleMode = kAdc16LongSampleCycleOf6;
adcUserConfig.refVoltSrc = kAdc16RefVoltSrcOfVref;
#if FSL_FEATURE_ADC16_HAS_DMA
adcUserConfig.dmaEnable = false; //DMA disabled
#endif /* FSL_FEATURE_ADC16_HAS_DMA */
ADC16_HAL_ConfigConverter(ADC0_BASE_PTR, &adcUserConfig);
#if FSL_FEATURE_ADC16_HAS_MUX_SELECT
// H/W trigger
ADC16_HAL_SetChnMuxMode(ADC0_BASE_PTR, kAdc16ChnMuxOfA);
#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
/* Hardware compare. */
/* Available range is between cmpValue1 and cmpValue2. */
adcHwCmpConfig.hwCmpEnable = false;
adcHwCmpConfig.hwCmpRangeEnable = false;
adcHwCmpConfig.hwCmpGreaterThanEnable = false;
adcHwCmpConfig.cmpValue1 = 0x0001U;
adcHwCmpConfig.cmpValue2 = 0x0001U;
ADC16_HAL_ConfigHwCompare(ADC0_BASE_PTR, &adcHwCmpConfig);
#if FSL_FEATURE_ADC16_HAS_HW_AVERAGE
// Use hardware average to increase stability of the measurement.
userHwAverageConfig.hwAverageEnable = false;
userHwAverageConfig.hwAverageCountMode = kAdc16HwAverageCountOf32;
ADC16_HAL_ConfigHwAverage(ADC0_BASE_PTR, &userHwAverageConfig);
#endif // FSL_FEATURE_ADC16_HAS_HW_AVERAGE
ADC16_HAL_SetAutoCalibrationCmd(ADC0_BASE_PTR, false);
adcChnConfig.chnIdx = (adc16_chn_t)ADC_CHANNEL_DCBV;
#if FSL_FEATURE_ADC16_HAS_DIFF_MODE
adcChnConfig.diffConvEnable = false;
#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
adcChnConfig.convCompletedIntEnable = false;
ADC16_HAL_ConfigChn(ADC0_BASE_PTR, 0,&adcChnConfig);
adcChnConfig.convCompletedIntEnable = true;
ADC16_HAL_ConfigChn(ADC0_BASE_PTR, 1,&adcChnConfig);
return 0;
}
/* User includes (#include below this line is not maintained by Processor Expert) */
static portTASK_FUNCTION(Task1, pvParameters)
{
(void)pvParameters; /* ignore unused parameter */
int spiFlag = 1;
uint8_t txBuffer[5];
uint8_t rxBuffer[5];
YellowLEDInit();
// PerformanceGPIOInit();
// ADC0Init();
ADC0_Init();
PDB0Init();
// SPI2_Init();
// Spi1MasterInit(SPI2_BASE_PTR,BAUDRATE_500KHZ);
// PDB0_Init();
hal_spi_init();
// hal_spi_transfe_start();
// txBuffer[0] = hal_spi_transfer_one_byte(0x9F,0);
// txBuffer[1] = hal_spi_transfer_one_byte(0x0,0);
// txBuffer[2] = hal_spi_transfer_one_byte(0x0,0);
// txBuffer[3] = hal_spi_transfer_one_byte(0x0,0);
// txBuffer[4] = hal_spi_transfer_one_byte(0x0,1);
// hal_spi_transfe_stop();
// printf("%x %x %x %x %x\n",txBuffer[1],txBuffer[2],txBuffer[3],txBuffer[4]);
//
// Enable the ADC and PDB interrupts in NVIC
set_irq_priority (INT_ADC0-16, 2);
enable_irq(INT_ADC0-16) ; // ready for this interrupt.
set_irq_priority (INT_PDB0-16, 2);
enable_irq(INT_PDB0-16) ; // ready for this interrupt.
set_irq_priority (INT_SPI2-16, 2);
enable_irq(INT_SPI2-16) ; // ready for this interrupt.
// set_irq_priority (INT_SWI-16, 3);
// enable_irq(INT_SWI-16);
EnableInterrupts;
// NVICSTIR = (INT_SWI-16);
// Start triggering from PDB peripheral
PDB0_SC |= PDB_SC_SWTRIG_MASK;
for(;;)
{
// GreenLED_Neg();
NegYellowLED();
// hal_spi_transfe_start();
// txBuffer[0] = hal_spi_transfer_one_byte(0x9F,0);
// txBuffer[1] = hal_spi_transfer_one_byte(0x0,0);
// txBuffer[2] = hal_spi_transfer_one_byte(0x0,0);
// txBuffer[3] = hal_spi_transfer_one_byte(0x0,0);
// txBuffer[4] = hal_spi_transfer_one_byte(0x0,1);
// hal_spi_transfe_stop();
// printf("%x %x %x %x %x\n",txBuffer[1],txBuffer[2],txBuffer[3],txBuffer[4]);
if(spiFlag)
{
// spiFlag = 0;
txBuffer[0] = 0x9f;
Spi2MasterTx(txBuffer,rxBuffer,4);
}
FRTOS1_vTaskDelay(100/portTICK_RATE_MS); /* wait for 100 ms */
} /* for */
}
