static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
{
	u32 validatedStep=step;
	int err;
	
	if (mali_step_lock > -1 && step != mali_step_lock) {
		step = mali_step_lock;
	}

#ifdef CONFIG_REGULATOR
	if (mali_regulator_get_usecount() == 0) {
		MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n"));
		return MALI_FALSE;
	}
#endif

	if (boostup) {
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
	} else {
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
	}

#ifdef EXYNOS4_ASV_ENABLED
#ifndef CONFIG_ABB_CONTROL
	if (samsung_rev() < EXYNOS4412_REV_2_0) {
		if (mali_dvfs[step].clock == 160)
			exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V);
		else
			exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V);
	}
#else
	abb_target(ABB_G3D, mali_dvfs[step].clock*1000);
#endif
#endif


	set_mali_dvfs_current_step(validatedStep);
	/*for future use*/
	maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep];

#if CPUFREQ_LOCK_DURING_440
	/* lock/unlock CPU freq by Mali */
	if (mali_dvfs[step].clock == 440)
		err = cpufreq_lock_by_mali(1200);
	else
		cpufreq_unlock_by_mali();
#endif

	return MALI_TRUE;
}
Exemplo n.º 2
0
static _mali_osk_errcode_t enable_mali_clocks(void)
{
	int err;
	err = clk_enable(mali_clock);
	MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err));

	mali_runtime_resume.vol = mali_dvfs_get_vol(MALI_DVFS_STEPS + 1);
#if MALI_PMM_RUNTIME_JOB_CONTROL_ON
#if MALI_DVFS_ENABLED
	// set clock rate
	if (get_mali_dvfs_control_status() != 0 || mali_gpu_clk >= mali_runtime_resume.clk)
		mali_clk_set_rate(mali_gpu_clk, GPU_MHZ);
	else {
		mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol);
		mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ);
	}
	if (mali_gpu_clk <= mali_runtime_resume.clk)
		set_mali_dvfs_current_step(MALI_DVFS_STEPS + 1);
	/* lock/unlock CPU freq by Mali */
	if (mali_gpu_clk >= 533)
		err = cpufreq_lock_by_mali(1400);
	else if (mali_gpu_clk == 440)
		err = cpufreq_lock_by_mali(1200);
#else
	mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol);
	mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ);
#endif
#else
	mali_clk_set_rate(mali_gpu_clk, GPU_MHZ);
#endif
	MALI_SUCCESS;
}
Exemplo n.º 3
0
static _mali_osk_errcode_t enable_mali_clocks(struct device *dev)
{
	int err;
	err = clk_enable(mali_clock);
	MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err));

	/* set clock rate */
#ifdef CONFIG_MALI_DVFS
	if (mali_dvfs_control != 0 || mali_gpu_clk >= mali_runtime_resume.clk) {
		mali_clk_set_rate(mali_gpu_clk, GPU_MHZ);
	} else {
#ifdef CONFIG_REGULATOR
		mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol);
		exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_runtime_resume.clk * GPU_ASV_VOLT));
#endif
		mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ);
		set_mali_dvfs_current_step(mali_runtime_resume.step);
	}
#else
	mali_clk_set_rate((unsigned int)mali_gpu_clk, GPU_MHZ);

	maliDvfsStatus.currentStep = MALI_DVFS_DEFAULT_STEP;
#endif

	MALI_SUCCESS;
}
Exemplo n.º 4
0
static _mali_osk_errcode_t enable_mali_clocks(void)
{
	int err;
	err = clk_enable(mali_clock);
	MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err));

#if 0
#if MALI_DVFS_ENABLED
	// set clock rate
	if (get_mali_dvfs_control_status() != 0 || mali_gpu_clk >= mali_runtime_resume.clk)
		mali_clk_set_rate(mali_gpu_clk, GPU_MHZ);
	else {
		mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol);
		mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ);
		set_mali_dvfs_current_step(MALI_DVFS_DEFAULT_STEP);
	}
#if CPUFREQ_LOCK_DURING_440
	/* lock/unlock CPU freq by Mali */
	if (mali_gpu_clk >= 533)
		err = cpufreq_lock_by_mali(1200);
	else if (mali_gpu_clk == 440)
		err = cpufreq_lock_by_mali(1000);
#endif
#else
	mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol);
	mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ);
#endif
#else
	mali_clk_set_rate(mali_gpu_clk, GPU_MHZ);
#endif
	MALI_SUCCESS;
}
int mali_dvfs_bottom_lock_push(int lock_step)
{
	int prev_status = _mali_osk_atomic_read(&bottomlock_status);

	if (prev_status < 0) {
		MALI_PRINT(("gpu bottom lock status is not valid for push\n"));
		return -1;
	}
	// not a bad idea to limit locking to 4th step, so let's leave this -gm
	if (samsung_rev() < EXYNOS4412_REV_2_0)
		lock_step = min(lock_step, MALI_DVFS_STEPS - 2);
	else
		lock_step = min(lock_step, MALI_DVFS_STEPS - 1);

	if (bottom_lock_step < lock_step) {
		bottom_lock_step = lock_step;
		if (get_mali_dvfs_status() < lock_step) {
			mali_regulator_set_voltage(mali_dvfs[lock_step].vol,
						   mali_dvfs[lock_step].vol);
			mali_clk_set_rate(mali_dvfs[lock_step].clock,
					  mali_dvfs[lock_step].freq);
			set_mali_dvfs_current_step(lock_step);
		}
	}
	return _mali_osk_atomic_inc_return(&bottomlock_status);
}
Exemplo n.º 6
0
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
{
	u32 validatedStep=step;
	int err;

#ifdef CONFIG_REGULATOR
	if (mali_regulator_get_usecount() == 0) {
		MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n"));
		return MALI_FALSE;
	}
#endif

	if (boostup) {
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
	} else {
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
	}

#ifdef EXYNOS4_ASV_ENABLED
	if (mali_dvfs[step].clock == 160)
		exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V);
	else
		exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V);
#endif


	set_mali_dvfs_current_step(validatedStep);
	/*for future use*/
	maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep];

	/* lock/unlock CPU freq by Mali */
	/* if ((mali_dvfs[step].clock == 533) || (mali_dvfs[step].clock == 440))
		#if defined(CONFIG_EXYNOS4X12_1800MHZ_SUPPORT)
		err = cpufreq_lock_by_mali(1800);
		#elif defined(CONFIG_EXYNOS4X12_1600MHZ_SUPPORT)
		err = cpufreq_lock_by_mali(1600);
		#elif defined(CONFIG_EXYNOS4X12_1500MHZ_SUPPORT)
		err = cpufreq_lock_by_mali(1500);
		#elif defined(CONFIG_EXYNOS4X12_1400MHZ_SUPPORT)
		err = cpufreq_lock_by_mali(1400);
		#else
		err = cpufreq_lock_by_mali(1200);
		#endif
	else
		cpufreq_unlock_by_mali(); */

	return MALI_TRUE;
}
Exemplo n.º 7
0
mali_bool init_mali_dvfs_status(int step)
{
	/*default status
	add here with the right function to get initilization value.
	*/
	if (!mali_dvfs_wq)
		mali_dvfs_wq = create_singlethread_workqueue("mali_dvfs");

	/*add a error handling here*/
	set_mali_dvfs_current_step(step);

	return MALI_TRUE;
}
int mali_dvfs_bottom_lock_push(void)
{
	int prev_status = _mali_osk_atomic_read(&bottomlock_status);

	if (prev_status < 0) {
		MALI_PRINT(("gpu bottom lock status is not valid for push"));
		return -1;
	}

	if (prev_status == 0) {
		mali_regulator_set_voltage(mali_dvfs[1].vol, mali_dvfs[1].vol);
		mali_clk_set_rate(mali_dvfs[1].clock, mali_dvfs[1].freq);
		set_mali_dvfs_current_step(1);
	}

	return _mali_osk_atomic_inc_return(&bottomlock_status);
}
Exemplo n.º 9
0
int mali_dvfs_bottom_lock_push(int lock_step)
{
	int prev_status = _mali_osk_atomic_read(&bottomlock_status);

	if (prev_status < 0) {
		MALI_PRINT(("gpu bottom lock status is not valid for push\n"));
		return -1;
	}
	if (bottom_lock_step < lock_step) {
		bottom_lock_step = lock_step;
		if (get_mali_dvfs_status() < lock_step) {
			mali_regulator_set_voltage(mali_dvfs[lock_step].vol, mali_dvfs[lock_step].vol);
			mali_clk_set_rate(mali_dvfs[lock_step].clock, mali_dvfs[lock_step].freq);
			set_mali_dvfs_current_step(lock_step);
		}
	}
	return _mali_osk_atomic_inc_return(&bottomlock_status);
}
Exemplo n.º 10
0
static _mali_osk_errcode_t enable_mali_clocks(void)
{
	int err;
	err = clk_enable(mali_clock);
	MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err));

	// set clock rate
	 if (get_mali_dvfs_control_status() != 0 || mali_gpu_clk >= mali_runtime_resume.clk)
		mali_clk_set_rate(mali_gpu_clk, GPU_MHZ);
	 else {
		mali_regulator_set_voltage(mali_runtime_resume.vol, mali_runtime_resume.vol);
		mali_clk_set_rate(mali_runtime_resume.clk, GPU_MHZ);
	 }
	 if (mali_gpu_clk <= mali_runtime_resume.clk)
		set_mali_dvfs_current_step(7);

	MALI_SUCCESS;
}
Exemplo n.º 11
0
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
{
	u32 validatedStep=step;
	int err;

#ifdef CONFIG_REGULATOR
	if (mali_regulator_get_usecount() == 0) {
		MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n"));
		return MALI_FALSE;
	}
#endif

	if (boostup) {
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
	} else {
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
	}

	set_mali_dvfs_current_step(validatedStep);
	/*for future use*/
	maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep];

#if CPUFREQ_LOCK_DURING_440
	/* lock/unlock CPU freq by Mali */
	if (mali_dvfs[step].clock >= 533)
		err = cpufreq_lock_by_mali(1200);
	else if (mali_dvfs[step].clock == 440)
		err = cpufreq_lock_by_mali(1000);
	else
		cpufreq_unlock_by_mali();
#endif

	return MALI_TRUE;
}
Exemplo n.º 12
0
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
{
	u32 validatedStep=step;

#ifdef CONFIG_REGULATOR
	if (mali_regulator_get_usecount() == 0) {
		MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n"));
		return MALI_FALSE;
	}
#endif

	if (boostup) {
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
	} else {
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
	}

#ifdef EXYNOS4_ASV_ENABLED
	if (samsung_rev() < EXYNOS4412_REV_2_0) {
		if (mali_dvfs[step].clock == 160)
			exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V);
		else
			exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V);
	}
#endif


	set_mali_dvfs_current_step(validatedStep);
	/*for future use*/
	maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep];

	return MALI_TRUE;
}
Exemplo n.º 13
0
static int mali_devfreq_target(struct device *dev, unsigned long *freq, u32 flags)
{
	unsigned int nextStatus = (unsigned int)*freq;
	unsigned int curStatus = 0;

	curStatus = maliDvfsStatus.currentStep;

	MALI_DEBUG_PRINT(4, ("= curStatus %d, nextStatus %d, maliDvfsStatus.currentStep %d\n", curStatus, nextStatus, maliDvfsStatus.currentStep));

	/*if next status is same with current status, don't change anything*/
	if (curStatus != nextStatus) {
#if MALI_DVFS_CLK_DEBUG
		unsigned int *pRegMaliClkDiv;
		unsigned int *pRegMaliMpll;
#endif
		if (nextStatus > curStatus) {
#ifdef CONFIG_MALI_DVFS
			update_time_in_state(curStatus);
#endif
#ifdef CONFIG_REGULATOR
			/*change the voltage*/
			mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
			exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
			/*change the clock*/
			mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
		} else if (nextStatus < curStatus) {
#ifdef CONFIG_MALI_DVFS
			update_time_in_state(curStatus);
#endif
			/*change the clock*/
			mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
#ifdef CONFIG_REGULATOR
			/*change the voltage*/
			mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
			exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
		} else
			return 0;

#if defined(CONFIG_MALI400_PROFILING)
		_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE|
				MALI_PROFILING_EVENT_CHANNEL_GPU|
				MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
				mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0);
#endif
		mali_clk_put(MALI_FALSE);

#if MALI_DVFS_CLK_DEBUG
		pRegMaliClkDiv = ioremap(0x1003c52c, 32);
		pRegMaliMpll = ioremap(0x1003c22c, 32);
		MALI_PRINT(("Mali MPLL reg:%d, CLK DIV: %d \n", *pRegMaliMpll, *pRegMaliClkDiv));
#endif
		set_mali_dvfs_current_step(nextStatus);
		/*for future use*/
		maliDvfsStatus.pCurrentDvfs = &mali_dvfs[nextStatus];

#if CPUFREQ_LOCK_DURING_440
		/* lock/unlock CPU freq by Mali */
		if (mali_dvfs[nextStatus].clock >= 440)
			cpufreq_lock_by_mali(400);
		else
			cpufreq_unlock_by_mali();
#endif
		/*wait until clock and voltage is stablized*/
		mali_platform_wating(MALI_DVFS_WATING); /*msec*/
	}

	return 0;
}