static void Sync(void) { setmirror(MI_0); setprg32(0x8000,reg & 3); setchr4(0x0000,(reg & 4) | ppulatch); setchr4(0x1000,(reg & 4) | 3); }
static void Sync(void) { for(int x = 0; x < 3; x++) setprg8(0x8000 + x * 8192, PRGBanks[x]); setchr4(0x0000, CHRBanks[0]); setchr4(0x1000, CHRBanks[1]); }
static void MMC5CHRA(void) { int x; switch(mmc5vsize&3) { case 0:setchr8(CHRBanksA[7]); MMC5SPRVROM_BANK8(CHRBanksA[7]); break; case 1:setchr4(0x0000,CHRBanksA[3]); setchr4(0x1000,CHRBanksA[7]); MMC5SPRVROM_BANK4(0x0000,CHRBanksA[3]); MMC5SPRVROM_BANK4(0x1000,CHRBanksA[7]); break; case 2:setchr2(0x0000,CHRBanksA[1]); setchr2(0x0800,CHRBanksA[3]); setchr2(0x1000,CHRBanksA[5]); setchr2(0x1800,CHRBanksA[7]); MMC5SPRVROM_BANK2(0x0000,CHRBanksA[1]); MMC5SPRVROM_BANK2(0x0800,CHRBanksA[3]); MMC5SPRVROM_BANK2(0x1000,CHRBanksA[5]); MMC5SPRVROM_BANK2(0x1800,CHRBanksA[7]); break; case 3: for(x=0;x<8;x++) { setchr1(x<<10,CHRBanksA[x]); MMC5SPRVROM_BANK1(x<<10,CHRBanksA[x]); } break; } }
static void Sync(void) { setprg8(0x8000, regs[0]); setprg8(0xA000, regs[2]); setprg8(0xC000, regs[4]); setprg8(0xE000, ~0); setchr4(0x0000, regs[6]); setchr4(0x1000, regs[7]); }
static void CPROMReset(CartInfo *info) { latche = 0; setprg32(0x8000,0); setchr4(0x0000, 0); setchr4(0x1000, 0); SetReadHandler(0x8000,0xFFFF,CartBR); SetWriteHandler(0x8000,0xffff,CPROMWrite); }
static void Sync(void) { setprg8(0x8000, preg[0]); setprg8(0xA000, preg[1]); setprg8(0xC000, preg[2]); setprg8(0xE000, ~0); setchr4(0x0000, creg[0] | ((mode & 2) << 3)); setchr4(0x1000, creg[1] | ((mode & 4) << 2)); setmirror((mode & 1) ^ 1); }
static void Sync(void) { setprg32(0x8000, 0); if(CHRsize[0] == 8192) { setchr4(0x0000, latche & 1); setchr4(0x1000, latche & 1); } else { setchr8(latche & 1); // actually, my bad, overdumped roms, the real CHR size if 8K } setmirror(MI_0 + (latche & 1)); }
static void CHRSync(void) { if(latches[0] == 0) setchr4(0x0000, CHRBanks[0]); else setchr4(0x0000, CHRBanks[1]); if(latches[1] == 0) setchr4(0x1000, CHRBanks[2]); else setchr4(0x1000, CHRBanks[3]); }
static void Sync(void) { setmirror((mode ^ 1) & 1); setprg8r(0x10, 0x6000, 0); setchr4(0x0000, lastnt); setchr4(0x1000, 1); if (mode & 4) setprg32(0x8000, prg & 7); else { setprg16(0x8000, prg & 0x0f); setprg16(0xC000, 0); } }
static void Sync(void) { if (is10) { setprg8r(0x10, 0x6000, 0); setprg16(0x8000, preg); setprg16(0xC000, ~0); } else { setprg8(0x8000, preg); setprg8(0xA000, ~2); setprg8(0xC000, ~1); setprg8(0xE000, ~0); } setchr4(0x0000, creg[latch0]); setchr4(0x1000, creg[latch1 + 2]); setmirror(mirr); }
static void M163HB(void) { if(DRegs[1]&0x80) { if(scanline==239) { setchr4(0x0000,0); setchr4(0x1000,0); } else if(scanline==127) { setchr4(0x0000,1); setchr4(0x1000,1); } } }
static int CPROM_StateAction(StateMem *sm, int load, int data_only) { SFORMAT StateRegs[] = { SFVAR(latche), SFEND }; int ret = MDFNSS_StateAction(sm, load, data_only, StateRegs, "MAPR"); if(load) setchr4(0x1000, latche & 3); return(ret); }
static void latchcheck(uint32 VAddr) { uint8 l,h; h=VAddr>>8; if(h>=0x20 || ((h&0xF)!=0xF)) return; l=VAddr&0xF8; if(h<0x10) { if(l==0xD8) { setchr4(0x0000, CHRBanks[0]); latches[0] = 0; } else if(l==0xE8) { setchr4(0x0000, CHRBanks[1]); latches[0] = 1; } } else { if(l==0xD8) { setchr4(0x1000, CHRBanks[2]); latches[1] = 0; } else if(l==0xE8) { setchr4(0x1000, CHRBanks[3]); latches[1] = 1; } } }
static void tekvrom(void) { int x; switch(tkcom[0]&0x18) { case 0x00: // 8KB setchr8(chrlow[0]|(chrhigh[0]<<8)); break; case 0x08: // 4KB for(x=0;x<8;x+=4) setchr4(x<<10,chrlow[x]|(chrhigh[x]<<8)); break; case 0x10: // 2KB for(x=0;x<8;x+=2) setchr2(x<<10,chrlow[x]|(chrhigh[x]<<8)); break; case 0x18: // 1KB for(x=0;x<8;x++) setchr1(x<<10,(chrlow[x]|(chrhigh[x]<<8))); break; } }
static void Sync(void) { setprg8r(0x10, 0x6000, 0); setprg32(0x8000, regs[0]); setchr4(0x0000, regs[1]); setchr4(0x1000, regs[2]); }
static void UNLAX5705IRQ(void) { if(scanline > 174) setchr4(0x0000,1); else setchr4(0x0000,0); }
static DECLFW(CPROMWrite) { latche=V&3; setchr4(0x1000, V & 3); }
static void Sync(void) { setprg32(0x8000, PRGBank32); setchr4(0x0000, CHRBanks[0]); setchr4(0x1000, CHRBanks[1]); }