static void prelabel(Node p) {
if (p == NULL)
return;
prelabel(p->kids[0]);
prelabel(p->kids[1]);
if (NeedsReg[opindex(p->op)])
setreg(p, (*IR->x.rmap)(opkind(p->op)));
switch (generic(p->op)) {
case ADDRF: case ADDRL:
if (p->syms[0]->sclass == REGISTER)
p->op = VREG+P;
break;
case INDIR:
if (p->kids[0]->op == VREG+P)
setreg(p, p->kids[0]->syms[0]);
break;
case ASGN:
if (p->kids[0]->op == VREG+P)
rtarget(p, 1, p->kids[0]->syms[0]);
break;
case CVI: case CVU: case CVP:
if (optype(p->op) != F
&& opsize(p->op) <= p->syms[0]->u.c.v.i)
p->op = LOAD + opkind(p->op);
break;
}
(IR->x.target)(p);
}
static void
omap_set_lcd_mode(int w, int h)
{
uint32 DISPC = DISPC_BASE;
unsigned int i;
struct video_mode *m;
dprintf("omap3: set_lcd_mode %d,%d\n", w, h);
for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) {
if (w <= modes[i].width
&& h <= modes[i].height)
goto found;
}
i -= 1;
found:
m = &modes[i];
dprintf("omap3: found mode[%s]\n", m->name);
setreg(DISPC, DISPC_SIZE_LCD, (m->width - 1) | ((m->height - 1) << 16));
setreg(DISPC, DISPC_TIMING_H, m->dispc_timing_h);
setreg(DISPC, DISPC_TIMING_V, m->dispc_timing_v);
modreg(DISPC, DISPC_DIVISOR, 0xffff, m->dispc_divisor);
modaddr(CM_CLKSEL_DSS, 0xffff, m->dss_divisor);
// Tell hardware to update, and wait for it
modreg(DISPC, DISPC_CONTROL,
DISPC_GOLCD,
DISPC_GOLCD);
while ((readreg(DISPC, DISPC_CONTROL) & DISPC_GOLCD))
;
}
//set the MOV
void MOV::set(int type1, intptr_t val1, int type2, intptr_t val2) {
//MOV-exclusive specials
if (val1 == EAX && isreg(type1) && type2 == ptrfromreg(type1)) {
MEMPTR* memptr = (MEMPTR*)(val2);
if (memptr->reg1 == -1) {
if (type1 == TREG32)
bytes.assign("\xA1").append(to4bytes(memptr->constant));
else if (type1 == TREG16)
bytes.assign("\x66\xA1").append(to4bytes(memptr->constant));
else if (type1 == TREG8)
bytes.assign("\xA0").append(to4bytes(memptr->constant));
if (memptr->deletable)
delete memptr;
return;
}
} else if (val2 == EAX && isreg(type2) && type1 == ptrfromreg(type2)) {
MEMPTR* memptr = (MEMPTR*)(val1);
if (memptr->reg1 == -1) {
if (type2 == TREG32)
bytes.assign("\xA3").append(to4bytes(memptr->constant));
else if (type2 == TREG16)
bytes.assign("\x66\xA3").append(to4bytes(memptr->constant));
else if (type2 == TREG8)
bytes.assign("\xA2").append(to4bytes(memptr->constant));
if (memptr->deletable)
delete memptr;
return;
}
}
//move data addresses
if (type2 == TDATAADDRESS) {
set(type1, val1, TCONSTANT, IMAGEBASE);
tag = TAGOPXDATAADDRESS;
tag2 = val2;
tag3 = type1;
tag4 = val1;
//move code addresses
} else if (type2 == TCODEADDRESS) {
set(type1, val1, TCONSTANT, IMAGEBASE);
tag = TAGOPXCODEADDRESS;
tagp = val2;
tag3 = type1;
tag4 = val1;
//regular setting
} else if (type1 == TREG32)
setreg(type1, val1, type2, val2, "", "", 0xB8, "", "\x8B");
else if (type1 == TREG16)
setreg(type1, val1, type2, val2, "", "\x66", 0xB8, "", "\x66\x8B");
else if (type1 == TREG8)
setreg(type1, val1, type2, val2, "", "", 0xB0, "", "\x8A");
else if (type1 == TDWORDPTR)
setptr(type1, val1, type2, val2, "\x89", "", "\xC7", 0);
else if (type1 == TWORDPTR)
setptr(type1, val1, type2, val2, "\x66\x89", "", "\x66\xC7", 0);
else if (type1 == TBYTEPTR)
setptr(type1, val1, type2, val2, "\x88", "\xC6", "", 0);
else if (isdataptr(type1))
setdataptr(type1, val1, type2, val2);
}
static void
omap_dss_init(void)
{
setreg(DSS_BASE, DSS_SYSCONFIG, DSS_AUTOIDLE);
// Select DSS1 ALWON as clock source
setreg(DSS_BASE, DSS_CONTROL, DSS_VENC_OUT_SEL | DSS_DAC_POWERDN_BGZ
| DSS_DAC_DEMEN | DSS_VENC_CLOCK_4X_ENABLE);
}
// init beagle gpio for video
static void
omap_beagle_init(void)
{
// setup GPIO stuff, i can't find any references to these
setreg(GPIO1_BASE, GPIO_OE, 0xfefffedf);
setreg(GPIO1_BASE, GPIO_SETDATAOUT, 0x01000120);
// DVI-D is enabled by GPIO 170?
}
static int tvoutc_setclk(int mode)
{
const reg_t *sd,*hd;
int xtal;
if(used_audio_pll==-1)
used_audio_pll=(system_serial_low==0xA)?1:0;
if(used_audio_pll)
{
printf("TEST:used audio pll for video out for test!!\n");
sd=tvreg_aclk_sd;
hd=tvreg_aclk_hd;
}
else
{
printf("used Video pll for video out!!\n");
sd=tvreg_vclk_sd;
hd=tvreg_vclk_hd;
}
xtal=get_xtal_clock();
xtal=xtal/1000000;
if(xtal>=24 && xtal <=25)/*current only support 24,25*/
{
xtal-=24;
}
else
{
printf("UNsupport xtal setting for vidoe xtal=%d,default to 24M\n",xtal);
xtal=0;
}
switch(mode)
{
case TVOUT_480I:
case TVOUT_480CVBS:
case TVOUT_480P:
case TVOUT_576I:
case TVOUT_576CVBS:
case TVOUT_576P:
setreg(&sd[xtal]);
//clk_set_rate(clk,540);
break;
case TVOUT_720P:
case TVOUT_1080I:
case TVOUT_1080P:
setreg(&hd[xtal]);
if(xtal == 1)
{
WRITE_MPEG_REG(HHI_VID_CLK_DIV, 4);
}
// clk_set_rate(clk,297);
break;
default:
printf("unsupport tv mode,video clk is not set!!\n");
}
return 0;
}
int tvoutc_setclk(tvmode_t mode)
{
struct clk *clk;
const reg_t *sd,*hd;
int xtal;
sd=tvreg_vclk_sd;
hd=tvreg_vclk_hd;
clk=clk_get_sys("clk_xtal", NULL);
if(!clk)
{
printk(KERN_ERR "can't find clk %s for VIDEO PLL SETTING!\n\n","clk_xtal");
return -1;
}
xtal=clk_get_rate(clk);
xtal=xtal/1000000;
if(xtal>=24 && xtal <=25)/*current only support 24,25*/
{
xtal-=24;
}
else
{
printk(KERN_WARNING "UNsupport xtal setting for vidoe xtal=%d,default to 24M\n",xtal);
xtal=0;
}
switch(mode)
{
case TVMODE_480I:
case TVMODE_480I_RPT:
case TVMODE_480CVBS:
case TVMODE_480P:
case TVMODE_480P_RPT:
case TVMODE_576I:
case TVMODE_576I_RPT:
case TVMODE_576CVBS:
case TVMODE_576P:
setreg(&sd[xtal]);
break;
case TVMODE_720P:
case TVMODE_720P_50HZ:
case TVMODE_1080I:
case TVMODE_1080I_50HZ:
case TVMODE_1080P:
case TVMODE_1080P_50HZ:
setreg(&hd[xtal]);
if(xtal == 1)
{
WRITE_MPEG_REG(HHI_VID_CLK_DIV, 4);
}
break;
default:
//printk(KERN_ERR "unsupport tv mode,video clk is not set!!\n");
break;
}
return 0 ;
}
static void
tcpip_handler(void)
{
/*
char *str;
uip_ipaddr_t tadd;
printf("In tcphandler\n");
if(uip_newdata()) {
str = uip_appdata;
str[uip_datalen()] = '\0';
printf("DATA recv '%s'\n", str);
//uip_ip6addr(&tadd, 0xaaaa, 0, 0, 0, 0x0212, 0x7402, 0x0002, 0x0202);
//uip_udp_packet_sendto(client_conn, "from client ", sizeof("from client "), &tadd, UIP_HTONS(12345));
}
*/
uint8_t *appdata=NULL,a;int code=0;
if(uip_newdata()) {
appdata = (uint8_t *) uip_appdata;
MAPPER_GET_PACKETDATA(code,appdata);
switch(code)
{
case 1://helping packet
printf("Helper message \n");
help(appdata);
break;
case 2://adding neighbor info and ranks
forward_packet(appdata);
break;
case 3://victim packet
printf("I am Victim\n");
monitoring(appdata);
break;
case 4://monitoring node
break;
case 5://Selent packet
//upade_info(appdata);
break;
case 7://Nbr info req
snd_nbr_info();
break;
case 8://nbr_info process
if(!attacker_set)
select_attacker(appdata);
break;
case 9://Wormhole deactive
MAPPER_GET_PACKETDATA(code,appdata);
if(code==2)
{printf("Attacker 2\n");attack_flag=1;attacker=2;setreg(17,0);}
if(code==3)
{printf("Attacker 3\n");attack_flag=1;attacker=3;dis_output(NULL);setreg(17,0);}
break;
}
}
}
/*---------------------------------------------------------------------------*/
int
cc2420_init(void)
{
uint16_t reg;
{
int s = splhigh();
cc2420_arch_init(); /* Initalize ports and SPI. */
DISABLE_FIFOP_INT();
FIFOP_INT_INIT();
splx(s);
}
/* Turn on voltage regulator and reset. */
SET_VREG_ACTIVE();
//clock_delay(250); OK
SET_RESET_ACTIVE();
clock_delay(127);
SET_RESET_INACTIVE();
//clock_delay(125); OK
/* Turn on the crystal oscillator. */
strobe(CC2420_SXOSCON);
/* Turn on/off automatic packet acknowledgment and address decoding. */
reg = getreg(CC2420_MDMCTRL0);
reg |= 0x40; /* XXX CCA mode 1 */
#if CC2420_CONF_AUTOACK
reg |= AUTOACK | ADR_DECODE;
#else
reg &= ~(AUTOACK | ADR_DECODE);
#endif /* CC2420_CONF_AUTOACK */
setreg(CC2420_MDMCTRL0, reg);
/* Change default values as recomended in the data sheet, */
/* correlation threshold = 20, RX bandpass filter = 1.3uA. */
setreg(CC2420_MDMCTRL1, CORR_THR(20));
reg = getreg(CC2420_RXCTRL1);
reg |= RXBPF_LOCUR;
setreg(CC2420_RXCTRL1, reg);
/* Set the FIFOP threshold to maximum. */
setreg(CC2420_IOCFG0, FIFOP_THR(127));
/* Turn off "Security enable" (page 32). */
reg = getreg(CC2420_SECCTRL0);
reg &= ~RXFIFO_PROTECTION;
setreg(CC2420_SECCTRL0, reg);
cc2420_set_pan_addr(0xffff, 0x0000, NULL);
cc2420_set_channel(26);
process_start(&cc2420_process, NULL);
return 1;
}
int roach_late_iic_init(void)
{
if (!(roach_late_iic_base = ioremap64(EPX_IIC0_BASE, 0x100))){
return -1;
}
setreg(IIC0_INTRMSK, 0);
setreg(IIC0_MDCTRL, 0);
return 0;
}
static void
omap_attach_framebuffer(addr_t data, int width, int height, int depth)
{
uint32 DISPC = DISPC_BASE;
uint32 gsize = ((height - 1) << 16) | (width - 1);
dprintf("omap3: attach bitmap (%d,%d) to screen\n", width, height);
setreg(DISPC, DISPC_GFX_BA0, (uint32)data);
setreg(DISPC, DISPC_GFX_BA1, (uint32)data);
setreg(DISPC, DISPC_GFX_POSITION, 0);
setreg(DISPC, DISPC_GFX_SIZE, gsize);
setreg(DISPC, DISPC_GFX_FIFO_THRESHOLD, (0x3ff << 16) | 0x3c0);
setreg(DISPC, DISPC_GFX_ROW_INC, 1);
setreg(DISPC, DISPC_GFX_PIXEL_INC, 1);
setreg(DISPC, DISPC_GFX_WINDOW_SKIP, 0);
setreg(DISPC, DISPC_GFX_ATTRIBUTES, DISPC_GFXFORMAT_RGB16
| DISPC_GFXBURSTSIZE_16x32 | DISPC_GFXENABLE);
// Tell hardware to update, and wait for it
modreg(DISPC, DISPC_CONTROL, DISPC_GOLCD, DISPC_GOLCD);
while ((readreg(DISPC, DISPC_CONTROL) & DISPC_GOLCD))
;
}
//set the MOVSX
void MOVSX::set(int type1, intptr_t val1, int type2, intptr_t val2) {
if (type1 == TREG32) {
if (type2 == TREG16 || type2 == TWORDPTR)
setreg(type1, val1, type2, val2, "", "", 0, "", "\x0F\xBF");
else if (type2 == TREG8 || type2 == TBYTEPTR)
setreg(type1, val1, type2, val2, "", "", 0, "", "\x0F\xBE");
} else if (type1 == TREG16) {
if (type2 == TREG8 || type2 == TBYTEPTR)
setreg(type1, val1, type2, val2, "", "", 0, "", "\x66\x0F\xBE");
}
}
status_t
ArchFBArmOmap3::Init()
{
gKernelArgs.frame_buffer.enabled = true;
setreg(DISPC_BASE, DISPC_IRQENABLE, 0x00000);
setreg(DISPC_BASE, DISPC_IRQSTATUS, 0x1ffff);
omap_beagle_init();
omap_clock_init();
omap_dss_init();
omap_dispc_init();
return B_OK;
}
static int
lm78rdreg(int reg)
{
uchar val;
if(waserror()){
qunlock(&lm78);
nexterror();
}
qlock(&lm78);
switch(lm78.ifc){
case Smbus:
lm78.smbus->transact(lm78.smbus, SMBsend, Serialaddr, reg, nil);
lm78.smbus->transact(lm78.smbus, SMBrecv, Serialaddr, 0, &val);
break;
case Parallel:
setreg(reg);
val = inb(lm78.port+Rpdata);
break;
default:
error(Enodev);
break;
}
qunlock(&lm78);
poperror();
return val;
}
//set the CMP
void CMP::set(int type1, intptr_t val1, int type2, intptr_t val2) {
if (type1 == TREG32)
setreg(type1, val1, type2, val2, "\x83", "\x81", 0xF8, "\x3D", "\x3B");
else if (type1 == TREG16)
setreg(type1, val1, type2, val2, "\x66\x83", "\x66\x81", 0xF8, "\x66\x3D", "\x66\x3B");
else if (type1 == TREG8)
setreg(type1, val1, type2, val2, "\x80", "", 0xF8, "\x3C", "\x3A");
else if (type1 == TDWORDPTR)
setptr(type1, val1, type2, val2, "\x39", "\x83", "\x81", 0x38);
else if (type1 == TWORDPTR)
setptr(type1, val1, type2, val2, "\x66\x39", "\x66\x83", "\x66\x81", 0x38);
else if (type1 == TBYTEPTR)
setptr(type1, val1, type2, val2, "\x38", "\x80", "", 0x38);
else if (isdataptr(type1))
setdataptr(type1, val1, type2, val2);
}
//set the OR
void OR::set(int type1, intptr_t val1, int type2, intptr_t val2) {
if (type1 == TREG32)
setreg(type1, val1, type2, val2, "\x83", "\x81", 0xC8, "\x0D", "\x0B");
else if (type1 == TREG16)
setreg(type1, val1, type2, val2, "\x66\x83", "\x66\x81", 0xC8, "\x66\x0D", "\x66\x0B");
else if (type1 == TREG8)
setreg(type1, val1, type2, val2, "\x80", "", 0xC8, "\x0C", "\x0A");
else if (type1 == TDWORDPTR)
setptr(type1, val1, type2, val2, "\x09", "\x83", "\x81", 8);
else if (type1 == TWORDPTR)
setptr(type1, val1, type2, val2, "\x66\x09", "\x66\x83", "\x66\x81", 8);
else if (type1 == TBYTEPTR)
setptr(type1, val1, type2, val2, "\x08", "\x80", "", 8);
else if (isdataptr(type1))
setdataptr(type1, val1, type2, val2);
}
//set the AND
void AND::set(int type1, intptr_t val1, int type2, intptr_t val2) {
if (type1 == TREG32)
setreg(type1, val1, type2, val2, "\x83", "\x81", 0xE0, "\x25", "\x23");
else if (type1 == TREG16)
setreg(type1, val1, type2, val2, "\x66\x83", "\x66\x81", 0xE0, "\x66\x25", "\x66\x23");
else if (type1 == TREG8)
setreg(type1, val1, type2, val2, "\x80", "", 0xE0, "\x24", "\x22");
else if (type1 == TDWORDPTR)
setptr(type1, val1, type2, val2, "\x21", "\x83", "\x81", 0x20);
else if (type1 == TWORDPTR)
setptr(type1, val1, type2, val2, "\x66\x21", "\x66\x83", "\x66\x81", 0x20);
else if (type1 == TBYTEPTR)
setptr(type1, val1, type2, val2, "\x20", "\x80", "", 0x20);
else if (isdataptr(type1))
setdataptr(type1, val1, type2, val2);
}
int tv_out_open(int mode)
{
const reg_t *s;
if (TVOUT_VALID(mode))
{
tvmode = mode;
s = tvregsTab[mode];
while (MREG_END_MARKER != s->reg)
setreg(s++);
chip_version_init();
tvoutc_setclk(mode);
enable_vsync_interrupt();
WRITE_MPEG_REG(VPP_POSTBLEND_H_SIZE, tvinfoTab[mode].xres);
change_vdac_setting(0x120120, mode);
set_disp_mode_auto(mode );
return 0;
}
return -1;
}
//set the SUB
void SUB::set(int type1, intptr_t val1, int type2, intptr_t val2) {
if (type1 == TREG32)
setreg(type1, val1, type2, val2, "\x83", "\x81", 0xE8, "\x2D", "\x2B");
else if (type1 == TREG16)
setreg(type1, val1, type2, val2, "\x66\x83", "\x66\x81", 0xE8, "\x66\x2D", "\x66\x2B");
else if (type1 == TREG8)
setreg(type1, val1, type2, val2, "\x80", "", 0xE8, "\x2C", "\x2A");
else if (type1 == TDWORDPTR)
setptr(type1, val1, type2, val2, "\x29", "\x83", "\x81", 0x28);
else if (type1 == TWORDPTR)
setptr(type1, val1, type2, val2, "\x66\x29", "\x66\x83", "\x66\x81", 0x28);
else if (type1 == TBYTEPTR)
setptr(type1, val1, type2, val2, "\x28", "\x80", "", 0x28);
else if (isdataptr(type1))
setdataptr(type1, val1, type2, val2);
}
//set the ADD
void ADD::set(int type1, intptr_t val1, int type2, intptr_t val2) {
if (type1 == TREG32)
setreg(type1, val1, type2, val2, "\x83", "\x81", 0xC0, "\x05", "\x03");
else if (type1 == TREG16)
setreg(type1, val1, type2, val2, "\x66\x83", "\x66\x81", 0xC0, "\x66\x05", "\x66\x03");
else if (type1 == TREG8)
setreg(type1, val1, type2, val2, "\x80", "", 0xC0, "\x04", "\x02");
else if (type1 == TDWORDPTR)
setptr(type1, val1, type2, val2, "\x01", "\x83", "\x81", 0);
else if (type1 == TWORDPTR)
setptr(type1, val1, type2, val2, "\x66\x01", "\x66\x83", "\x66\x81", 0);
else if (type1 == TBYTEPTR)
setptr(type1, val1, type2, val2, string("\0", 1), "\x80", "", 0);
else if (isdataptr(type1))
setdataptr(type1, val1, type2, val2);
}
/* routines that actually touch the device */
static void
lm78wrreg(int reg, uchar val)
{
if(waserror()){
qunlock(&lm78);
nexterror();
}
qlock(&lm78);
switch(lm78.ifc){
case Smbus:
lm78.smbus->transact(lm78.smbus, SMBbytewrite, Serialaddr, reg, &val);
break;
case Parallel:
setreg(reg);
outb(lm78.port+Rpdata, val);
break;
default:
error(Enodev);
break;
}
qunlock(&lm78);
poperror();
}
//set the XOR
void XOR::set(int type1, intptr_t val1, int type2, intptr_t val2) {
if (type1 == TREG32)
setreg(type1, val1, type2, val2, "\x83", "\x81", 0xF0, "\x35", "\x33");
else if (type1 == TREG16)
setreg(type1, val1, type2, val2, "\x66\x83", "\x66\x81", 0xF0, "\x66\x35", "\x66\x33");
else if (type1 == TREG8)
setreg(type1, val1, type2, val2, "\x80", "", 0xF0, "\x34", "\x32");
else if (type1 == TDWORDPTR)
setptr(type1, val1, type2, val2, "\x31", "\x83", "\x81", 0x30);
else if (type1 == TWORDPTR)
setptr(type1, val1, type2, val2, "\x66\x31", "\x66\x83", "\x66\x81", 0x30);
else if (type1 == TBYTEPTR)
setptr(type1, val1, type2, val2, "\x30", "\x80", "", 0x30);
else if (isdataptr(type1))
setdataptr(type1, val1, type2, val2);
}
/*---------------------------------------------------------------------------*/
void
cc2520_set_cca_threshold(int value)
{
GET_LOCK();
setreg(CC2520_CCACTRL0, value & 0xff);
RELEASE_LOCK();
}
/*---------------------------------------------------------------------------*/
int
cc2520_set_channel(int c)
{
uint16_t f;
GET_LOCK();
/*
* Subtract the base channel (11), multiply by 5, which is the
* channel spacing. 357 is 2405-2048 and 0x4000 is LOCK_THR = 1.
*/
channel = c;
f = MIN_CHANNEL + ((channel - MIN_CHANNEL) * CHANNEL_SPACING);
/*
* Writing RAM requires crystal oscillator to be stable.
*/
BUSYWAIT_UNTIL((status() & (BV(CC2520_XOSC16M_STABLE))), RTIMER_SECOND / 10);
/* Wait for any transmission to end. */
BUSYWAIT_UNTIL(!(status() & BV(CC2520_TX_ACTIVE)), RTIMER_SECOND / 10);
/* Define radio channel (between 11 and 25) */
setreg(CC2520_FREQCTRL, f);
/* If we are in receive mode, we issue an SRXON command to ensure
that the VCO is calibrated. */
if(receive_on) {
strobe(CC2520_INS_SRXON);
}
RELEASE_LOCK();
return 1;
}
/*---------------------------------------------------------------------------*/
int
cc2420_set_channel(int c)
{
uint16_t f;
GET_LOCK();
/*
* Subtract the base channel (11), multiply by 5, which is the
* channel spacing. 357 is 2405-2048 and 0x4000 is LOCK_THR = 1.
*/
channel = c;
f = 5 * (c - 11) + 357 + 0x4000;
/*
* Writing RAM requires crystal oscillator to be stable.
*/
BUSYWAIT_UNTIL((status() & (BV(CC2420_XOSC16M_STABLE))), RTIMER_SECOND / 10);
/* Wait for any transmission to end. */
BUSYWAIT_UNTIL(!(status() & BV(CC2420_TX_ACTIVE)), RTIMER_SECOND / 10);
setreg(CC2420_FSCTRL, f);
/* If we are in receive mode, we issue an SRXON command to ensure
that the VCO is calibrated. */
if(receive_on) {
strobe(CC2420_SRXON);
}
RELEASE_LOCK();
return 1;
}
int main()
{
int file;
int adapter_nr = 0;
char filename[20];
snprintf(filename, 19, "/dev/i2c-%d", adapter_nr);
file = open(filename, O_RDWR);
if (file < 0)
{
printf("cannot open filen\n");
exit(1);
}
printf("file opened\n");
int addr = 0x20;
if(ioctl(file, I2C_SLAVE, addr) < 0)
{
printf("cannot find slave device address 0x%x\n", addr);
exit(1);
}
setreg(file, 3,0xF0);
setreg(file, 2,0x00);
int i;
__u8 val = 1;
while(1)
{
setreg(file, 1,(~val)&0xFF);
sleep(1);
val<<=1;
if(val==0x10)
val = 1;
int k = getreg(file,0);
if((k&0x10) == 0)
break;
}
printf("reg%d=0x%x\n", 0, getreg(file, 0));
close(file);
}
/*
* pop -- pop a word off the given stack
*
* sp -- stack pointer register to use. Can be any of the eight
* general purpose registers.
* return value -- the word popped off the stack
*/
static size_t pop(size_t sp)
{
size_t word;
word = getmem(getreg(sp));
setreg(sp, getreg(sp)-1);
return(word);
}
int main(int argc, char *argv[])
{
if (argc >= 3) {
if ( 0 == strcmp("red",argv[1]) ) {
setreg(ledctl_red,0);
setreg(leddata_red,strcmp("off",argv[2])?1:0);
}
else {
setreg(ledctl_green,0);
setreg(leddata_green,strcmp("off",argv[2])?1:0);
}
} else {
printusage();
return -1;
}
return 0;
}
/*---------------------------------------------------------------------------*/
void
cc2420_set_cca_threshold(int value)
{
uint16_t shifted = value << 8;
GET_LOCK();
setreg(CC2420_RSSI, shifted);
RELEASE_LOCK();
}
/*---------------------------------------------------------------------------*/
static void
set_txpower(uint8_t power)
{
uint16_t reg;
reg = getreg(CC2420_TXCTRL);
reg = (reg & 0xffe0) | (power & 0x1f);
setreg(CC2420_TXCTRL, reg);
}
