void initClocks(void)
{
// PLL setup
setupPLL();
feedSeq();
connectPLL();
feedSeq();
//VPBDIV = 0x01; -already set
//////
}
void systemInit(void)
{
/* USER CODE BEGIN (15) */
/* USER CODE END */
/* Configure PLL control registers and enable PLLs.
* The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
* This initialization sequence performs all the tasks that are not
* required to be done at full application speed while the PLL locks.
*/
setupPLL();
/* USER CODE BEGIN (16) */
/* USER CODE END */
/* Enable clocks to peripherals and release peripheral reset */
periphInit();
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Configure device-level multiplexing and I/O multiplexing */
muxInit();
/* USER CODE BEGIN (18) */
/* USER CODE END */
/** - Set up flash address and data wait states based on the target CPU clock frequency
* The number of address and data wait states for the target CPU clock frequency are specified
* in the specific part's datasheet.
*/
setupFlash();
/* USER CODE BEGIN (19) */
/* USER CODE END */
/** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
trimLPO();
/* USER CODE BEGIN (20) */
/* USER CODE END */
/** - Wait for PLLs to start up and map clock domains to desired clock sources */
mapClocks();
/* USER CODE BEGIN (21) */
/* USER CODE END */
/** - set ECLK pins functional mode */
systemREG1->SYSPC1 = 0U;
/** - set ECLK pins default output value */
systemREG1->SYSPC4 = 0U;
/** - set ECLK pins output direction */
systemREG1->SYSPC2 = 1U;
/** - set ECLK pins open drain enable */
systemREG1->SYSPC7 = 0U;
/** - set ECLK pins pullup/pulldown enable */
systemREG1->SYSPC8 = 0U;
/** - set ECLK pins pullup/pulldown select */
systemREG1->SYSPC9 = 1U;
/** - Setup ECLK */
systemREG1->ECPCNTL = (uint32)((uint32)0U << 24U)
| (uint32)((uint32)0U << 23U)
| (uint32)((uint32)(8U - 1U) & 0xFFFFU);
/* USER CODE BEGIN (22) */
/* USER CODE END */
}
/* Requirements : HL_SR471 */
void systemInit(void)
{
uint32 efcCheckStatus;
/* USER CODE BEGIN (15) */
/* USER CODE END */
/* Configure PLL control registers and enable PLLs.
* The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
* This initialization sequence performs all the tasks that are not
* required to be done at full application speed while the PLL locks.
*/
setupPLL();
/* USER CODE BEGIN (16) */
/* USER CODE END */
/* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
* This includes a check for the eFuse controller error outputs to be stuck-at-zero.
*/
efcCheckStatus = efcCheck();
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Enable clocks to peripherals and release peripheral reset */
periphInit();
/* USER CODE BEGIN (18) */
/* USER CODE END */
/* Configure device-level multiplexing and I/O multiplexing */
muxInit();
/* USER CODE BEGIN (19) */
/* USER CODE END */
if(efcCheckStatus == 0U)
{
/* Wait for eFuse controller self-test to complete and check results */
if (checkefcSelfTest() == FALSE) /* eFuse controller ECC logic self-test failed */
{
selftestFailNotification(EFCCHECK_FAIL1); /* device operation is not reliable */
}
}
else if(efcCheckStatus == 2U)
{
/* Wait for eFuse controller self-test to complete and check results */
if (checkefcSelfTest() == FALSE) /* eFuse controller ECC logic self-test failed */
{
selftestFailNotification(EFCCHECK_FAIL1); /* device operation is not reliable */
}
else
{
selftestFailNotification(EFCCHECK_FAIL2);
}
}
else
{
/* Empty */
}
/* USER CODE BEGIN (20) */
/* USER CODE END */
/** - Set up flash address and data wait states based on the target CPU clock frequency
* The number of address and data wait states for the target CPU clock frequency are specified
* in the specific part's datasheet.
*/
setupFlash();
/* USER CODE BEGIN (21) */
/* USER CODE END */
/** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
trimLPO();
/* USER CODE BEGIN (23) */
/* USER CODE END */
/** - Wait for PLLs to start up and map clock domains to desired clock sources */
mapClocks();
/* USER CODE BEGIN (24) */
/* USER CODE END */
/** - set ECLK pins functional mode */
systemREG1->SYSPC1 = 0U;
/** - set ECLK pins default output value */
systemREG1->SYSPC4 = 0U;
/** - set ECLK pins output direction */
systemREG1->SYSPC2 = 1U;
/** - set ECLK pins open drain enable */
systemREG1->SYSPC7 = 0U;
/** - set ECLK pins pullup/pulldown enable */
systemREG1->SYSPC8 = 0U;
/** - set ECLK pins pullup/pulldown select */
systemREG1->SYSPC9 = 1U;
/** - Setup ECLK */
systemREG1->ECPCNTL = (uint32)((uint32)0U << 24U)
| (uint32)((uint32)0U << 23U)
| (uint32)((uint32)(8U - 1U) & 0xFFFFU);
/* USER CODE BEGIN (25) */
/* USER CODE END */
}