int
is_condition_ok (SIM_DESC sd,
address_word cia,
int cond)
{
switch (cond)
{
case 0x0:
return 1;
case 0x1:
return PSW_VAL(PSW_F0);
case 0x2:
return !PSW_VAL(PSW_F0);
case 0x3:
return PSW_VAL(PSW_F1);
case 0x4:
return !PSW_VAL(PSW_F1);
case 0x5:
return PSW_VAL(PSW_F0) && PSW_VAL(PSW_F1);
case 0x6:
return PSW_VAL(PSW_F0) && !PSW_VAL(PSW_F1);
case 0x7:
sim_engine_abort (sd, STATE_CPU (sd, 0), cia,
"is_condition_ok - bad instruction condition bits");
return 0;
default:
sim_engine_abort (sd, STATE_CPU (sd, 0), cia,
"internal error - is_condition_ok - bad switch");
return -1;
}
}
void
mn10300_core_signal (SIM_DESC sd,
sim_cpu *cpu,
sim_cia cia,
unsigned map,
int nr_bytes,
address_word addr,
transfer_type transfer,
sim_core_signals sig)
{
const char *copy = (transfer == read_transfer ? "read" : "write");
address_word ip = CIA_ADDR (cia);
switch (sig)
{
case sim_core_unmapped_signal:
sim_io_eprintf (sd, "mn10300-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
nr_bytes, copy,
(unsigned long) addr, (unsigned long) ip);
program_interrupt(sd, cpu, cia, SIM_SIGSEGV);
break;
case sim_core_unaligned_signal:
sim_io_eprintf (sd, "mn10300-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
nr_bytes, copy,
(unsigned long) addr, (unsigned long) ip);
program_interrupt(sd, cpu, cia, SIM_SIGBUS);
break;
default:
sim_engine_abort (sd, cpu, cia,
"mn10300_core_signal - internal error - bad switch");
}
}
/* Determine the correct FQ register to use for the given exception.
Return -1 if a register is not available. */
static int
fq_for_exception (
SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
)
{
SI fq;
struct frv_fp_exception_info *fp_info = & item->u.fp_info;
/* For fp_exception overflow, underflow or inexact, use FQ0 or FQ1. */
if (fp_info->ftt == FTT_IEEE_754_EXCEPTION
&& (fp_info->fsr_mask & (FSR_OVERFLOW | FSR_UNDERFLOW | FSR_INEXACT)))
{
fq = GET_FQ (0);
if (! GET_FQ_VALID (fq))
return 0; /* FQ0 is available. */
fq = GET_FQ (1);
if (! GET_FQ_VALID (fq))
return 1; /* FQ1 is available. */
/* No FQ register is available */
{
SIM_DESC sd = CPU_STATE (current_cpu);
IADDR pc = CPU_PC_GET (current_cpu);
sim_engine_abort (sd, current_cpu, pc, "No FQ register available\n");
}
return -1;
}
/* For other exceptions, use FQ2 if the insn was in slot F0/I0 and FQ3
otherwise. */
if (item->slot == UNIT_FM0 || item->slot == UNIT_I0)
return 2;
return 3;
}
address_word
micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu,
address_word cia,
int instruction_size)
{
if (instruction_size == MICROMIPS_DELAYSLOT_SIZE_ANY)
{
micromips16_instruction_word instruction_0 = IMEM16_MICROMIPS (cia);
if (MICROMIPS_MINOR_OPCODE (instruction_0) > 0
&& MICROMIPS_MINOR_OPCODE (instruction_0) < 4)
return micromips16_idecode_issue (sd, instruction_0, cia);
else
{
micromips32_instruction_word instruction_0 = IMEM32_MICROMIPS (cia);
return micromips32_idecode_issue (sd, instruction_0, cia);
}
}
else if (instruction_size == MICROMIPS_DELAYSLOT_SIZE_16)
{
micromips16_instruction_word instruction_0 = IMEM16_MICROMIPS (cia);
if (MICROMIPS_MINOR_OPCODE (instruction_0) > 0
&& MICROMIPS_MINOR_OPCODE (instruction_0) < 4)
return micromips16_idecode_issue (sd, instruction_0, cia);
else
sim_engine_abort (sd, cpu, cia,
"Invalid 16 bit micromips instruction");
}
else if (instruction_size == MICROMIPS_DELAYSLOT_SIZE_32)
{
micromips32_instruction_word instruction_0 = IMEM32_MICROMIPS (cia);
return micromips32_idecode_issue (sd, instruction_0, cia);
}
else
return NULL_CIA;
}
void
sim_cpu_hw_io_write_buffer (sim_cpu *cpu,
sim_cia cia,
struct hw *hw,
const void *source,
int space,
unsigned_word addr,
unsigned nr_bytes)
{
SIM_DESC sd = CPU_STATE (cpu);
STATE_HW (sd)->cpu = cpu;
STATE_HW (sd)->cia = cia;
if (hw_io_write_buffer (hw, source, space, addr, nr_bytes) != nr_bytes)
sim_engine_abort (sd, cpu, cia, "broken CPU write");
}
void
sim_cpu_hw_io_read_buffer (sim_cpu *cpu,
sim_cia cia,
struct hw *hw,
void *dest,
int space,
unsigned_word addr,
unsigned nr_bytes)
{
SIM_DESC sd = CPU_STATE (cpu);
STATE_HW (sd)->cpu = cpu;
STATE_HW (sd)->cia = cia;
if (hw_io_read_buffer (hw, dest, space, addr, nr_bytes) != nr_bytes)
sim_engine_abort (sd, cpu, cia, "broken CPU read");
}
int
is_wrong_slot (SIM_DESC sd,
address_word cia,
itable_index index)
{
switch (STATE_CPU (sd, 0)->unit)
{
case memory_unit:
return !itable[index].option[itable_option_mu];
case integer_unit:
return !itable[index].option[itable_option_iu];
case any_unit:
return 0;
default:
sim_engine_abort (sd, STATE_CPU (sd, 0), cia,
"internal error - is_wrong_slot - bad switch");
return -1;
}
}
static SIM_RC
schedule_watchpoint (SIM_DESC sd,
sim_watch_point *point)
{
sim_watchpoints *watch = STATE_WATCHPOINTS (sd);
switch (point->type)
{
case pc_watchpoint:
point->event = sim_events_watch_sim (sd,
watch->pc,
watch->sizeof_pc,
0/* host-endian */,
point->is_within,
point->arg0, point->arg1,
/* PC in arg0..arg1 */
handle_watchpoint,
point);
return SIM_RC_OK;
case clock_watchpoint:
point->event = sim_events_watch_clock (sd,
point->arg0, /* ms time */
handle_watchpoint,
point);
return SIM_RC_OK;
case cycles_watchpoint:
point->event = sim_events_schedule (sd,
point->arg0, /* time */
handle_watchpoint,
point);
return SIM_RC_OK;
default:
sim_engine_abort (sd, NULL, NULL_CIA,
"handle_watchpoint - internal error - bad switch");
return SIM_RC_FAIL;
}
return SIM_RC_OK;
}
BI
frvbf_check_non_excepting_load (
SIM_CPU *current_cpu, SI base_index, SI disp_index, SI target_index,
SI immediate_disp, QI data_size, BI is_float
)
{
BI rc = 1; /* perform the load. */
SIM_DESC sd = CPU_STATE (current_cpu);
int daec = 0;
int rec = 0;
int ec = 0;
USI necr;
int do_elos;
SI NE_flags[2];
SI NE_base;
SI nesr;
SI ne_index;
FRV_REGISTER_CONTROL *control;
SI address = GET_H_GR (base_index);
if (disp_index >= 0)
address += GET_H_GR (disp_index);
else
address += immediate_disp;
/* Check for interrupt factors. */
switch (data_size)
{
case NESR_UQI_SIZE:
case NESR_QI_SIZE:
break;
case NESR_UHI_SIZE:
case NESR_HI_SIZE:
if (address & 1)
ec = 1;
break;
case NESR_SI_SIZE:
if (address & 3)
ec = 1;
break;
case NESR_DI_SIZE:
if (address & 7)
ec = 1;
if (target_index & 1)
rec = 1;
break;
case NESR_XI_SIZE:
if (address & 0xf)
ec = 1;
if (target_index & 3)
rec = 1;
break;
default:
{
IADDR pc = GET_H_PC ();
sim_engine_abort (sd, current_cpu, pc,
"check_non_excepting_load: Incorrect data_size\n");
break;
}
}
control = CPU_REGISTER_CONTROL (current_cpu);
if (control->spr[H_SPR_NECR].implemented)
{
necr = GET_NECR ();
do_elos = GET_NECR_VALID (necr) && GET_NECR_ELOS (necr);
}
else
do_elos = 0;
/* NECR, NESR, NEEAR are only implemented for the full frv machine. */
if (do_elos)
{
ne_index = next_available_nesr (current_cpu, NO_NESR);
if (ne_index == NO_NESR)
{
IADDR pc = GET_H_PC ();
sim_engine_abort (sd, current_cpu, pc,
"No available NESR register\n");
}
/* Fill in the basic fields of the NESR. */
nesr = GET_NESR (ne_index);
SET_NESR_VALID (nesr);
SET_NESR_EAV (nesr);
SET_NESR_DRN (nesr, target_index);
SET_NESR_SIZE (nesr, data_size);
SET_NESR_NEAN (nesr, ne_index);
if (is_float)
SET_NESR_FR (nesr);
else
CLEAR_NESR_FR (nesr);
/* Set the corresponding NEEAR. */
SET_NEEAR (ne_index, address);
SET_NESR_DAEC (nesr, 0);
SET_NESR_REC (nesr, 0);
SET_NESR_EC (nesr, 0);
}
/* Set the NE flag corresponding to the target register if an interrupt
factor was detected.
daec is not checked here yet, but is declared for future reference. */
if (is_float)
NE_base = H_SPR_FNER0;
else
NE_base = H_SPR_GNER0;
GET_NE_FLAGS (NE_flags, NE_base);
if (rec)
{
SET_NE_FLAG (NE_flags, target_index);
if (do_elos)
SET_NESR_REC (nesr, NESR_REGISTER_NOT_ALIGNED);
}
if (ec)
{
SET_NE_FLAG (NE_flags, target_index);
if (do_elos)
SET_NESR_EC (nesr, NESR_MEM_ADDRESS_NOT_ALIGNED);
}
if (do_elos)
SET_NESR (ne_index, nesr);
/* If no interrupt factor was detected then set the NE flag on the
target register if the NE flag on one of the input registers
is already set. */
if (! rec && ! ec && ! daec)
{
BI ne_flag = GET_NE_FLAG (NE_flags, base_index);
if (disp_index >= 0)
ne_flag |= GET_NE_FLAG (NE_flags, disp_index);
if (ne_flag)
{
SET_NE_FLAG (NE_flags, target_index);
rc = 0; /* Do not perform the load. */
}
else
CLEAR_NE_FLAG (NE_flags, target_index);
}
SET_NE_FLAGS (NE_base, NE_flags);
return rc; /* perform the load? */
}
/* Set ESFR0, EPCRx, ESRx, EARx and EDRx, according to the given program
interrupt. */
static void
set_exception_status_registers (
SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
)
{
struct frv_interrupt *interrupt = & frv_interrupt_table[item->kind];
int slot = (item->vpc - previous_vliw_pc) / 4;
int reg_index = -1;
int set_ear = 0;
int set_edr = 0;
int set_daec = 0;
int set_epcr = 0;
SI esr = 0;
SIM_DESC sd = CPU_STATE (current_cpu);
/* If the interrupt is strict (precise) or the interrupt is on the insns
in the I0 pipe, then set the 0 registers. */
if (interrupt->precise)
{
reg_index = 0;
if (interrupt->kind == FRV_REGISTER_EXCEPTION)
SET_ESR_REC (esr, item->u.rec);
else if (interrupt->kind == FRV_INSTRUCTION_ACCESS_EXCEPTION)
SET_ESR_IAEC (esr, item->u.iaec);
/* For fr550, don't set epcr for precise interrupts. */
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
set_epcr = 1;
}
else
{
switch (interrupt->kind)
{
case FRV_DIVISION_EXCEPTION:
set_isr_exception_fields (current_cpu, item);
/* fall thru to set reg_index. */
case FRV_COMMIT_EXCEPTION:
/* For fr550, always use ESR0. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
reg_index = 0;
else if (item->slot == UNIT_I0)
reg_index = 0;
else if (item->slot == UNIT_I1)
reg_index = 1;
set_epcr = 1;
break;
case FRV_DATA_STORE_ERROR:
reg_index = 14; /* Use ESR14. */
break;
case FRV_DATA_ACCESS_ERROR:
reg_index = 15; /* Use ESR15, EPCR15. */
set_ear = 1;
break;
case FRV_DATA_ACCESS_EXCEPTION:
set_daec = 1;
/* fall through */
case FRV_DATA_ACCESS_MMU_MISS:
case FRV_MEM_ADDRESS_NOT_ALIGNED:
/* Get the appropriate ESR, EPCR, EAR and EDR.
EAR will be set. EDR will not be set if this is a store insn. */
set_ear = 1;
/* For fr550, never use EDRx. */
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
if (item->u.data_written.length != 0)
set_edr = 1;
reg_index = esr_for_data_access_exception (current_cpu, item);
set_epcr = 1;
break;
case FRV_MP_EXCEPTION:
/* For fr550, use EPCR2 and ESR2. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
reg_index = 2;
set_epcr = 1;
}
break; /* MSR0-1, FQ0-9 are already set. */
case FRV_FP_EXCEPTION:
set_fp_exception_registers (current_cpu, item);
/* For fr550, use EPCR2 and ESR2. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
reg_index = 2;
set_epcr = 1;
}
break;
default:
{
SIM_DESC sd = CPU_STATE (current_cpu);
IADDR pc = CPU_PC_GET (current_cpu);
sim_engine_abort (sd, current_cpu, pc,
"invalid non-strict program interrupt kind: %d\n",
interrupt->kind);
break;
}
}
} /* non-strict (imprecise) interrupt */
/* Now fill in the selected exception status registers. */
if (reg_index != -1)
{
/* Now set the exception status registers. */
SET_ESFR_FLAG (reg_index);
SET_ESR_EC (esr, interrupt->ec);
if (set_epcr)
{
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
SET_EPCR (reg_index, previous_vliw_pc);
else
SET_EPCR (reg_index, item->vpc);
}
if (set_ear)
{
SET_EAR (reg_index, item->eaddress);
SET_ESR_EAV (esr);
}
else
CLEAR_ESR_EAV (esr);
if (set_edr)
{
int edn = set_edr_register (current_cpu, item, 0/* EDR0-3 */);
SET_ESR_EDN (esr, edn);
SET_ESR_EDV (esr);
}
else
CLEAR_ESR_EDV (esr);
if (set_daec)
SET_ESR_DAEC (esr, item->u.daec);
SET_ESR_VALID (esr);
SET_ESR (reg_index, esr);
}
}
/* Handle an individual interrupt. */
static void
handle_interrupt (SIM_CPU *current_cpu, IADDR pc)
{
struct frv_interrupt *interrupt;
int writeback_done = 0;
while (1)
{
/* Interrupts are queued in priority order with the highest priority
last. */
int index = frv_interrupt_state.queue_index - 1;
struct frv_interrupt_queue_element *item
= & frv_interrupt_state.queue[index];
interrupt = & frv_interrupt_table[item->kind];
switch (interrupt->iclass)
{
case FRV_EXTERNAL_INTERRUPT:
/* Perform writeback first. This may cause a higher priority
interrupt. */
if (! writeback_done)
{
frvbf_perform_writeback (current_cpu);
writeback_done = 1;
continue;
}
frv_external_interrupt (current_cpu, item, pc);
return;
case FRV_SOFTWARE_INTERRUPT:
frv_interrupt_state.queue_index = index;
frv_software_interrupt (current_cpu, item, pc);
return;
case FRV_PROGRAM_INTERRUPT:
/* If the program interrupt is not strict (imprecise), then perform
writeback first. This may, in turn, cause a higher priority
interrupt. */
if (! interrupt->precise && ! writeback_done)
{
frv_interrupt_state.imprecise_interrupt = item;
frvbf_perform_writeback (current_cpu);
writeback_done = 1;
continue;
}
frv_interrupt_state.queue_index = index;
frv_program_interrupt (current_cpu, item, pc);
return;
case FRV_BREAK_INTERRUPT:
frv_interrupt_state.queue_index = index;
frv_break_interrupt (current_cpu, interrupt, pc);
return;
case FRV_RESET_INTERRUPT:
break;
default:
break;
}
frv_interrupt_state.queue_index = index;
break; /* out of loop. */
}
/* We should never get here. */
{
SIM_DESC sd = CPU_STATE (current_cpu);
sim_engine_abort (sd, current_cpu, pc,
"interrupt class not supported %d\n",
interrupt->iclass);
}
}
/* Save data written to memory into the interrupt state so that it can be
copied to the appropriate EDR register, if necessary, in the event of an
interrupt. */
void
frv_save_data_written_for_interrupts (
SIM_CPU *current_cpu, CGEN_WRITE_QUEUE_ELEMENT *item
)
{
/* Record the slot containing the insn doing the write in the
interrupt state. */
frv_interrupt_state.slot = CGEN_WRITE_QUEUE_ELEMENT_PIPE (item);
/* Now record any data written to memory in the interrupt state. */
switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
{
case CGEN_BI_WRITE:
case CGEN_QI_WRITE:
case CGEN_SI_WRITE:
case CGEN_SF_WRITE:
case CGEN_PC_WRITE:
case CGEN_FN_HI_WRITE:
case CGEN_FN_SI_WRITE:
case CGEN_FN_SF_WRITE:
case CGEN_FN_DI_WRITE:
case CGEN_FN_DF_WRITE:
case CGEN_FN_XI_WRITE:
case CGEN_FN_PC_WRITE:
break; /* Ignore writes to registers. */
case CGEN_MEM_QI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_qi_write.value;
break;
case CGEN_MEM_HI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_hi_write.value;
break;
case CGEN_MEM_SI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_si_write.value;
break;
case CGEN_MEM_DI_WRITE:
frv_interrupt_state.data_written.length = 2;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_di_write.value >> 32;
frv_interrupt_state.data_written.words[1]
= item->kinds.mem_di_write.value;
break;
case CGEN_MEM_DF_WRITE:
frv_interrupt_state.data_written.length = 2;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_df_write.value >> 32;
frv_interrupt_state.data_written.words[1]
= item->kinds.mem_df_write.value;
break;
case CGEN_MEM_XI_WRITE:
frv_interrupt_state.data_written.length = 4;
frv_interrupt_state.data_written.words[0]
= item->kinds.mem_xi_write.value[0];
frv_interrupt_state.data_written.words[1]
= item->kinds.mem_xi_write.value[1];
frv_interrupt_state.data_written.words[2]
= item->kinds.mem_xi_write.value[2];
frv_interrupt_state.data_written.words[3]
= item->kinds.mem_xi_write.value[3];
break;
case CGEN_FN_MEM_QI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_qi_write.value;
break;
case CGEN_FN_MEM_HI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_hi_write.value;
break;
case CGEN_FN_MEM_SI_WRITE:
frv_interrupt_state.data_written.length = 1;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_si_write.value;
break;
case CGEN_FN_MEM_DI_WRITE:
frv_interrupt_state.data_written.length = 2;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_di_write.value >> 32;
frv_interrupt_state.data_written.words[1]
= item->kinds.fn_mem_di_write.value;
break;
case CGEN_FN_MEM_DF_WRITE:
frv_interrupt_state.data_written.length = 2;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_df_write.value >> 32;
frv_interrupt_state.data_written.words[1]
= item->kinds.fn_mem_df_write.value;
break;
case CGEN_FN_MEM_XI_WRITE:
frv_interrupt_state.data_written.length = 4;
frv_interrupt_state.data_written.words[0]
= item->kinds.fn_mem_xi_write.value[0];
frv_interrupt_state.data_written.words[1]
= item->kinds.fn_mem_xi_write.value[1];
frv_interrupt_state.data_written.words[2]
= item->kinds.fn_mem_xi_write.value[2];
frv_interrupt_state.data_written.words[3]
= item->kinds.fn_mem_xi_write.value[3];
break;
default:
{
SIM_DESC sd = CPU_STATE (current_cpu);
IADDR pc = CPU_PC_GET (current_cpu);
sim_engine_abort (sd, current_cpu, pc,
"unknown write kind during save for interrupt\n");
}
break;
}
}
/* Handle a program interrupt or a software interrupt in non-operating mode. */
void
frv_non_operating_interrupt (
SIM_CPU *current_cpu, enum frv_interrupt_kind kind, IADDR pc
)
{
SIM_DESC sd = CPU_STATE (current_cpu);
switch (kind)
{
case FRV_INTERRUPT_LEVEL_1:
case FRV_INTERRUPT_LEVEL_2:
case FRV_INTERRUPT_LEVEL_3:
case FRV_INTERRUPT_LEVEL_4:
case FRV_INTERRUPT_LEVEL_5:
case FRV_INTERRUPT_LEVEL_6:
case FRV_INTERRUPT_LEVEL_7:
case FRV_INTERRUPT_LEVEL_8:
case FRV_INTERRUPT_LEVEL_9:
case FRV_INTERRUPT_LEVEL_10:
case FRV_INTERRUPT_LEVEL_11:
case FRV_INTERRUPT_LEVEL_12:
case FRV_INTERRUPT_LEVEL_13:
case FRV_INTERRUPT_LEVEL_14:
case FRV_INTERRUPT_LEVEL_15:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: external %d\n", kind + 1);
break;
case FRV_TRAP_INSTRUCTION:
break; /* handle as in operating mode. */
case FRV_COMMIT_EXCEPTION:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: commit_exception\n");
break;
case FRV_DIVISION_EXCEPTION:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: division_exception\n");
break;
case FRV_DATA_STORE_ERROR:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: data_store_error\n");
break;
case FRV_DATA_ACCESS_EXCEPTION:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: data_access_exception\n");
break;
case FRV_DATA_ACCESS_MMU_MISS:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: data_access_mmu_miss\n");
break;
case FRV_DATA_ACCESS_ERROR:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: data_access_error\n");
break;
case FRV_MP_EXCEPTION:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: mp_exception\n");
break;
case FRV_FP_EXCEPTION:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: fp_exception\n");
break;
case FRV_MEM_ADDRESS_NOT_ALIGNED:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: mem_address_not_aligned\n");
break;
case FRV_REGISTER_EXCEPTION:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: register_exception\n");
break;
case FRV_MP_DISABLED:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: mp_disabled\n");
break;
case FRV_FP_DISABLED:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: fp_disabled\n");
break;
case FRV_PRIVILEGED_INSTRUCTION:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: privileged_instruction\n");
break;
case FRV_ILLEGAL_INSTRUCTION:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: illegal_instruction\n");
break;
case FRV_INSTRUCTION_ACCESS_EXCEPTION:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: instruction_access_exception\n");
break;
case FRV_INSTRUCTION_ACCESS_MMU_MISS:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: instruction_access_mmu_miss\n");
break;
case FRV_INSTRUCTION_ACCESS_ERROR:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: insn_access_error\n");
break;
case FRV_COMPOUND_EXCEPTION:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: compound_exception\n");
break;
case FRV_BREAK_EXCEPTION:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: break_exception\n");
break;
case FRV_RESET:
sim_engine_abort (sd, current_cpu, pc,
"interrupt: reset\n");
break;
default:
sim_engine_abort (sd, current_cpu, pc,
"unhandled interrupt kind: %d\n", kind);
break;
}
}
