int speechStop()
{
#ifdef _WIN32
return stopspeech();
#else
return spd_stop(conn);
#endif
}
void CSpeech::Speak(const std::string &strText, bool bInterrupt) {
if (!Init()) {
return;
}
if (!bInterrupt) {
spd_say(m_speaker, SPD_TEXT, strText.c_str());
} else {
spd_stop(m_speaker);
}
}
int readSpdData (u8 * spdData)
{
DECLARE_GLOBAL_DATA_PTR;
volatile i2c8220_t *pi2cReg;
volatile pcfg8220_t *pcfg;
u8 slvAdr = DRAM_SPD;
u8 Tmp;
int Length = SPD_SIZE;
int i = 0;
/* Enable Port Configuration for SDA and SDL signals */
pcfg = (volatile pcfg8220_t *) (MMAP_PCFG);
__asm__ ("sync");
pcfg->pcfg3 &= ~CFG_I2C_PORT3_CONFIG;
__asm__ ("sync");
/* Points the structure to I2c mbar memory offset */
pi2cReg = (volatile i2c8220_t *) (MMAP_I2C);
/* Clear FDR, ADR, SR and CR reg */
pi2cReg->adr = 0;
pi2cReg->fdr = 0;
pi2cReg->cr = 0;
pi2cReg->sr = 0;
/* Set for fix XLB Bus Frequency */
switch (gd->bus_clk) {
case 60000000:
pi2cReg->fdr = 0x15;
break;
case 70000000:
pi2cReg->fdr = 0x16;
break;
case 80000000:
pi2cReg->fdr = 0x3a;
break;
case 90000000:
pi2cReg->fdr = 0x17;
break;
case 100000000:
pi2cReg->fdr = 0x3b;
break;
case 110000000:
pi2cReg->fdr = 0x18;
break;
case 120000000:
pi2cReg->fdr = 0x19;
break;
case 130000000:
pi2cReg->fdr = 0x1a;
break;
}
pi2cReg->adr = CFG_I2C_SLAVE<<1;
pi2cReg->cr = I2C_CTL_EN; /* Set Enable */
/*
The I2C bus should be in Idle state. If the bus is busy,
clear the STA bit in control register
*/
if (spd_status (pi2cReg, I2C_STA_BB, 0) != OK) {
if ((pi2cReg->cr & I2C_CTL_STA) == I2C_CTL_STA)
pi2cReg->cr &= ~I2C_CTL_STA;
/* Check again if it is still busy, return error if found */
if (spd_status (pi2cReg, I2C_STA_BB, 1) == OK)
return ERROR;
}
pi2cReg->cr |= I2C_CTL_TX; /* Enable the I2c for TX, Ack */
pi2cReg->cr |= I2C_CTL_STA; /* Generate start signal */
if (spd_status (pi2cReg, I2C_STA_BB, 1) != OK)
return ERROR;
/* Write slave address */
pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */
pi2cReg->dr = slvAdr; /* Write a byte */
if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */
spd_stop (pi2cReg);
return ERROR;
}
if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
spd_stop (pi2cReg);
return ERROR;
}
/* Issue the offset to start */
pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */
pi2cReg->dr = 0; /* Write a byte */
if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */
spd_stop (pi2cReg);
return ERROR;
}
if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
spd_stop (pi2cReg);
return ERROR;
}
/* Set repeat start */
pi2cReg->cr |= I2C_CTL_RSTA; /* Repeat Start */
pi2cReg->sr &= ~I2C_STA_IF; /* Clear Interrupt */
pi2cReg->dr = slvAdr | 1; /* Write a byte */
if (spd_status (pi2cReg, I2C_STA_CF, 1) != OK) { /* Transfer not complete? */
spd_stop (pi2cReg);
return ERROR;
}
if (spd_status (pi2cReg, I2C_STA_IF, 1) != OK) {
spd_stop (pi2cReg);
return ERROR;
}
if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01))
return ERROR;
pi2cReg->cr &= ~I2C_CTL_TX; /* Set receive mode */
if (((pi2cReg->sr & 0x07) == 0x07) || (pi2cReg->sr & 0x01))
return ERROR;
/* Dummy Read */
if (spd_readbyte (pi2cReg, &Tmp, &i) != OK) {
spd_stop (pi2cReg);
return ERROR;
}
i = 0;
while (Length) {
if (Length == 2)
pi2cReg->cr |= I2C_CTL_TXAK;
if (Length == 1)
pi2cReg->cr &= ~I2C_CTL_STA;
if (spd_readbyte (pi2cReg, spdData, &Length) != OK) {
return spd_stop (pi2cReg);
}
i++;
Length--;
spdData++;
}
/* Stop the service */
spd_stop (pi2cReg);
return OK;
}
