void writeregs ( uint8_t data[] , uint8_t size )
{
spi_cson();
for ( uint8_t i = 0 ; i < size ; i++)
{
spi_sendbyte( data[i]);
}
spi_csoff();
delay(1000);
}
static char checkpacket()
{
spi_cson();
int status = spi_sendzerorecvbyte();
spi_csoff();
if( (status & B00001110) != B00001110 )
{
// rx fifo not empty
return 2;
}
return 0;
}
static char checkpacket()
{
spi_cson();
int status = spi_sendzerorecvbyte();
spi_csoff();
if ( status&(1<<MASK_RX_DR) )
{ // rx clear bit
// this is not working well
// xn_writereg( STATUS , (1<<MASK_RX_DR) );
//RX packet received
//return 1;
}
if( (status & B00001110) != B00001110 )
{
// rx fifo not empty
return 2;
}
return 0;
}
void rx_init()
{
// always on (CH_ON) channel set 1
aux[AUXNUMBER - 2] = 1;
// always off (CH_OFF) channel set 0
aux[AUXNUMBER - 1] = 0;
#ifdef AUX1_START_ON
aux[CH_AUX1] = 1;
#endif
#ifdef RADIO_XN297L
#define XN_TO_RX B10001111
#define XN_TO_TX B10000010
#define XN_POWER B00111111
#endif
#ifdef RADIO_XN297
static uint8_t bbcal[6] = { 0x3f , 0x4c , 0x84 , 0x6F , 0x9c , 0x20 };
writeregs( bbcal , sizeof(bbcal) );
// new values
static uint8_t rfcal[8] = { 0x3e , 0xc9 , 0x9a , 0xA0 , 0x61 , 0xbb , 0xab , 0x9c };
writeregs( rfcal , sizeof(rfcal) );
static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , 0xa7 , 0x03};
writeregs( demodcal , sizeof(demodcal) );
#define XN_TO_RX B00001111
#define XN_TO_TX B00000010
#define XN_POWER B00000111
#endif
bleinit();
delay(100);
int rxaddress[5] = { 0 , 0 , 0 , 0 , 0 };
xn_writerxaddress( rxaddress);
xn_writereg( EN_AA , 0 ); // aa disabled
xn_writereg( EN_RXADDR , 1 ); // pipe 0 only
xn_writereg( RF_SETUP , XN_POWER); // lna high current on ( better performance )
xn_writereg( RX_PW_P0 , 15 ); // payload size
xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?)
xn_writereg( SETUP_AW , 3 ); // address size (5 bits)
xn_command( FLUSH_RX);
xn_writereg( RF_CH , 0 ); // bind on channel 0
// set above
// xn_writereg( 29 , 32); // feture reg , CE mode (software controlled)
#ifdef RADIO_XN297L
xn_writereg( 0x1d, B00111000 ); // 64 bit payload , software ce
spi_cson();
spi_sendbyte( 0xFD); // internal CE high command
spi_sendbyte( 0); // required for above
spi_csoff();
#endif
#ifdef RADIO_XN297
xn_writereg( 0x1d, B00011000 ); // 64 bit payload , software ce
#endif
xn_writereg( 0 , XN_TO_RX ); // power up, crc enabled, rx mode
#ifdef RADIO_CHECK
void check_radio(void);
check_radio();
#endif
}
void rx_init()
{
// always on (CH_ON) channel set 1
aux[AUXNUMBER - 2] = 1;
// always off (CH_OFF) channel set 0
aux[AUXNUMBER - 1] = 0;
#ifdef AUX1_START_ON
aux[CH_AUX1] = 1;
#endif
#ifdef AUX4_START_ON
aux[CH_AUX4] = 1;
#endif
#ifdef RADIO_XN297L
#define XN_TO_RX B10001111
#define XN_TO_TX B10000010
#define XN_POWER B00111111
#endif
#ifdef RADIO_XN297
static uint8_t bbcal[6] = { 0x3f , 0x4c , 0x84 , 0x6F , 0x9c , 0x20 };
writeregs( bbcal , sizeof(bbcal) );
// new values
static uint8_t rfcal[8] = { 0x3e , 0xc9 , 0x9a , 0xA0 , 0x61 , 0xbb , 0xab , 0x9c };
writeregs( rfcal , sizeof(rfcal) );
static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , 0xa7 , 0x03};
//static uint8_t demodcal[6] = { 0x39 , 0x0b , 0xdf , 0xc4 , B00100111 , B00000000};
writeregs( demodcal , sizeof(demodcal) );
#define XN_TO_RX B00001111
#define XN_TO_TX B00000010
//#define XN_POWER B00000111 // disabled by silverAG for SilverVISE - value is added from config.h
// SilverVISE - start:
#ifdef TX_POWER_GENERAL
// use value from config.h
#define XN_POWER TX_POWER_GENERAL
#else
#define XN_POWER B00000111
#endif
// SilverVISE - end
#endif
bleinit();
delay(100);
int rxaddress[5] = { 0 , 0 , 0 , 0 , 0 };
xn_writerxaddress( rxaddress);
xn_writereg( EN_AA , 0 ); // aa disabled
xn_writereg( EN_RXADDR , 1 ); // pipe 0 only
xn_writereg( RF_SETUP , XN_POWER); // lna high current on ( better performance )
xn_writereg( RX_PW_P0 , 15 ); // payload size
xn_writereg( SETUP_RETR , 0 ); // no retransmissions ( redundant?)
xn_writereg( SETUP_AW , 3 ); // address size (5 bits)
xn_command( FLUSH_RX);
xn_writereg( RF_CH , 0 ); // bind on channel 0
#ifdef RADIO_XN297L
xn_writereg( 0x1d, B00111000 ); // 64 bit payload , software ce
spi_cson();
spi_sendbyte( 0xFD); // internal CE high command
spi_sendbyte( 0); // required for above
spi_csoff();
#endif
#ifdef RADIO_XN297
xn_writereg( 0x1d, B00011000 ); // 64 bit payload , software ce
#endif
xn_writereg( 0 , XN_TO_RX ); // power up, crc enabled, rx mode
#ifdef RADIO_CHECK
int rxcheck = xn_readreg( 0x0f); // rx address pipe 5
// should be 0xc6
extern void failloop( int);
if ( rxcheck != 0xc6) failloop(3);
#endif
}