bool Spi_stm32::init(void) { bool ret = true; // SPI IOs configurations // MISO init gpio_mode_setup(config_.miso_gpio_config.port, GPIO_MODE_AF, config_.miso_gpio_config.pull, config_.miso_gpio_config.pin ); gpio_set_af(config_.miso_gpio_config.port, config_.miso_gpio_config.alt_fct, config_.miso_gpio_config.pin ); // MOSI init gpio_mode_setup(config_.mosi_gpio_config.port, GPIO_MODE_AF, config_.mosi_gpio_config.pull, config_.mosi_gpio_config.pin ); gpio_set_af(config_.mosi_gpio_config.port, config_.mosi_gpio_config.alt_fct, config_.mosi_gpio_config.pin ); gpio_set_output_options(config_.mosi_gpio_config.port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, config_.mosi_gpio_config.pin ); // SCK init gpio_mode_setup(config_.sck_gpio_config.port, GPIO_MODE_AF, config_.sck_gpio_config.pull, config_.sck_gpio_config.pin ); gpio_set_af(config_.sck_gpio_config.port, config_.sck_gpio_config.alt_fct, config_.sck_gpio_config.pin ); gpio_set_output_options(config_.sck_gpio_config.port, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, config_.sck_gpio_config.pin ); // SPI configuration switch (config_.spi_device) { case STM32_SPI1: rcc_periph_clock_enable(RCC_SPI1); break; case STM32_SPI2: rcc_periph_clock_enable(RCC_SPI2); break; case STM32_SPI3: rcc_periph_clock_enable(RCC_SPI3); break; default: ret = false; } if (config_.ss_mode_hard) { spi_disable_software_slave_management(spi_); spi_enable_ss_output(spi_); } // Warning: software slave managment not tested else { spi_enable_software_slave_management(spi_); } SPI_CR1(spi_) |= config_.clk_div; // Clock frequency spi_set_standard_mode(spi_, config_.mode); spi_enable(spi_); spi_set_master_mode(spi_); return ret; }
int devspi_create(const struct spi_config *conf) { struct dev_spi *spi = NULL; if (!conf) return -EINVAL; if (conf->base == 0) return -EINVAL; if ((conf->idx < 0) || (conf->idx > MAX_SPIS)) return -EINVAL; spi = kalloc(sizeof(struct dev_spi)); if (!spi) return -ENOMEM; /* Claim pins for SCK/MOSI/MISO */ gpio_create(&mod_spi, &conf->pio_sck); gpio_create(&mod_spi, &conf->pio_mosi); gpio_create(&mod_spi, &conf->pio_miso); /* Erase spi content */ memset(spi, 0, sizeof(struct dev_spi)); /* Enable clocks */ rcc_periph_clock_enable(conf->rcc); rcc_periph_clock_enable(conf->dma_rcc); /* Startup routine */ //spi_disable(conf->base); /**********************************/ /* reset SPI1 */ spi_reset(conf->base); /* init SPI1 master */ spi_init_master(conf->base, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); /* enable SPI1 first */ spi_enable(conf->base); /**********************************/ #if 0 spi_set_master_mode(conf->base); spi_set_baudrate_prescaler(conf->base, SPI_CR1_BR_FPCLK_DIV_256); /* TODO: Calculate prescaler from baudrate */ if(conf->polarity == 0) spi_set_clock_polarity_0(conf->base); else spi_set_clock_polarity_1(conf->base); if(conf->phase == 0) spi_set_clock_phase_0(conf->base); else spi_set_clock_phase_1(conf->base); if(conf->rx_only == 0) spi_set_full_duplex_mode(conf->base); else spi_set_receive_only_mode(conf->base); if(conf->bidir_mode == 0) spi_set_unidirectional_mode(conf->base); else spi_set_bidirectional_mode(conf->base); if(conf->dff_16) spi_set_dff_16bit(conf->base); else spi_set_dff_8bit(conf->base); if(conf->enable_software_slave_management) spi_enable_software_slave_management(conf->base); else spi_disable_software_slave_management(conf->base); if(conf->send_msb_first) spi_send_msb_first(conf->base); else spi_send_lsb_first(conf->base); spi_set_nss_high(conf->base); #endif /* Set up device struct */ spi->base = conf->base; spi->irq = conf->irq; //spi->tx_dma_config = &conf->tx_dma; //spi->rx_dma_config = &conf->rx_dma; spi->mutex = mutex_init(); /* Store address in the DEV_SPI array. */ DEV_SPI[conf->idx] = spi; /* Enable interrupts */ //nvic_set_priority(conf->irq, 1); //nvic_enable_irq(conf->irq); return 0; }