void spi_stop(void)
{
spi_disable_tx_dma(SPI2);
spi_disable_rx_dma(SPI2);
spi_disable(SPI2);
// spi_clean_disable(SPI2);
}
/* SPI transmit completed with DMA */
void dma1_channel3_isr(void)
{
gpio_set(GPIOB,GPIO1);
if ((DMA1_ISR &DMA_ISR_TCIF3) != 0) {
DMA1_IFCR |= DMA_IFCR_CTCIF3;
}
dma_disable_transfer_complete_interrupt(DMA1, DMA_CHANNEL3);
spi_disable_tx_dma(SPI1);
dma_disable_channel(DMA1, DMA_CHANNEL3);
/* If tx_len < rx_len, create a dummy transfer to clock in the remaining
* rx data
*/
if (rx_buf_remainder > 0) {
dma_channel_reset(DMA1, DMA_CHANNEL3);
dma_set_peripheral_address(DMA1, DMA_CHANNEL3, (uint32_t)&SPI1_DR);
dma_set_memory_address(DMA1, DMA_CHANNEL3, (uint32_t)(&dummy_tx_buf)); // Change here
dma_set_number_of_data(DMA1, DMA_CHANNEL3, rx_buf_remainder); // Change here
dma_set_read_from_memory(DMA1, DMA_CHANNEL3);
dma_disable_memory_increment_mode(DMA1, DMA_CHANNEL3); // Change here
#if USE_16BIT_TRANSFERS
dma_set_peripheral_size(DMA1, DMA_CHANNEL3, DMA_CCR_PSIZE_16BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL3, DMA_CCR_MSIZE_16BIT);
#else
dma_set_peripheral_size(DMA1, DMA_CHANNEL3, DMA_CCR_PSIZE_8BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL3, DMA_CCR_MSIZE_8BIT);
#endif
dma_set_priority(DMA1, DMA_CHANNEL3, DMA_CCR_PL_HIGH);
rx_buf_remainder = 0; // Clear the buffer remainder to disable this section later
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL3);
dma_enable_channel(DMA1, DMA_CHANNEL3);
spi_enable_tx_dma(SPI1);
} else {
/* Increment the status to indicate one of the transfers is complete */
transceive_status++;
}
gpio_clear(GPIOB,GPIO1);
}
/* Cleanup between DMA transfers. */
static void cleanup_dma_spi(void){
/* Disable SPI without resetting the peripheral. */
dma_disable_channel(DMA1, DMA_CHANNEL3);
dma_disable_channel(DMA1, DMA_CHANNEL2);
spi_disable(SPI3);
if(TxSpi){
/* After tx_spi() completes there will be several nonsense bytes
* in the RXFIFO. They must be cleared out so that they don't
* corrupt a subsequent SPI read. */
uint8_t throwaway;
throwaway = SPI_DR(SPI3);
throwaway = SPI_DR(SPI3);
throwaway = SPI_DR(SPI3);
throwaway = SPI_DR(SPI3);
throwaway = throwaway; /* Suppress compiler warnings. */
TxSpi = false;
}
spi_disable_tx_dma(SPI3);
spi_disable_rx_dma(SPI3);
DmaCleanupNeeded = false;
}
/// Processing done after tx completes
void process_tx_dma_interrupt(struct spi_periph *periph) {
struct spi_periph_dma *dma = periph->init_struct;
struct spi_transaction *trans = periph->trans[periph->trans_extract_idx];
/* Disable DMA Channel */
dma_disable_transfer_complete_interrupt(dma->dma, dma->tx_chan);
/* Disable SPI TX request */
spi_disable_tx_dma((uint32_t)periph->reg_addr);
/* Disable DMA tx channel */
dma_disable_channel(dma->dma, dma->tx_chan);
if (dma->tx_extra_dummy_dma) {
/*
* We are finished the first part of the transmit with real data,
* but still need to clock in the rest of the receive data.
* Set up a dummy dma transmit transfer to accomplish this.
*/
/* Reset the flag so this only happens once in a transaction */
dma->tx_extra_dummy_dma = FALSE;
/* Use the difference in length between tx and rx */
uint16_t len_remaining = trans->input_length - trans->output_length;
spi_configure_dma(dma->dma, dma->tx_chan, (uint32_t)dma->spidr,
(uint32_t)&(dma->tx_dummy_buf), len_remaining, trans->dss, FALSE);
dma_set_read_from_memory(dma->dma, dma->tx_chan);
dma_set_priority(dma->dma, dma->tx_chan, DMA_CCR_PL_MEDIUM);
/* Enable DMA transfer complete interrupts. */
dma_enable_transfer_complete_interrupt(dma->dma, dma->tx_chan);
/* Enable DMA channels */
dma_enable_channel(dma->dma, dma->tx_chan);
/* Enable SPI transfers via DMA */
spi_enable_tx_dma((uint32_t)periph->reg_addr);
}
}
void mew_spi_flash_init(void) {
gpio_mode_setup(MEW_FLASH_GPIO_PORT_WP, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, MEW_FLASH_GPIO_PIN_WP);
gpio_set_output_options(MEW_FLASH_GPIO_PORT_WP, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, MEW_FLASH_GPIO_PIN_WP);
gpio_set(MEW_FLASH_GPIO_PORT_WP, MEW_FLASH_GPIO_PIN_WP);
gpio_mode_setup(MEW_FLASH_GPIO_PORT_HOLD, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, MEW_FLASH_GPIO_PIN_HOLD);
gpio_set_output_options(MEW_FLASH_GPIO_PORT_HOLD, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, MEW_FLASH_GPIO_PIN_HOLD);
gpio_set(MEW_FLASH_GPIO_PORT_HOLD, MEW_FLASH_GPIO_PIN_HOLD);
gpio_mode_setup(MEW_FLASH_GPIO_PORT_CS, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, MEW_FLASH_GPIO_PIN_CS);
gpio_set_output_options(MEW_FLASH_GPIO_PORT_CS, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, MEW_FLASH_GPIO_PIN_CS);
gpio_set(MEW_FLASH_GPIO_PORT_CS, MEW_FLASH_GPIO_PIN_CS);
gpio_mode_setup(MEW_FLASH_SPI_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLDOWN, MEW_FLASH_SPI_GPIO_PINS);
gpio_set_output_options(MEW_FLASH_SPI_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, MEW_FLASH_SPI_GPIO_PINS);
gpio_set_af(MEW_FLASH_SPI_GPIO_PORT, MEW_FLASH_SPI_GPIO_AF_NUMBER, MEW_FLASH_SPI_GPIO_PINS);
spi_disable(MEW_FLASH_SPI);
spi_set_master_mode(MEW_FLASH_SPI);
spi_set_baudrate_prescaler(MEW_FLASH_SPI, SPI_CR1_BR_FPCLK_DIV_2);
spi_set_clock_polarity_0(MEW_FLASH_SPI);
spi_set_clock_phase_0(MEW_FLASH_SPI);
spi_set_unidirectional_mode(MEW_FLASH_SPI);
spi_enable_software_slave_management(MEW_FLASH_SPI);
spi_send_msb_first(MEW_FLASH_SPI);
spi_set_nss_high(MEW_FLASH_SPI);
SPI_I2SCFGR(MEW_FLASH_SPI) &= ~SPI_I2SCFGR_I2SMOD;
spi_disable_tx_buffer_empty_interrupt(MEW_FLASH_SPI);
spi_disable_rx_buffer_not_empty_interrupt(MEW_FLASH_SPI);
spi_disable_error_interrupt(MEW_FLASH_SPI);
spi_disable_tx_dma(MEW_FLASH_SPI);
spi_disable_rx_dma(MEW_FLASH_SPI);
spi_set_dff_8bit(MEW_FLASH_SPI);
spi_send_msb_first(MEW_FLASH_SPI);
spi_enable(MEW_FLASH_SPI);
}
