void radio_init()
{
rcc_periph_clock_enable(R_RCC_SPI);
rcc_periph_clock_enable(R_RCC_GPIO);
gpio_mode_setup(R_SPI_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
R_SPI_PINS);
gpio_set_af(R_SPI_PORT, R_SPI_AFn, R_SPI_PINS);
gpio_mode_setup(R_CS_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,
R_CS_PIN);
// Reset and enable the SPI periph
spi_reset(R_SPI);
spi_init_master(R_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_64,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
SPI_CR1_CRCL_8BIT,
SPI_CR1_MSBFIRST);
// Trigger an RXNE event when we have 8 bits (one byte) in the buffer
spi_fifo_reception_threshold_8bit(R_SPI);
// NSS must be set high for the peripheral to function
spi_enable_software_slave_management(R_SPI);
spi_set_nss_high(R_SPI);
gpio_set(R_CS_PORT, R_CS_PIN);
// Enable
spi_enable(R_SPI);
radio_sleep();
}
//Setup hardware
TouchADS7843::TouchADS7843(void)
{
//Enable clocks
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_SPI1EN); //SPI
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); //SPI
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); //PEN_INT
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN); //AFIO (EXTI)
//Setup GPIO
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, BIT13); //PEN_INT
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, BIT6); //MISO
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, BIT4); //CS
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, BIT5 | BIT7); //MOSI, SCK
//Set up SPI as mater
_cs(1);
spi_enable_software_slave_management(SPI1);
spi_set_nss_high(SPI1);
spi_set_baudrate_prescaler(SPI1, 7);
spi_set_clock_polarity_0(SPI1);
spi_set_clock_phase_0(SPI1);
spi_set_dff_8bit(SPI1);
spi_set_master_mode(SPI1);
spi_enable(SPI1);
//Enable PEN_INT
nvic_enable_irq(NVIC_EXTI15_10_IRQ);
exti_select_source(EXTI13, GPIOC);
exti_set_trigger(EXTI13, EXTI_TRIGGER_BOTH);
exti_reset_request(EXTI13);
exti_enable_request(EXTI13);
}
void spi_setup(void) {
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_SPI1EN);
/* For spi signal pins */
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPAEN);
/* For spi mode select on the l3gd20 */
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPEEN);
/* Setup GPIOE3 pin for spi mode l3gd20 select. */
gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3);
/* Start with spi communication disabled */
gpio_set(GPIOE, GPIO3);
/* Setup GPIO pins for AF5 for SPI1 signals. */
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO6 | GPIO7);
gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO6 | GPIO7);
//spi initialization;
spi_set_master_mode(SPI1);
spi_set_baudrate_prescaler(SPI1, SPI_CR1_BR_FPCLK_DIV_64);
spi_set_clock_polarity_0(SPI1);
spi_set_clock_phase_0(SPI1);
spi_set_full_duplex_mode(SPI1);
spi_set_unidirectional_mode(SPI1); /* bidirectional but in 3-wire */
spi_set_data_size(SPI1, SPI_CR2_DS_8BIT);
spi_enable_software_slave_management(SPI1);
spi_send_msb_first(SPI1);
spi_set_nss_high(SPI1);
//spi_enable_ss_output(SPI1);
spi_fifo_reception_threshold_8bit(SPI1);
SPI_I2SCFGR(SPI1) &= ~SPI_I2SCFGR_I2SMOD;
spi_enable(SPI1);
}
/* Setup the SPI bus. This function may cause spurious signals on the SPI bus,
* so it should be called before the transaction starts (i.e. while SS is high).
* -CPOL is the clock polarity (0 or 1)
* -CPHA is the clock phase (0 or 1)
* -baudrate is one of libopencm3's SPI_CR1_BAUDRATE_FPCLK_DIV_X values.
* Baudrates are derived from the low-speed peripheral clock APB1.
* -firstbit is either SPI_CR1_MSBFIRST or SPI_CR1_LSBFIRST. */
void setup_spi(uint8_t cpol, uint8_t cpha, uint8_t baudrate, uint8_t firstbit){
disable_and_reset_spi_properly();
SPI_CR1(SPI3) &= 0xFFC7; /* Mask off baudrate bits. */
SPI_CR1(SPI3) |= baudrate;
if(0 == cpol){
spi_set_clock_polarity_0(SPI3);
} else {
spi_set_clock_polarity_1(SPI3);
}
if(0 == cpha){
spi_set_clock_phase_0(SPI3);
} else {
spi_set_clock_polarity_1(SPI3);
}
spi_set_unidirectional_mode(SPI3); /* bidirectional but in 3-wire */
spi_set_full_duplex_mode(SPI3);
SPI_CR1(SPI3) &= ~SPI_CR1_LSBFIRST;
SPI_CR1(SPI3) |= firstbit;
spi_enable_software_slave_management(SPI3);
spi_set_nss_high(SPI3);
spi_set_master_mode(SPI3);
spi_set_data_size(SPI3, SPI_CR2_DS_8BIT);
spi_fifo_reception_threshold_8bit(SPI3);
SPI_I2SCFGR(SPI3) &= ~SPI_I2SCFGR_I2SMOD;
/* All DMA configuration is handled by tx_spi(), rx_spi(), and rxtx_spi(). */
}
void init_codec() {
/* enable clock for Aux power and power up the regulators */
rcc_peripheral_enable_clock(&CODEC_PWR_APB, CODEC_RCC_PWR);
gpio_set_mode(CODEC_PWR_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, CODEC_PWR);
gpio_set(CODEC_PWR_PORT, CODEC_PWR);
/* enable SPI1 clock */
rcc_peripheral_enable_clock(&CODEC_SPI_APB, CODEC_RCC_SPI);
/* enable clock for the chip select pin */
rcc_peripheral_enable_clock(&CODEC_IOS_APB, CODEC_RCC_IOS);
/* enable clock for the RST/DREQ lines */
rcc_peripheral_enable_clock(&CODEC_IOI_APB, CODEC_RCC_IOI);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN);
/* set the pin modes for the SPI pins */
gpio_set_mode(CODEC_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, CODEC_CS);
gpio_set_mode(CODEC_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, CODEC_MOSI);
gpio_set_mode(CODEC_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, CODEC_SCK);
gpio_set_mode(CODEC_PORT, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, CODEC_MISO);
/* set the modes for the reset and busy pins */
gpio_set_mode(CODEC_RST_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, CODEC_RST);
gpio_set_mode(CODEC_DREQ_PORT, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, CODEC_DREQ);
gpio_clear(CODEC_RST_PORT, CODEC_RST);
/* configure the SPI port */
spi_set_unidirectional_mode(CODEC_SPI);
spi_disable_crc(CODEC_SPI);
spi_set_dff_8bit(CODEC_SPI);
spi_set_full_duplex_mode(CODEC_SPI);
spi_enable_software_slave_management(CODEC_SPI);
spi_set_nss_high(CODEC_SPI);
spi_set_baudrate_prescaler(CODEC_SPI, SPI_CR1_BR_FPCLK_DIV_32);
spi_set_master_mode(CODEC_SPI);
spi_send_msb_first(CODEC_SPI);
spi_set_clock_polarity_0(CODEC_SPI);
spi_set_clock_phase_0(CODEC_SPI);
spi_disable_ss_output(CODEC_SPI);
spi_enable(CODEC_SPI);
/* disable chip select */
gpio_set(CODEC_PORT, CODEC_CS);
/* make sure reset is not asserted */
gpio_set(CODEC_RST_PORT, CODEC_RST);
return;
}
/* *************** HAL API functions **************************************** */
void hal_init( void ) {
int ret = 0;
/* Reset variables used in file. */
hal_system_time = 0;
// hal_reset_flags();
/* Enable GPIOA clock. Enable AFIO clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR,
RCC_APB2ENR_IOPAEN |
RCC_APB2ENR_IOPBEN |
RCC_APB2ENR_IOPCEN |
RCC_APB2ENR_SPI1EN |
RCC_APB2ENR_AFIOEN );
/* The following pins are output pins. */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,RST); //reset
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SLP_TR); //sleep
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SEL); //cs
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
SCK | MOSI | MISO); //sck mosi miso
spi_disable(RF_SPI);
SPI2_I2SCFGR = 0;
/* Setup SPI parameters. */
spi_init_master(RF_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_16, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
spi_set_unidirectional_mode(RF_SPI);
spi_set_full_duplex_mode(RF_SPI); /* Not receive-only */
spi_enable_software_slave_management(RF_SPI);
spi_set_nss_high(RF_SPI);
spi_enable_ss_output(RF_SPI); /* Required, see NSS, 25.3.1 section. */
/* Finally enable the SPI. */
spi_enable(RF_SPI);
/* Set GPIO4 (in GPIO port C) to 'input float'. */
gpio_set_mode(RF_IRQ_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, RF_IRQ_PIN);
gpio_clear(RF_IRQ_PORT, RF_IRQ_PIN);
/* Configure the EXTI subsystem. */
exti_select_source(EXTI4, RF_IRQ_PORT);
exti_set_trigger(EXTI4, EXTI_TRIGGER_RISING);
exti_enable_request(EXTI4);
exti_reset_request(EXTI4);
PRINTF("Enabling interrupts\r\n");
/* Enable EXTI0 interrupt. */
nvic_enable_irq(NVIC_EXTI4_IRQ);
nvic_set_priority(NVIC_EXTI4_IRQ,4);
//@@@!? timer_init();
// ret = trx_init();
// if(ret!=0)
// {
// PRINTF("rf231:hal init failed\r\n");
// }else
// {
// PRINTF("rf231:hal init success\r\n");
// }
}
void TxSpiInit(void)
{
/* Enable SPI2 */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN);
/* Enable GPIOA */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
/* Enable GPIOB */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
/* SCK, MOSI */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13 | GPIO15);
/* MISO */
gpio_set_mode(GPIOB, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, GPIO14);
/*CYRF cfg */
/* Reset and CS */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO11 | GPIO12);
gpio_set(GPIOB, GPIO12);
gpio_clear(GPIOB, GPIO11);
/* A7105 */
//Disable JTAG and SWD
AFIO_MAPR = (AFIO_MAPR & ~AFIO_MAPR_SWJ_MASK) | AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF;
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO13);
gpio_set(GPIOA, GPIO13);
/* CC2500 */
//Disable JTAG and SWD
AFIO_MAPR = (AFIO_MAPR & ~AFIO_MAPR_SWJ_MASK) | AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF;
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO14);
gpio_set(GPIOA, GPIO14);
/* Includes enable? */
spi_init_master(SPI2,
SPI_CR1_BAUDRATE_FPCLK_DIV_16,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
SPI_CR1_DFF_8BIT,
SPI_CR1_MSBFIRST);
spi_enable_software_slave_management(SPI2);
spi_set_nss_high(SPI2);
spi_enable(SPI2);
}
/*--------------------------------------------------------------------------*/
static void spi_setup(void) {
/* Configure GPIOs: SS=PB12, SCK=PB13, MISO=PB14 and MOSI=PB15
* For now ignore the SS pin so we can use it to time the ISRs
*/
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, /* GPIO4 | */
GPIO13 |
GPIO15 );
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT,
GPIO14);
/* Reset SPI, SPI_CR1 register cleared, SPI is disabled */
spi_reset(SPI2);
/* Explicitly disable I2S in favour of SPI operation */
SPI2_I2SCFGR = 0;
/* Set up SPI in Master mode with:
* Clock baud rate: 1/64 of peripheral clock frequency
* Clock polarity: Idle High
* Clock phase: Data valid on 2nd clock pulse
* Data frame format: 8-bit or 16-bit
* Frame format: MSB First
*/
#if USE_16BIT_TRANSFERS
spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_16BIT, SPI_CR1_MSBFIRST);
#else
spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
#endif
/*
* Set NSS management to software.
*
* Note:
* Setting nss high is very important, even if we are controlling the GPIO
* ourselves this bit needs to be at least set to 1, otherwise the spi
* peripheral will not send any data out.
*/
spi_enable_software_slave_management(SPI2);
spi_set_nss_high(SPI2);
/* Enable SPI2 periph. */
spi_enable(SPI2);
}
void spi_start(void)
{
/* Reset flash chip */
gpio_clear(GPIOD, BL_SPI2_RST);
wait(10);
gpio_set(GPIOD, BL_SPI2_RST);
wait(10);
gpio_set(GPIOD, BL_SPI2_WP);
/* No WriteProtect, Set Chip select to 1(no select) */
gpio_set(GPIOB, BL_SPI2_NSS);
/* Reset and disable SPI */
spi_reset(SPI2);
/* Disable I2S */
SPI2_I2SCFGR = 0;
/* CR1 */
spi_set_clock_phase_0(SPI2); /* CPHA = 0 */
spi_set_clock_polarity_0(SPI2); /* CPOL = 0 */
spi_send_msb_first(SPI2); /* LSB = 0 */
spi_set_full_duplex_mode(SPI2); /* RXONLY = 0 */
spi_set_unidirectional_mode(SPI2); /* BIDI = 0 */
spi_enable_software_slave_management(SPI2); /* SSM = 1 */
spi_set_nss_high(SPI2); /* SSI = 1 */
spi_set_master_mode(SPI2); /* MSTR = 1 */
spi_set_dff_8bit(SPI2); /* DFf = 8 bit */
// spi_enable_crc(SPI2);
/* XXX: Too fast? Maybe DIV_4 will be better? */
spi_set_baudrate_prescaler(SPI2, SPI_CR1_BR_FPCLK_DIV_2);
/* CR2 */
spi_enable_ss_output(SPI2); /* SSOE = 1 */
/* Disable regular interrupt flags */
spi_disable_tx_buffer_empty_interrupt(SPI2);
spi_disable_rx_buffer_not_empty_interrupt(SPI2);
spi_disable_error_interrupt(SPI2);
/* Enabling RX/TX DMA flags */
spi_enable_tx_dma(SPI2);
spi_enable_rx_dma(SPI2);
d_print("REG: %lu:%lu\r\n", SPI_CR1(SPI2), SPI_CR2(SPI2));
spi_enable(SPI2);
}
static void spi_setup(void) {
/* Radio RST */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO0);
/* Configure GPIOs: SS=PA4, SCK=PA5, MISO=PA6 and MOSI=PA7 */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO4);
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO5 |
GPIO7 );
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT,
GPIO6);
/* Reset SPI, SPI_CR1 register cleared, SPI is disabled */
spi_reset(SPI1);
/* Set up SPI in Master mode with:
* Clock baud rate: 1/64 of peripheral clock frequency
* Clock polarity: Idle High
* Clock phase: Data valid on 2nd clock pulse
* Data frame format: 8-bit
* Frame format: MSB First
*/
spi_init_master(SPI1,
SPI_CR1_BAUDRATE_FPCLK_DIV_64,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
SPI_CR1_DFF_8BIT,
SPI_CR1_MSBFIRST);
/*
* Set NSS management to software.
*
* Note:
* Setting nss high is very important, even if we are controlling the GPIO
* ourselves this bit needs to be at least set to 1, otherwise the spi
* peripheral will not send any data out.
*/
spi_enable_software_slave_management(SPI1);
spi_set_nss_high(SPI1);
/* Enable SPI1 periph. */
spi_enable(SPI1);
}
void SPITouch_Init()
{
if(! HAS_TOUCH)
return;
#if 0
/* Enable SPI1 */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_SPI1EN);
/* Enable GPIOA */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
/* Enable GPIOB */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
#endif
/* CS */
gpio_set_mode(_TOUCH_PORT, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, _TOUCH_PIN);
/* PenIRQ is pull-up input*/
gpio_set_mode(_TOUCH_PORT, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_PULL_UPDOWN, _TOUCH_IRQ_PIN);
gpio_set(_TOUCH_PORT, _TOUCH_IRQ_PIN);
CS_LO();
spi_xfer(SPI1, RESET);
CS_HI();
//SPITouch_Calibrate(197312, 147271, -404, -20); /* Read from my Tx */
#if 0
/* SCK, MOSI */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO5 | GPIO7);
/* MISO */
gpio_set_mode(GPIOA, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, GPIO6);
/* Includes enable */
spi_init_master(SPI1,
SPI_CR1_BAUDRATE_FPCLK_DIV_4,
SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_2,
SPI_CR1_DFF_8BIT,
SPI_CR1_MSBFIRST);
spi_enable_software_slave_management(SPI1);
spi_set_nss_high(SPI1);
spi_enable(SPI1);
#endif
}
void spi_setup(void) {
// SPI1 SCK
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_SCK);
// SPI1 MOSI
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_MOSI);
// SPI ChipSelect
gpio_set_mode(MRF_SELECT_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, MRF_SELECT_PIN);
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_SPI1_MISO);
/* Setup SPI parameters. */
spi_init_master(MRF_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_4, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
/* Ignore the stupid NSS pin. */
spi_enable_software_slave_management(MRF_SPI);
spi_enable_ss_output(MRF_SPI);
spi_set_nss_high(MRF_SPI);
/* Finally enable the SPI. */
spi_enable(MRF_SPI);
}
void spi_setup(void) {
/* Configure GPIOs: SS=PB12, SCK=PB13, MISO=PB14 and MOSI=PA15 */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO12 |
GPIO13 |
GPIO15 );
//SPI input
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14);
//BUSSY C7
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7);
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO5 | GPIO6 );
/* Reset SPI, SPI_CR1 register cleared, SPI is disabled */
spi_reset(SPI2);
/* Set up SPI in Master mode with:
* Clock baud rate: 1/16 of peripheral clock frequency
* Clock polarity: Idle Low
* Clock phase: Data valid on 1nd clock pulse
* Data frame format: 8-bit
* Frame format: MSB First
*/
spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_2, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_LSBFIRST);
spi_set_master_mode(SPI2);
spi_enable_software_slave_management(SPI2);
spi_enable_ss_output(SPI2);
spi_set_nss_high(SPI2);
spi_disable_error_interrupt(SPI2);
spi_disable_crc(SPI2);
/* Enable SPI2 periph. */
spi_enable(SPI2);
}
static void spi_setup(void)
{
/* The DOGM128 display is connected to SPI2, so initialise it. */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN);
spi_set_unidirectional_mode(DOGM128_SPI); /* We want to send only. */
spi_disable_crc(DOGM128_SPI); /* No CRC for this slave. */
spi_set_dff_8bit(DOGM128_SPI); /* 8-bit dataword-length */
spi_set_full_duplex_mode(DOGM128_SPI); /* Not receive-only */
/* We want to handle the CS signal in software. */
spi_enable_software_slave_management(DOGM128_SPI);
spi_set_nss_high(DOGM128_SPI);
/* PCLOCK/256 as clock. */
spi_set_baudrate_prescaler(DOGM128_SPI, SPI_CR1_BR_FPCLK_DIV_256);
/* We want to control everything and generate the clock -> master. */
spi_set_master_mode(DOGM128_SPI);
spi_set_clock_polarity_1(DOGM128_SPI); /* SCK idle state high. */
/* Bit is taken on the second (rising edge) of SCK. */
spi_set_clock_phase_1(DOGM128_SPI);
spi_enable_ss_output(DOGM128_SPI);
spi_enable(DOGM128_SPI);
}
void mew_spi_flash_init(void) {
gpio_mode_setup(MEW_FLASH_GPIO_PORT_WP, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, MEW_FLASH_GPIO_PIN_WP);
gpio_set_output_options(MEW_FLASH_GPIO_PORT_WP, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, MEW_FLASH_GPIO_PIN_WP);
gpio_set(MEW_FLASH_GPIO_PORT_WP, MEW_FLASH_GPIO_PIN_WP);
gpio_mode_setup(MEW_FLASH_GPIO_PORT_HOLD, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, MEW_FLASH_GPIO_PIN_HOLD);
gpio_set_output_options(MEW_FLASH_GPIO_PORT_HOLD, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, MEW_FLASH_GPIO_PIN_HOLD);
gpio_set(MEW_FLASH_GPIO_PORT_HOLD, MEW_FLASH_GPIO_PIN_HOLD);
gpio_mode_setup(MEW_FLASH_GPIO_PORT_CS, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, MEW_FLASH_GPIO_PIN_CS);
gpio_set_output_options(MEW_FLASH_GPIO_PORT_CS, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, MEW_FLASH_GPIO_PIN_CS);
gpio_set(MEW_FLASH_GPIO_PORT_CS, MEW_FLASH_GPIO_PIN_CS);
gpio_mode_setup(MEW_FLASH_SPI_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLDOWN, MEW_FLASH_SPI_GPIO_PINS);
gpio_set_output_options(MEW_FLASH_SPI_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, MEW_FLASH_SPI_GPIO_PINS);
gpio_set_af(MEW_FLASH_SPI_GPIO_PORT, MEW_FLASH_SPI_GPIO_AF_NUMBER, MEW_FLASH_SPI_GPIO_PINS);
spi_disable(MEW_FLASH_SPI);
spi_set_master_mode(MEW_FLASH_SPI);
spi_set_baudrate_prescaler(MEW_FLASH_SPI, SPI_CR1_BR_FPCLK_DIV_2);
spi_set_clock_polarity_0(MEW_FLASH_SPI);
spi_set_clock_phase_0(MEW_FLASH_SPI);
spi_set_unidirectional_mode(MEW_FLASH_SPI);
spi_enable_software_slave_management(MEW_FLASH_SPI);
spi_send_msb_first(MEW_FLASH_SPI);
spi_set_nss_high(MEW_FLASH_SPI);
SPI_I2SCFGR(MEW_FLASH_SPI) &= ~SPI_I2SCFGR_I2SMOD;
spi_disable_tx_buffer_empty_interrupt(MEW_FLASH_SPI);
spi_disable_rx_buffer_not_empty_interrupt(MEW_FLASH_SPI);
spi_disable_error_interrupt(MEW_FLASH_SPI);
spi_disable_tx_dma(MEW_FLASH_SPI);
spi_disable_rx_dma(MEW_FLASH_SPI);
spi_set_dff_8bit(MEW_FLASH_SPI);
spi_send_msb_first(MEW_FLASH_SPI);
spi_enable(MEW_FLASH_SPI);
}
void SPI_ProtoInit()
{
/* Enable SPI2 */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN);
/* Enable GPIOA */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
/* Enable GPIOB */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
/* SCK, MOSI */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13 | GPIO15);
/* MISO */
gpio_set_mode(GPIOB, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_FLOAT, GPIO14);
/*CYRF cfg */
/* Reset and CS */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO11);
gpio_clear(GPIOB, GPIO11);
if(Transmitter.module_enable[CYRF6936].port) {
struct mcu_pin *port = &Transmitter.module_enable[CYRF6936];
printf("CYRF port: %08x pin: %04x\n", port->port, port->pin);
//GPIOB.12
gpio_set_mode(Transmitter.module_enable[CYRF6936].port, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, Transmitter.module_enable[CYRF6936].pin);
gpio_set(Transmitter.module_enable[CYRF6936].port, Transmitter.module_enable[CYRF6936].pin);
}
//Disable JTAG and SWD
AFIO_MAPR = (AFIO_MAPR & ~AFIO_MAPR_SWJ_MASK) | AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF;
/* A7105 */
#ifdef PROTO_HAS_A7105
if(Transmitter.module_enable[A7105].port) {
//GPIOA.13
struct mcu_pin *port = &Transmitter.module_enable[A7105];
printf("A7105 port: %08x pin: %04x\n", port->port, port->pin);
gpio_set_mode(Transmitter.module_enable[A7105].port, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, Transmitter.module_enable[A7105].pin);
gpio_set(Transmitter.module_enable[A7105].port, Transmitter.module_enable[A7105].pin);
}
#endif
/* CC2500 */
#ifdef PROTO_HAS_CC2500
if(Transmitter.module_enable[CC2500].port) {
//GPIOA.14
struct mcu_pin *port = &Transmitter.module_enable[CC2500];
printf("CC2500 port: %08x pin: %04x\n", port->port, port->pin);
gpio_set_mode(Transmitter.module_enable[CC2500].port, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, Transmitter.module_enable[CC2500].pin);
gpio_set(Transmitter.module_enable[CC2500].port, Transmitter.module_enable[CC2500].pin);
}
#endif
/* NRF24L01 */
#ifdef PROTO_HAS_NRF24L01
if(Transmitter.module_enable[NRF24L01].port) {
//GPIOA.14
struct mcu_pin *port = &Transmitter.module_enable[NRF24L01];
printf("nRF24L01 port: %08x pin: %04x\n", port->port, port->pin);
gpio_set_mode(Transmitter.module_enable[NRF24L01].port, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, Transmitter.module_enable[NRF24L01].pin);
gpio_set(Transmitter.module_enable[NRF24L01].port, Transmitter.module_enable[NRF24L01].pin);
}
#endif
/* Includes enable? */
spi_init_master(SPI2,
SPI_CR1_BAUDRATE_FPCLK_DIV_16,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
SPI_CR1_DFF_8BIT,
SPI_CR1_MSBFIRST);
spi_enable_software_slave_management(SPI2);
spi_set_nss_high(SPI2);
spi_enable(SPI2);
PROTO_Stubs(0);
}
void spi3_arch_init(void) {
// set the default configuration
spi3_dma.spidr = (uint32_t)&SPI3_DR;
spi3_dma.dma = DMA2;
spi3_dma.rx_chan = DMA_CHANNEL1;
spi3_dma.tx_chan = DMA_CHANNEL2;
spi3_dma.rx_nvic_irq = NVIC_DMA2_CHANNEL1_IRQ;
spi3_dma.tx_nvic_irq = NVIC_DMA2_CHANNEL2_IRQ;
spi3_dma.tx_dummy_buf = 0;
spi3_dma.tx_extra_dummy_dma = FALSE;
spi3_dma.rx_dummy_buf = 0;
spi3_dma.rx_extra_dummy_dma = FALSE;
// set the default configuration
set_default_comm_config(&spi3_dma.comm);
spi3_dma.comm_sig = get_comm_signature(&spi3_dma.comm);
// set init struct, indices and status
spi3.reg_addr = (void *)SPI3;
spi3.init_struct = &spi3_dma;
spi3.trans_insert_idx = 0;
spi3.trans_extract_idx = 0;
spi3.status = SPIIdle;
// Enable SPI3 Periph and gpio clocks
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI3EN);
// Configure GPIOs: SCK, MISO and MOSI
gpio_set_mode(GPIO_BANK_SPI3_SCK, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
GPIO_SPI3_SCK | GPIO_SPI3_MOSI);
gpio_set_mode(GPIO_BANK_SPI3_MISO, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT,
GPIO_SPI3_MISO);
/// @todo disable JTAG so the pins can be used?
// reset SPI
spi_reset(SPI3);
// Disable SPI peripheral
spi_disable(SPI3);
// Force SPI mode over I2S.
SPI3_I2SCFGR = 0;
// configure master SPI.
spi_init_master(SPI3, spi3_dma.comm.br, spi3_dma.comm.cpol, spi3_dma.comm.cpha,
spi3_dma.comm.dff, spi3_dma.comm.lsbfirst);
/*
* Set NSS management to software.
* Setting nss high is very important, even if we are controlling the GPIO
* ourselves this bit needs to be at least set to 1, otherwise the spi
* peripheral will not send any data out.
*/
spi_enable_software_slave_management(SPI3);
spi_set_nss_high(SPI3);
// Enable SPI_3 DMA clock
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA2EN);
// Enable SPI3 periph.
spi_enable(SPI3);
spi_arch_int_enable(&spi3);
}
/**
* Start a new transaction with DMA.
*/
static void spi_start_dma_transaction(struct spi_periph* periph, struct spi_transaction* trans)
{
struct spi_periph_dma *dma;
uint8_t sig = 0x00;
/* Store local copy to notify of the results */
trans->status = SPITransRunning;
periph->status = SPIRunning;
dma = periph->init_struct;
/*
* Check if we need to reconfigure the spi peripheral for this transaction
*/
sig = get_transaction_signature(trans);
if (sig != dma->comm_sig) {
/* A different config is required in this transaction... */
set_comm_from_transaction(&(dma->comm), trans);
/* remember the new conf signature */
dma->comm_sig = sig;
/* apply the new configuration */
spi_disable((uint32_t)periph->reg_addr);
spi_init_master((uint32_t)periph->reg_addr, dma->comm.br, dma->comm.cpol,
dma->comm.cpha, dma->comm.dff, dma->comm.lsbfirst);
spi_enable_software_slave_management((uint32_t)periph->reg_addr);
spi_set_nss_high((uint32_t)periph->reg_addr);
spi_enable((uint32_t)periph->reg_addr);
}
/*
* Select the slave after reconfiguration of the peripheral
*/
if (trans->select == SPISelectUnselect || trans->select == SPISelect) {
SpiSlaveSelect(trans->slave_idx);
}
/* Run the callback AFTER selecting the slave */
if (trans->before_cb != 0) {
trans->before_cb(trans);
}
/*
* Receive DMA channel configuration ----------------------------------------
*
* We always run the receive DMA until the very end!
* This is done so we can use the transfer complete interrupt
* of the RX DMA to signal the end of the transaction.
*
* If we want to receive less than we transmit, a dummy buffer
* for the rx DMA is used after for the remaining data.
*
* In the transmit only case (input_length == 0),
* the dummy is used right from the start.
*/
if (trans->input_length == 0) {
/* run the dummy rx dma for the complete transaction length */
spi_configure_dma(dma->dma, dma->rx_chan, (uint32_t)dma->spidr,
(uint32_t)&(dma->rx_dummy_buf), trans->output_length, trans->dss, FALSE);
} else {
/* run the real rx dma for input_length */
spi_configure_dma(dma->dma, dma->rx_chan, (uint32_t)dma->spidr,
(uint32_t)trans->input_buf, trans->input_length, trans->dss, TRUE);
/* use dummy rx dma for the rest */
if (trans->output_length > trans->input_length) {
/* Enable use of second dma transfer with dummy buffer (cleared in ISR) */
dma->rx_extra_dummy_dma = TRUE;
}
}
dma_set_read_from_peripheral(dma->dma, dma->rx_chan);
dma_set_priority(dma->dma, dma->rx_chan, DMA_CCR_PL_VERY_HIGH);
/*
* Transmit DMA channel configuration ---------------------------------------
*
* We always run the transmit DMA!
* To receive data, the clock must run, so something has to be transmitted.
* If needed, use a dummy DMA transmitting zeros for the remaining length.
*
* In the reveive only case (output_length == 0),
* the dummy is used right from the start.
*/
if (trans->output_length == 0) {
spi_configure_dma(dma->dma, dma->tx_chan, (uint32_t)dma->spidr,
(uint32_t)&(dma->tx_dummy_buf), trans->input_length, trans->dss, FALSE);
} else {
spi_configure_dma(dma->dma, dma->tx_chan, (uint32_t)dma->spidr,
(uint32_t)trans->output_buf, trans->output_length, trans->dss, TRUE);
if (trans->input_length > trans->output_length) {
/* Enable use of second dma transfer with dummy buffer (cleared in ISR) */
dma->tx_extra_dummy_dma = TRUE;
}
}
dma_set_read_from_memory(dma->dma, dma->tx_chan);
dma_set_priority(dma->dma, dma->tx_chan, DMA_CCR_PL_MEDIUM);
/* Enable DMA transfer complete interrupts. */
dma_enable_transfer_complete_interrupt(dma->dma, dma->rx_chan);
dma_enable_transfer_complete_interrupt(dma->dma, dma->tx_chan);
/* Enable DMA channels */
dma_enable_channel(dma->dma, dma->rx_chan);
dma_enable_channel(dma->dma, dma->tx_chan);
/* Enable SPI transfers via DMA */
spi_enable_rx_dma((uint32_t)periph->reg_addr);
spi_enable_tx_dma((uint32_t)periph->reg_addr);
}
void codecInit(void)
{
memset(adcBuffer, 0xaa, sizeof(adcBuffer));
// I2S2 alternate function mapping
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO12 | GPIO13 | GPIO14 | GPIO15);
gpio_set_af(GPIOB, GPIO_AF5, GPIO12 | GPIO13 | GPIO15);
gpio_set_af(GPIOB, GPIO_AF6, GPIO14); // I2S2ext_SD (I2S receive)
gpio_mode_setup(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO6);
gpio_set_af(GPIOC, GPIO_AF5, GPIO6); // MCLK
gpio_set_output_options(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO12 | GPIO13 | GPIO15);
gpio_set_output_options(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, GPIO6);
// Set up SPI1
spi_reset(SPI1);
spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_256, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_16BIT, SPI_CR1_MSBFIRST);
spi_set_nss_high(SPI1);
spi_enable_software_slave_management(SPI1);
spi_enable(SPI1);
// SPI1 alternate function mapping, set CSB signal high output
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO7);
gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO7);
gpio_set(GPIOA, GPIO4);
gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO4);
codecConfig();
// Set up I2S for 48kHz 16-bit stereo.
// The input to the PLLI2S is 1MHz. Division factors are from
// table 126 in the data sheet.
//
// This gives us 1.536MHz SCLK = 16 bits * 2 channels * 48000 Hz
// and 12.288 MHz MCLK = 256 * 48000 Hz.
// With this PLL configuration the actual sampling frequency
// is nominally 47991 Hz.
spi_reset(SPI2);
RCC_PLLI2SCFGR = (3 << 28) | (258 << 6);
RCC_CR |= RCC_CR_PLLI2SON;
while (!(RCC_CR & RCC_CR_PLLI2SRDY));
const unsigned i2sdiv = 3;
SPI_I2SPR(SPI2) = SPI_I2SPR_MCKOE | SPI_I2SPR_ODD | i2sdiv;
SPI_I2SCFGR(SPI2) |= SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE |
(SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT << SPI_I2SCFGR_I2SCFG_LSB);
SPI_I2SCFGR(I2S2_EXT_BASE) = SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE |
(SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE << SPI_I2SCFGR_I2SCFG_LSB);
// Configure the DMA engine to stream data to the DAC.
dma_stream_reset(DMA1, DAC_DMA_STREAM);
dma_set_peripheral_address(DMA1, DAC_DMA_STREAM, (intptr_t)&SPI_DR(SPI2));
dma_set_memory_address(DMA1, DAC_DMA_STREAM, (intptr_t)dacBuffer[0]);
dma_set_memory_address_1(DMA1, DAC_DMA_STREAM, (intptr_t)dacBuffer[1]);
dma_set_number_of_data(DMA1, DAC_DMA_STREAM, BUFFER_SAMPLES);
dma_channel_select(DMA1, DAC_DMA_STREAM, DAC_DMA_CHANNEL);
dma_set_transfer_mode(DMA1, DAC_DMA_STREAM, DMA_SxCR_DIR_MEM_TO_PERIPHERAL);
dma_set_memory_size(DMA1, DAC_DMA_STREAM, DMA_SxCR_MSIZE_16BIT);
dma_set_peripheral_size(DMA1, DAC_DMA_STREAM, DMA_SxCR_PSIZE_16BIT);
dma_enable_memory_increment_mode(DMA1, DAC_DMA_STREAM);
dma_enable_double_buffer_mode(DMA1, DAC_DMA_STREAM);
dma_enable_stream(DMA1, DAC_DMA_STREAM);
// Configure the DMA engine to stream data from the ADC.
dma_stream_reset(DMA1, ADC_DMA_STREAM);
dma_set_peripheral_address(DMA1, ADC_DMA_STREAM, (intptr_t)&SPI_DR(I2S2_EXT_BASE));
dma_set_memory_address(DMA1, ADC_DMA_STREAM, (intptr_t)adcBuffer[0]);
dma_set_memory_address_1(DMA1, ADC_DMA_STREAM, (intptr_t)adcBuffer[1]);
dma_set_number_of_data(DMA1, ADC_DMA_STREAM, BUFFER_SAMPLES);
dma_channel_select(DMA1, ADC_DMA_STREAM, ADC_DMA_CHANNEL);
dma_set_transfer_mode(DMA1, ADC_DMA_STREAM, DMA_SxCR_DIR_PERIPHERAL_TO_MEM);
dma_set_memory_size(DMA1, ADC_DMA_STREAM, DMA_SxCR_MSIZE_16BIT);
dma_set_peripheral_size(DMA1, ADC_DMA_STREAM, DMA_SxCR_PSIZE_16BIT);
dma_enable_memory_increment_mode(DMA1, ADC_DMA_STREAM);
dma_enable_double_buffer_mode(DMA1, ADC_DMA_STREAM);
dma_enable_stream(DMA1, ADC_DMA_STREAM);
dma_enable_transfer_complete_interrupt(DMA1, ADC_DMA_STREAM);
nvic_enable_irq(NVIC_DMA1_STREAM3_IRQ);
nvic_set_priority(NVIC_DMA1_STREAM3_IRQ, 0x80); // 0 is most urgent
// Start transmitting data
spi_enable_rx_dma(I2S2_EXT_BASE);
spi_enable_tx_dma(SPI2);
}
int devspi_create(const struct spi_config *conf)
{
struct dev_spi *spi = NULL;
if (!conf)
return -EINVAL;
if (conf->base == 0)
return -EINVAL;
if ((conf->idx < 0) || (conf->idx > MAX_SPIS))
return -EINVAL;
spi = kalloc(sizeof(struct dev_spi));
if (!spi)
return -ENOMEM;
/* Claim pins for SCK/MOSI/MISO */
gpio_create(&mod_spi, &conf->pio_sck);
gpio_create(&mod_spi, &conf->pio_mosi);
gpio_create(&mod_spi, &conf->pio_miso);
/* Erase spi content */
memset(spi, 0, sizeof(struct dev_spi));
/* Enable clocks */
rcc_periph_clock_enable(conf->rcc);
rcc_periph_clock_enable(conf->dma_rcc);
/* Startup routine */
//spi_disable(conf->base);
/**********************************/
/* reset SPI1 */
spi_reset(conf->base);
/* init SPI1 master */
spi_init_master(conf->base,
SPI_CR1_BAUDRATE_FPCLK_DIV_64,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
SPI_CR1_DFF_8BIT,
SPI_CR1_MSBFIRST);
/* enable SPI1 first */
spi_enable(conf->base);
/**********************************/
#if 0
spi_set_master_mode(conf->base);
spi_set_baudrate_prescaler(conf->base, SPI_CR1_BR_FPCLK_DIV_256); /* TODO: Calculate prescaler from baudrate */
if(conf->polarity == 0)
spi_set_clock_polarity_0(conf->base);
else
spi_set_clock_polarity_1(conf->base);
if(conf->phase == 0) spi_set_clock_phase_0(conf->base);
else
spi_set_clock_phase_1(conf->base);
if(conf->rx_only == 0)
spi_set_full_duplex_mode(conf->base);
else
spi_set_receive_only_mode(conf->base);
if(conf->bidir_mode == 0)
spi_set_unidirectional_mode(conf->base);
else
spi_set_bidirectional_mode(conf->base);
if(conf->dff_16)
spi_set_dff_16bit(conf->base);
else
spi_set_dff_8bit(conf->base);
if(conf->enable_software_slave_management)
spi_enable_software_slave_management(conf->base);
else
spi_disable_software_slave_management(conf->base);
if(conf->send_msb_first)
spi_send_msb_first(conf->base);
else
spi_send_lsb_first(conf->base);
spi_set_nss_high(conf->base);
#endif
/* Set up device struct */
spi->base = conf->base;
spi->irq = conf->irq;
//spi->tx_dma_config = &conf->tx_dma;
//spi->rx_dma_config = &conf->rx_dma;
spi->mutex = mutex_init();
/* Store address in the DEV_SPI array. */
DEV_SPI[conf->idx] = spi;
/* Enable interrupts */
//nvic_set_priority(conf->irq, 1);
//nvic_enable_irq(conf->irq);
return 0;
}
bool Spi_stm32::init(void)
{
bool ret = true;
// SPI IOs configurations
// MISO init
gpio_mode_setup(config_.miso_gpio_config.port,
GPIO_MODE_AF,
config_.miso_gpio_config.pull,
config_.miso_gpio_config.pin
);
gpio_set_af(config_.miso_gpio_config.port,
config_.miso_gpio_config.alt_fct,
config_.miso_gpio_config.pin
);
// MOSI init
gpio_mode_setup(config_.mosi_gpio_config.port,
GPIO_MODE_AF,
config_.mosi_gpio_config.pull,
config_.mosi_gpio_config.pin
);
gpio_set_af(config_.mosi_gpio_config.port,
config_.mosi_gpio_config.alt_fct,
config_.mosi_gpio_config.pin
);
gpio_set_output_options(config_.mosi_gpio_config.port,
GPIO_OTYPE_PP,
GPIO_OSPEED_50MHZ,
config_.mosi_gpio_config.pin
);
// SCK init
gpio_mode_setup(config_.sck_gpio_config.port,
GPIO_MODE_AF,
config_.sck_gpio_config.pull,
config_.sck_gpio_config.pin
);
gpio_set_af(config_.sck_gpio_config.port,
config_.sck_gpio_config.alt_fct,
config_.sck_gpio_config.pin
);
gpio_set_output_options(config_.sck_gpio_config.port,
GPIO_OTYPE_PP,
GPIO_OSPEED_100MHZ,
config_.sck_gpio_config.pin
);
// SPI configuration
switch (config_.spi_device)
{
case STM32_SPI1:
rcc_periph_clock_enable(RCC_SPI1);
break;
case STM32_SPI2:
rcc_periph_clock_enable(RCC_SPI2);
break;
case STM32_SPI3:
rcc_periph_clock_enable(RCC_SPI3);
break;
default:
ret = false;
}
if (config_.ss_mode_hard)
{
spi_disable_software_slave_management(spi_);
spi_enable_ss_output(spi_);
}
// Warning: software slave managment not tested
else
{
spi_enable_software_slave_management(spi_);
}
SPI_CR1(spi_) |= config_.clk_div; // Clock frequency
spi_set_standard_mode(spi_, config_.mode);
spi_enable(spi_);
spi_set_master_mode(spi_);
return ret;
}
