FAR struct spi_dev_s *up_spiinitialize(int port)
{
uint8_t regval;
/* Only the SPI1 interface is supported */
#ifdef CONFIG_DEBUG
if (port != 1)
{
return NULL;
}
#endif
/* Disable SPI */
outp(EZ80_SPI_CTL, 0);
/* Configure GPIOs. For the eZ80F91, the pin mapping for the four SPI pins
* is:
*
* GPIO ALT MASTER SLAVE COMMENT
* ---- ----- ------- ------- ---------------------------------
* PB2 SS INPUT INPUT Managed by board specific logic
* PB3 SCLK OUTPUT INPUT
* PB4 MISO INPUT OUTPUT
* PB5 MOSI OUTPUT INPUT
*
* Select the alternate function for PB2-5:
*/
#ifdef CONFIG_ARCH_CHIP_EZ80F91
regval = inp(EZ80_PB_DDR);
regval |= GPIOB_SPI_PINSET;
outp(EZ80_PB_DDR, regval);
regval = inp(EZ80_PB_ALT1);
regval &= ~GPIOB_SPI_PINSET;
outp(EZ80_PB_ALT1, regval);
regval = inp(EZ80_PB_ALT2);
regval |= GPIOB_SPI_PINSET;
outp(EZ80_PB_ALT2, regval);
#else
# error "Check GPIO initialization for this chip"
#endif
/* Set the initial clock frequency for indentification mode < 400kHz */
spi_setfrequency(NULL, 400000);
/* Enable the SPI.
* NOTE 1: Interrupts are not used in this driver version.
* NOTE 2: Initial mode is mode=0.
*/
outp(EZ80_SPI_CTL, SPI_CTL_SPIEN|SPI_CTL_MASTEREN);
return &g_spidev;
}
FAR struct spi_dev_s *up_spiinitialize(int port)
{
uint32_t regval32;
uint8_t regval8;
int i;
/* Only the SPI1 interface is supported */
#ifdef CONFIG_DEBUG
if (port != 1)
{
return NULL;
}
#endif
/* Configure multiplexed pins as connected on the mcu123.com board:
*
* PINSEL1 P0.17/CAP1.2/SCK1/MAT1.2 Bits 2-3=10 for SCK1
* PINSEL1 P0.18/CAP1.3/MISO1/MAT1.3 Bits 4-5=10 for MISO1
* PINSEL1 P0.19/MAT1.2/MOSI1/CAP1.2 Bits 6-7=10 for MOSI1
* PINSEL1 P0.20/MAT1.3/SSEL1/EINT3 Bits 8-9=10 for P0.20 (we'll control it via GPIO or FIO)
*/
regval32 = getreg32(LPC214X_PINSEL1);
regval32 &= ~(LPC214X_PINSEL1_P017_MASK|LPC214X_PINSEL1_P018_MASK|
LPC214X_PINSEL1_P019_MASK|LPC214X_PINSEL1_P020_MASK);
regval32 |= (LPC214X_PINSEL1_P017_SCK1|LPC214X_PINSEL1_P018_MISO1|
LPC214X_PINSEL1_P019_MOSI1|LPC214X_PINSEL1_P020_GPIO);
putreg32(regval32, LPC214X_PINSEL1);
/* Disable chip select using P0.20 (SSEL1) (low enables) */
regval32 = 1 << 20;
putreg32(regval32, CS_SET_REGISTER);
regval32 |= getreg32(CS_DIR_REGISTER);
putreg32(regval32, CS_DIR_REGISTER);
/* Enable peripheral clocking to SPI1 */
regval32 = getreg32(LPC214X_PCON_PCONP);
regval32 |= LPC214X_PCONP_PCSPI1;
putreg32(regval32, LPC214X_PCON_PCONP);
/* Configure 8-bit SPI mode */
putreg16(LPC214X_SPI1CR0_DSS8BIT|LPC214X_SPI1CR0_FRFSPI, LPC214X_SPI1_CR0);
/* Disable the SSP and all interrupts (we'll poll for all data) */
putreg8(0, LPC214X_SPI1_CR1);
putreg8(0, LPC214X_SPI1_IMSC);
/* Set the initial clock frequency for indentification mode < 400kHz */
spi_setfrequency(NULL, 400000);
/* Enable the SPI */
regval8 = getreg8(LPC214X_SPI1_CR1);
putreg8(regval8 | LPC214X_SPI1CR1_SSE, LPC214X_SPI1_CR1);
for (i = 0; i < 8; i++)
{
(void)getreg16(LPC214X_SPI1_DR);
}
return &g_spidev;
}
FAR struct spi_dev_s *up_spiinitialize(int port)
{
uint32_t regval32;
uint8_t regval8;
int i;
/* Only the SPI1 interface is supported */
#ifdef CONFIG_DEBUG
if (port != 1)
{
return NULL;
}
#endif
/* Configure multiplexed pins as connected on the ZP213X/4XPA board:
*
* PINSEL1 P0.17/CAP1.2/SCK1/MAT1.2 Bits 2-3=10 for SCK1
* PINSEL1 P0.18/CAP1.3/MISO1/MAT1.3 Bits 4-5=10 for MISO1
* (This is the RESET line for the UG_2864AMBAG01,
* although it is okay to configure it as an input too)
* PINSEL1 P0.19/MAT1.2/MOSI1/CAP1.2 Bits 6-7=10 for MOSI1
* PINSEL1 P0.20/MAT1.3/SSEL1/EINT3 Bits 8-9=00 for P0.20 (we'll control it via GPIO or FIO)
* PINSEL1 P0.23/VBUS Bits 12-13=00 for P0.21 (we'll control it via GPIO or FIO)
*/
regval32 = getreg32(LPC214X_PINSEL1);
#ifdef CONFIG_LCD_UG2864AMBAG01
regval32 &= ~(LPC214X_PINSEL1_P017_MASK|LPC214X_PINSEL1_P019_MASK|
LPC214X_PINSEL1_P020_MASK|LPC214X_PINSEL1_P023_MASK);
regval32 |= (LPC214X_PINSEL1_P017_SCK1|LPC214X_PINSEL1_P019_MOSI1|
LPC214X_PINSEL1_P020_GPIO|LPC214X_PINSEL1_P023_GPIO);
#else
regval32 &= ~(LPC214X_PINSEL1_P017_MASK|LPC214X_PINSEL1_P018_MASK
LPC214X_PINSEL1_P019_MASK|LPC214X_PINSEL1_P020_MASK|
LPC214X_PINSEL1_P023_MASK);
regval32 |= (LPC214X_PINSEL1_P017_SCK1|LPC214X_PINSEL1_P018_MISO1|
LPC214X_PINSEL1_P019_MOSI1|LPC214X_PINSEL1_P020_GPIO|
LPC214X_PINSEL1_P023_GPIO);
#endif
putreg32(regval32, LPC214X_PINSEL1);
/* De-select chip select using P0.20 (SSEL1) (low enables) and select A0
* for commands (also low)
*/
regval32 = (1 << 20) | (1 << 23);
putreg32(regval32, CS_SET_REGISTER);
regval32 |= getreg32(CS_DIR_REGISTER);
putreg32(regval32, CS_DIR_REGISTER);
spidbg("CS Pin Config: PINSEL1: %08x PIN: %08x DIR: %08x\n",
getreg32(LPC214X_PINSEL1), getreg32(CS_PIN_REGISTER),
getreg32(CS_DIR_REGISTER));
/* Enable peripheral clocking to SPI1 */
regval32 = getreg32(LPC214X_PCON_PCONP);
regval32 |= LPC214X_PCONP_PCSPI1;
putreg32(regval32, LPC214X_PCON_PCONP);
/* Configure 8-bit SPI mode */
putreg16(LPC214X_SPI1CR0_DSS8BIT|LPC214X_SPI1CR0_FRFSPI, LPC214X_SPI1_CR0);
/* Disable the SSP and all interrupts (we'll poll for all data) */
putreg8(0, LPC214X_SPI1_CR1);
putreg8(0, LPC214X_SPI1_IMSC);
/* Set the initial clock frequency for indentification mode < 400kHz */
spi_setfrequency(NULL, 400000);
/* Enable the SPI */
regval8 = getreg8(LPC214X_SPI1_CR1);
putreg8(regval8 | LPC214X_SPI1CR1_SSE, LPC214X_SPI1_CR1);
for (i = 0; i < 8; i++)
{
(void)getreg16(LPC214X_SPI1_DR);
}
return &g_spidev;
}
