int main(){
printf("srl(0xfffffff0,8):%x\n",srl(0xfffffff0,8));
printf("srl(0x0ffffff0,8):%x\n",srl(0x0ffffff0,8));
printf("sra(0xfffffff0,8):%x\n",sra(0xfffffff0,8));
printf("sra(0x0ffffff0,8):%x\n",sra(0x0ffffff0,8));
return 0;
}
void rgbaint_t::scale_imm_and_clamp(const INT32 scale)
{
mul_imm(scale);
sra(8);
max(0);
min(255);
}
void rgbaint_t::scale_and_clamp(const rgbaint_t& scale)
{
mul(scale);
sra(8);
max(0);
min(255);
}
bool Bitpack_fitss( int64_t n, unsigned width)
{
if (width >= 64)
return true;
int64_t narrow = sra(shl(n, 64-width), 64 - width);
return narrow == n;
}
int main(void) {
int x = 0x11223344;
int k = 1;
int s = sra(x, k);
printf("sra=%2.x", s);
return 0;
}
void rgbaint_t::scale_add_and_clamp(const rgbaint_t& scale, const rgbaint_t& other)
{
mul(scale);
sra(8);
add(other);
max(0);
min(255);
}
int64_t Bitpack_gets(uint64_t word, unsigned width, unsigned lsb)
{
if (width==0) return 0; /* avoid capturing unknown sign bit */
unsigned hi = lsb + width; /* one beyond the most significant bit */
assert(hi <= 64);
return sra(shl(word, 64 - hi), 64 - width);
}
int main(int argc, char *argv[])
{
int i, v, s;
for (i = 1; i < argc; i++) {
v = atoi(argv[i]);
s = 0;
printf("0x%x >> %d: Logical 0x%x, Arithmetic 0x%x\n",
v, s, srl(v,s), sra(v,s));
s = 2;
printf("0x%x >> %d: Logical 0x%x, Arithmetic 0x%x\n",
v, s, srl(v,s), sra(v,s));
s = 31;
printf("0x%x >> %d: Logical 0x%x, Arithmetic 0x%x\n",
v, s, srl(v,s), sra(v,s));
}
return 0;
}
void rgbaint_t::scale_add_and_clamp(const rgbaint_t& scale, const rgbaint_t& other, const rgbaint_t& scale2)
{
rgbaint_t color2(other);
color2.mul(scale2);
mul(scale);
add(color2);
sra(8);
max(0);
min(255);
}
void rgbaint_t::blend(const rgbaint_t& other, UINT8 factor)
{
const VECU32 shift = vec_splat_u32(-16);
const VECS32 scale1 = { factor, factor, factor, factor };
const VECS32 scale2 = { 0x100 - factor, 0x100 - factor, 0x100 - factor, 0x100 - factor, };
VECU32 temp = vec_msum((VECU16)m_value, (VECU16)vec_rl(scale1, shift), vec_splat_u32(0));
temp = vec_msum((VECU16)other.m_value, (VECU16)vec_rl(scale2, shift), temp);
m_value = vec_msum((VECU16)m_value, (VECU16)scale1, vec_mulo((VECU16)other.m_value, (VECU16)scale2));
m_value = vec_add(vec_sl(temp, shift), (VECU32)m_value);
sra(8);
}
OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
OopMapSet* oop_maps = NULL;
// for better readability
const bool must_gc_arguments = true;
const bool dont_gc_arguments = false;
// stub code & info for the different stubs
switch (id) {
case forward_exception_id:
{
oop_maps = generate_handle_exception(id, sasm);
}
break;
case new_instance_id:
case fast_new_instance_id:
case fast_new_instance_init_check_id:
{
Register G5_klass = G5; // Incoming
Register O0_obj = O0; // Outgoing
if (id == new_instance_id) {
__ set_info("new_instance", dont_gc_arguments);
} else if (id == fast_new_instance_id) {
__ set_info("fast new_instance", dont_gc_arguments);
} else {
assert(id == fast_new_instance_init_check_id, "bad StubID");
__ set_info("fast new_instance init check", dont_gc_arguments);
}
if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id) &&
UseTLAB && FastTLABRefill) {
Label slow_path;
Register G1_obj_size = G1;
Register G3_t1 = G3;
Register G4_t2 = G4;
assert_different_registers(G5_klass, G1_obj_size, G3_t1, G4_t2);
// Push a frame since we may do dtrace notification for the
// allocation which requires calling out and we don't want
// to stomp the real return address.
__ save_frame(0);
if (id == fast_new_instance_init_check_id) {
// make sure the klass is initialized
__ ldub(G5_klass, in_bytes(InstanceKlass::init_state_offset()), G3_t1);
__ cmp_and_br_short(G3_t1, InstanceKlass::fully_initialized, Assembler::notEqual, Assembler::pn, slow_path);
}
#ifdef ASSERT
// assert object can be fast path allocated
{
Label ok, not_ok;
__ ld(G5_klass, in_bytes(Klass::layout_helper_offset()), G1_obj_size);
// make sure it's an instance (LH > 0)
__ cmp_and_br_short(G1_obj_size, 0, Assembler::lessEqual, Assembler::pn, not_ok);
__ btst(Klass::_lh_instance_slow_path_bit, G1_obj_size);
__ br(Assembler::zero, false, Assembler::pn, ok);
__ delayed()->nop();
__ bind(not_ok);
__ stop("assert(can be fast path allocated)");
__ should_not_reach_here();
__ bind(ok);
}
#endif // ASSERT
// if we got here then the TLAB allocation failed, so try
// refilling the TLAB or allocating directly from eden.
Label retry_tlab, try_eden;
__ tlab_refill(retry_tlab, try_eden, slow_path); // preserves G5_klass
__ bind(retry_tlab);
// get the instance size
__ ld(G5_klass, in_bytes(Klass::layout_helper_offset()), G1_obj_size);
__ tlab_allocate(O0_obj, G1_obj_size, 0, G3_t1, slow_path);
__ initialize_object(O0_obj, G5_klass, G1_obj_size, 0, G3_t1, G4_t2);
__ verify_oop(O0_obj);
__ mov(O0, I0);
__ ret();
__ delayed()->restore();
__ bind(try_eden);
// get the instance size
__ ld(G5_klass, in_bytes(Klass::layout_helper_offset()), G1_obj_size);
__ eden_allocate(O0_obj, G1_obj_size, 0, G3_t1, G4_t2, slow_path);
__ incr_allocated_bytes(G1_obj_size, G3_t1, G4_t2);
__ initialize_object(O0_obj, G5_klass, G1_obj_size, 0, G3_t1, G4_t2);
__ verify_oop(O0_obj);
__ mov(O0, I0);
__ ret();
__ delayed()->restore();
__ bind(slow_path);
// pop this frame so generate_stub_call can push it's own
__ restore();
}
oop_maps = generate_stub_call(sasm, I0, CAST_FROM_FN_PTR(address, new_instance), G5_klass);
// I0->O0: new instance
}
break;
case counter_overflow_id:
// G4 contains bci, G5 contains method
oop_maps = generate_stub_call(sasm, noreg, CAST_FROM_FN_PTR(address, counter_overflow), G4, G5);
break;
case new_type_array_id:
case new_object_array_id:
{
Register G5_klass = G5; // Incoming
Register G4_length = G4; // Incoming
Register O0_obj = O0; // Outgoing
Address klass_lh(G5_klass, Klass::layout_helper_offset());
assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
assert(Klass::_lh_header_size_mask == 0xFF, "bytewise");
// Use this offset to pick out an individual byte of the layout_helper:
const int klass_lh_header_size_offset = ((BytesPerInt - 1) // 3 - 2 selects byte {0,1,0,0}
- Klass::_lh_header_size_shift / BitsPerByte);
if (id == new_type_array_id) {
__ set_info("new_type_array", dont_gc_arguments);
} else {
__ set_info("new_object_array", dont_gc_arguments);
}
#ifdef ASSERT
// assert object type is really an array of the proper kind
{
Label ok;
Register G3_t1 = G3;
__ ld(klass_lh, G3_t1);
__ sra(G3_t1, Klass::_lh_array_tag_shift, G3_t1);
int tag = ((id == new_type_array_id)
? Klass::_lh_array_tag_type_value
: Klass::_lh_array_tag_obj_value);
__ cmp_and_brx_short(G3_t1, tag, Assembler::equal, Assembler::pt, ok);
__ stop("assert(is an array klass)");
__ should_not_reach_here();
__ bind(ok);
}
#endif // ASSERT
if (UseTLAB && FastTLABRefill) {
Label slow_path;
Register G1_arr_size = G1;
Register G3_t1 = G3;
Register O1_t2 = O1;
assert_different_registers(G5_klass, G4_length, G1_arr_size, G3_t1, O1_t2);
// check that array length is small enough for fast path
__ set(C1_MacroAssembler::max_array_allocation_length, G3_t1);
__ cmp_and_br_short(G4_length, G3_t1, Assembler::greaterUnsigned, Assembler::pn, slow_path);
// if we got here then the TLAB allocation failed, so try
// refilling the TLAB or allocating directly from eden.
Label retry_tlab, try_eden;
__ tlab_refill(retry_tlab, try_eden, slow_path); // preserves G4_length and G5_klass
__ bind(retry_tlab);
// get the allocation size: (length << (layout_helper & 0x1F)) + header_size
__ ld(klass_lh, G3_t1);
__ sll(G4_length, G3_t1, G1_arr_size);
__ srl(G3_t1, Klass::_lh_header_size_shift, G3_t1);
__ and3(G3_t1, Klass::_lh_header_size_mask, G3_t1);
__ add(G1_arr_size, G3_t1, G1_arr_size);
__ add(G1_arr_size, MinObjAlignmentInBytesMask, G1_arr_size); // align up
__ and3(G1_arr_size, ~MinObjAlignmentInBytesMask, G1_arr_size);
__ tlab_allocate(O0_obj, G1_arr_size, 0, G3_t1, slow_path); // preserves G1_arr_size
__ initialize_header(O0_obj, G5_klass, G4_length, G3_t1, O1_t2);
__ ldub(klass_lh, G3_t1, klass_lh_header_size_offset);
__ sub(G1_arr_size, G3_t1, O1_t2); // body length
__ add(O0_obj, G3_t1, G3_t1); // body start
__ initialize_body(G3_t1, O1_t2);
__ verify_oop(O0_obj);
__ retl();
__ delayed()->nop();
__ bind(try_eden);
// get the allocation size: (length << (layout_helper & 0x1F)) + header_size
__ ld(klass_lh, G3_t1);
__ sll(G4_length, G3_t1, G1_arr_size);
__ srl(G3_t1, Klass::_lh_header_size_shift, G3_t1);
__ and3(G3_t1, Klass::_lh_header_size_mask, G3_t1);
__ add(G1_arr_size, G3_t1, G1_arr_size);
__ add(G1_arr_size, MinObjAlignmentInBytesMask, G1_arr_size);
__ and3(G1_arr_size, ~MinObjAlignmentInBytesMask, G1_arr_size);
__ eden_allocate(O0_obj, G1_arr_size, 0, G3_t1, O1_t2, slow_path); // preserves G1_arr_size
__ incr_allocated_bytes(G1_arr_size, G3_t1, O1_t2);
__ initialize_header(O0_obj, G5_klass, G4_length, G3_t1, O1_t2);
__ ldub(klass_lh, G3_t1, klass_lh_header_size_offset);
__ sub(G1_arr_size, G3_t1, O1_t2); // body length
__ add(O0_obj, G3_t1, G3_t1); // body start
__ initialize_body(G3_t1, O1_t2);
__ verify_oop(O0_obj);
__ retl();
__ delayed()->nop();
__ bind(slow_path);
}
if (id == new_type_array_id) {
oop_maps = generate_stub_call(sasm, I0, CAST_FROM_FN_PTR(address, new_type_array), G5_klass, G4_length);
} else {
oop_maps = generate_stub_call(sasm, I0, CAST_FROM_FN_PTR(address, new_object_array), G5_klass, G4_length);
}
// I0 -> O0: new array
}
break;
case new_multi_array_id:
{ // O0: klass
// O1: rank
// O2: address of 1st dimension
__ set_info("new_multi_array", dont_gc_arguments);
oop_maps = generate_stub_call(sasm, I0, CAST_FROM_FN_PTR(address, new_multi_array), I0, I1, I2);
// I0 -> O0: new multi array
}
break;
case register_finalizer_id:
{
__ set_info("register_finalizer", dont_gc_arguments);
// load the klass and check the has finalizer flag
Label register_finalizer;
Register t = O1;
__ load_klass(O0, t);
__ ld(t, in_bytes(Klass::access_flags_offset()), t);
__ set(JVM_ACC_HAS_FINALIZER, G3);
__ andcc(G3, t, G0);
__ br(Assembler::notZero, false, Assembler::pt, register_finalizer);
__ delayed()->nop();
// do a leaf return
__ retl();
__ delayed()->nop();
__ bind(register_finalizer);
OopMap* oop_map = save_live_registers(sasm);
int call_offset = __ call_RT(noreg, noreg,
CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), I0);
oop_maps = new OopMapSet();
oop_maps->add_gc_map(call_offset, oop_map);
// Now restore all the live registers
restore_live_registers(sasm);
__ ret();
__ delayed()->restore();
}
break;
case throw_range_check_failed_id:
{ __ set_info("range_check_failed", dont_gc_arguments); // arguments will be discarded
// G4: index
oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
}
break;
case throw_index_exception_id:
{ __ set_info("index_range_check_failed", dont_gc_arguments); // arguments will be discarded
// G4: index
oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
}
break;
case throw_div0_exception_id:
{ __ set_info("throw_div0_exception", dont_gc_arguments);
oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
}
break;
case throw_null_pointer_exception_id:
{ __ set_info("throw_null_pointer_exception", dont_gc_arguments);
oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
}
break;
case handle_exception_id:
{ __ set_info("handle_exception", dont_gc_arguments);
oop_maps = generate_handle_exception(id, sasm);
}
break;
case handle_exception_from_callee_id:
{ __ set_info("handle_exception_from_callee", dont_gc_arguments);
oop_maps = generate_handle_exception(id, sasm);
}
break;
case unwind_exception_id:
{
// O0: exception
// I7: address of call to this method
__ set_info("unwind_exception", dont_gc_arguments);
__ mov(Oexception, Oexception->after_save());
__ add(I7, frame::pc_return_offset, Oissuing_pc->after_save());
__ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address),
G2_thread, Oissuing_pc->after_save());
__ verify_not_null_oop(Oexception->after_save());
// Restore SP from L7 if the exception PC is a method handle call site.
__ mov(O0, G5); // Save the target address.
__ lduw(Address(G2_thread, JavaThread::is_method_handle_return_offset()), L0);
__ tst(L0); // Condition codes are preserved over the restore.
__ restore();
__ jmp(G5, 0);
__ delayed()->movcc(Assembler::notZero, false, Assembler::icc, L7_mh_SP_save, SP); // Restore SP if required.
}
break;
case throw_array_store_exception_id:
{
__ set_info("throw_array_store_exception", dont_gc_arguments);
oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
}
break;
case throw_class_cast_exception_id:
{
// G4: object
__ set_info("throw_class_cast_exception", dont_gc_arguments);
oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
}
break;
case throw_incompatible_class_change_error_id:
{
__ set_info("throw_incompatible_class_cast_exception", dont_gc_arguments);
oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
}
break;
case slow_subtype_check_id:
{ // Support for uint StubRoutine::partial_subtype_check( Klass sub, Klass super );
// Arguments :
//
// ret : G3
// sub : G3, argument, destroyed
// super: G1, argument, not changed
// raddr: O7, blown by call
Label miss;
__ save_frame(0); // Blow no registers!
__ check_klass_subtype_slow_path(G3, G1, L0, L1, L2, L4, NULL, &miss);
__ mov(1, G3);
__ ret(); // Result in G5 is 'true'
__ delayed()->restore(); // free copy or add can go here
__ bind(miss);
__ mov(0, G3);
__ ret(); // Result in G5 is 'false'
__ delayed()->restore(); // free copy or add can go here
}
case monitorenter_nofpu_id:
case monitorenter_id:
{ // G4: object
// G5: lock address
__ set_info("monitorenter", dont_gc_arguments);
int save_fpu_registers = (id == monitorenter_id);
// make a frame and preserve the caller's caller-save registers
OopMap* oop_map = save_live_registers(sasm, save_fpu_registers);
int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), G4, G5);
oop_maps = new OopMapSet();
oop_maps->add_gc_map(call_offset, oop_map);
restore_live_registers(sasm, save_fpu_registers);
__ ret();
__ delayed()->restore();
}
break;
case monitorexit_nofpu_id:
case monitorexit_id:
{ // G4: lock address
// note: really a leaf routine but must setup last java sp
// => use call_RT for now (speed can be improved by
// doing last java sp setup manually)
__ set_info("monitorexit", dont_gc_arguments);
int save_fpu_registers = (id == monitorexit_id);
// make a frame and preserve the caller's caller-save registers
OopMap* oop_map = save_live_registers(sasm, save_fpu_registers);
int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), G4);
oop_maps = new OopMapSet();
oop_maps->add_gc_map(call_offset, oop_map);
restore_live_registers(sasm, save_fpu_registers);
__ ret();
__ delayed()->restore();
}
break;
case deoptimize_id:
{
__ set_info("deoptimize", dont_gc_arguments);
OopMap* oop_map = save_live_registers(sasm);
int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize));
oop_maps = new OopMapSet();
oop_maps->add_gc_map(call_offset, oop_map);
restore_live_registers(sasm);
DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
assert(deopt_blob != NULL, "deoptimization blob must have been created");
AddressLiteral dest(deopt_blob->unpack_with_reexecution());
__ jump_to(dest, O0);
__ delayed()->restore();
}
break;
case access_field_patching_id:
{ __ set_info("access_field_patching", dont_gc_arguments);
oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
}
break;
case load_klass_patching_id:
{ __ set_info("load_klass_patching", dont_gc_arguments);
oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
}
break;
case load_mirror_patching_id:
{ __ set_info("load_mirror_patching", dont_gc_arguments);
oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
}
break;
case dtrace_object_alloc_id:
{ // O0: object
__ set_info("dtrace_object_alloc", dont_gc_arguments);
// we can't gc here so skip the oopmap but make sure that all
// the live registers get saved.
save_live_registers(sasm);
__ save_thread(L7_thread_cache);
__ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc),
relocInfo::runtime_call_type);
__ delayed()->mov(I0, O0);
__ restore_thread(L7_thread_cache);
restore_live_registers(sasm);
__ ret();
__ delayed()->restore();
}
break;
#if INCLUDE_ALL_GCS
case g1_pre_barrier_slow_id:
{ // G4: previous value of memory
BarrierSet* bs = Universe::heap()->barrier_set();
if (bs->kind() != BarrierSet::G1SATBCTLogging) {
__ save_frame(0);
__ set((int)id, O1);
__ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), I0);
__ should_not_reach_here();
break;
}
__ set_info("g1_pre_barrier_slow_id", dont_gc_arguments);
Register pre_val = G4;
Register tmp = G1_scratch;
Register tmp2 = G3_scratch;
Label refill, restart;
bool with_frame = false; // I don't know if we can do with-frame.
int satb_q_index_byte_offset =
in_bytes(JavaThread::satb_mark_queue_offset() +
PtrQueue::byte_offset_of_index());
int satb_q_buf_byte_offset =
in_bytes(JavaThread::satb_mark_queue_offset() +
PtrQueue::byte_offset_of_buf());
__ bind(restart);
// Load the index into the SATB buffer. PtrQueue::_index is a
// size_t so ld_ptr is appropriate
__ ld_ptr(G2_thread, satb_q_index_byte_offset, tmp);
// index == 0?
__ cmp_and_brx_short(tmp, G0, Assembler::equal, Assembler::pn, refill);
__ ld_ptr(G2_thread, satb_q_buf_byte_offset, tmp2);
__ sub(tmp, oopSize, tmp);
__ st_ptr(pre_val, tmp2, tmp); // [_buf + index] := <address_of_card>
// Use return-from-leaf
__ retl();
__ delayed()->st_ptr(tmp, G2_thread, satb_q_index_byte_offset);
__ bind(refill);
__ save_frame(0);
__ mov(pre_val, L0);
__ mov(tmp, L1);
__ mov(tmp2, L2);
__ call_VM_leaf(L7_thread_cache,
CAST_FROM_FN_PTR(address,
SATBMarkQueueSet::handle_zero_index_for_thread),
G2_thread);
__ mov(L0, pre_val);
__ mov(L1, tmp);
__ mov(L2, tmp2);
__ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
__ delayed()->restore();
}
break;
case g1_post_barrier_slow_id:
{
BarrierSet* bs = Universe::heap()->barrier_set();
if (bs->kind() != BarrierSet::G1SATBCTLogging) {
__ save_frame(0);
__ set((int)id, O1);
__ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), I0);
__ should_not_reach_here();
break;
}
__ set_info("g1_post_barrier_slow_id", dont_gc_arguments);
Register addr = G4;
Register cardtable = G5;
Register tmp = G1_scratch;
Register tmp2 = G3_scratch;
jbyte* byte_map_base = ((CardTableModRefBS*)bs)->byte_map_base;
Label not_already_dirty, restart, refill;
#ifdef _LP64
__ srlx(addr, CardTableModRefBS::card_shift, addr);
#else
__ srl(addr, CardTableModRefBS::card_shift, addr);
#endif
AddressLiteral rs(byte_map_base);
__ set(rs, cardtable); // cardtable := <card table base>
__ ldub(addr, cardtable, tmp); // tmp := [addr + cardtable]
assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code");
__ cmp_and_br_short(tmp, G0, Assembler::notEqual, Assembler::pt, not_already_dirty);
// We didn't take the branch, so we're already dirty: return.
// Use return-from-leaf
__ retl();
__ delayed()->nop();
// Not dirty.
__ bind(not_already_dirty);
// Get cardtable + tmp into a reg by itself
__ add(addr, cardtable, tmp2);
// First, dirty it.
__ stb(G0, tmp2, 0); // [cardPtr] := 0 (i.e., dirty).
Register tmp3 = cardtable;
Register tmp4 = tmp;
// these registers are now dead
addr = cardtable = tmp = noreg;
int dirty_card_q_index_byte_offset =
in_bytes(JavaThread::dirty_card_queue_offset() +
PtrQueue::byte_offset_of_index());
int dirty_card_q_buf_byte_offset =
in_bytes(JavaThread::dirty_card_queue_offset() +
PtrQueue::byte_offset_of_buf());
__ bind(restart);
// Get the index into the update buffer. PtrQueue::_index is
// a size_t so ld_ptr is appropriate here.
__ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, tmp3);
// index == 0?
__ cmp_and_brx_short(tmp3, G0, Assembler::equal, Assembler::pn, refill);
__ ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, tmp4);
__ sub(tmp3, oopSize, tmp3);
__ st_ptr(tmp2, tmp4, tmp3); // [_buf + index] := <address_of_card>
// Use return-from-leaf
__ retl();
__ delayed()->st_ptr(tmp3, G2_thread, dirty_card_q_index_byte_offset);
__ bind(refill);
__ save_frame(0);
__ mov(tmp2, L0);
__ mov(tmp3, L1);
__ mov(tmp4, L2);
__ call_VM_leaf(L7_thread_cache,
CAST_FROM_FN_PTR(address,
DirtyCardQueueSet::handle_zero_index_for_thread),
G2_thread);
__ mov(L0, tmp2);
__ mov(L1, tmp3);
__ mov(L2, tmp4);
__ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
__ delayed()->restore();
}
break;
#endif // INCLUDE_ALL_GCS
case predicate_failed_trap_id:
{
__ set_info("predicate_failed_trap", dont_gc_arguments);
OopMap* oop_map = save_live_registers(sasm);
int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
oop_maps = new OopMapSet();
oop_maps->add_gc_map(call_offset, oop_map);
DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
assert(deopt_blob != NULL, "deoptimization blob must have been created");
restore_live_registers(sasm);
AddressLiteral dest(deopt_blob->unpack_with_reexecution());
__ jump_to(dest, O0);
__ delayed()->restore();
}
break;
default:
{ __ set_info("unimplemented entry", dont_gc_arguments);
__ save_frame(0);
__ set((int)id, O1);
__ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), O1);
__ should_not_reach_here();
}
break;
}
return oop_maps;
}
void show_sra(int x, int k)
{
printf("sra(0x%08X, %d) = 0x%08X\n", x, k, sra(x, k));
}
void execution(int index){
if(test==1) printf("enter EX, with index=%d\n",index);
if(index==0 || index==34){ //NOP or HALT
return;
}
/**R-type instructions**/
else if(index==1){
add(RS,RT,RD);
}
else if(index==2){
addu(RS,RT,RD);
}
else if(index==3){
sub(RS,RT,RD);
}
else if(index==4){
and(RS,RT,RD);
}
else if(index==5){
or(RS,RT,RD);
}
else if(index==6){
xor(RS,RT,RD);
}
else if(index==7){
nor(RS,RT,RD);
}
else if(index==8){
nand(RS,RT,RD);
}
else if(index==9){
slt(RS,RT,RD);
}
else if(index==10){
sll(RT,RD,SHAMT);
}
else if(index==11){
srl(RT,RD,SHAMT);
}
else if(index==12){
sra(RT,RD,SHAMT);
}
/**J-type instructions**/
/*else if(index==13){
jr(RS);
}
else if(index==14){
jj(C);
}
else if(index==15){
jal(C);
}*/
/**I-type instructions**/
else if(index==16){
addi(RS,RT,C);
}
else if(index==17){
addiu(RS,RT,C);
}
else if(index==18){
lw(RS,RT,signedC);
}
else if(index==19){
lh(RS,RT,signedC);
}
else if(index==20){
lhu(RS,RT,C);
}
else if(index==21){
lb(RS,RT,signedC);
}
else if(index==22){
lbu(RS,RT,C);
}
else if(index==23){
sw(RS,RT,signedC);
}
else if(index==24){
sh(RS,RT,signedC);
}
else if(index==25){
sb(RS,RT,signedC);
}
else if(index==26){
lui(RT,C);
}
else if(index==27){
andi(RS,RT,C);
}
else if(index==28){
or(RS,RT,C);
}
else if(index==29){
nor(RS,RT,C);
}
else if(index==30){
slti(RS,RT,C);
}
/*else if(index==31){
beq(RS,RT,signedC);
}
else if(index==32){
bne(RS,RT,signedC);
}
else if(index==33){
bgtz(RS,signedC);
}*/
else{
if(test==1) printf("this is error instruction or is done in ID\n");
}
EX_prev=index;
DM_index=index;
}
// Helper to insert argument slots into the stack.
// arg_slots must be a multiple of stack_move_unit() and <= 0
void MethodHandles::insert_arg_slots(MacroAssembler* _masm,
RegisterOrConstant arg_slots,
int arg_mask,
Register argslot_reg,
Register temp_reg, Register temp2_reg, Register temp3_reg) {
assert(temp3_reg != noreg, "temp3 required");
assert_different_registers(argslot_reg, temp_reg, temp2_reg, temp3_reg,
(!arg_slots.is_register() ? Gargs : arg_slots.as_register()));
#ifdef ASSERT
verify_argslot(_masm, argslot_reg, temp_reg, "insertion point must fall within current frame");
if (arg_slots.is_register()) {
Label L_ok, L_bad;
__ cmp(arg_slots.as_register(), (int32_t) NULL_WORD);
__ br(Assembler::greater, false, Assembler::pn, L_bad);
__ delayed()->nop();
__ btst(-stack_move_unit() - 1, arg_slots.as_register());
__ br(Assembler::zero, false, Assembler::pt, L_ok);
__ delayed()->nop();
__ bind(L_bad);
__ stop("assert arg_slots <= 0 and clear low bits");
__ bind(L_ok);
} else {
assert(arg_slots.as_constant() <= 0, "");
assert(arg_slots.as_constant() % -stack_move_unit() == 0, "");
}
#endif // ASSERT
#ifdef _LP64
if (arg_slots.is_register()) {
// Was arg_slots register loaded as signed int?
Label L_ok;
__ sll(arg_slots.as_register(), BitsPerInt, temp_reg);
__ sra(temp_reg, BitsPerInt, temp_reg);
__ cmp(arg_slots.as_register(), temp_reg);
__ br(Assembler::equal, false, Assembler::pt, L_ok);
__ delayed()->nop();
__ stop("arg_slots register not loaded as signed int");
__ bind(L_ok);
}
#endif
// Make space on the stack for the inserted argument(s).
// Then pull down everything shallower than argslot_reg.
// The stacked return address gets pulled down with everything else.
// That is, copy [sp, argslot) downward by -size words. In pseudo-code:
// sp -= size;
// for (temp = sp + size; temp < argslot; temp++)
// temp[-size] = temp[0]
// argslot -= size;
RegisterOrConstant offset = __ regcon_sll_ptr(arg_slots, LogBytesPerWord, temp3_reg);
// Keep the stack pointer 2*wordSize aligned.
const int TwoWordAlignmentMask = right_n_bits(LogBytesPerWord + 1);
RegisterOrConstant masked_offset = __ regcon_andn_ptr(offset, TwoWordAlignmentMask, temp_reg);
__ add(SP, masked_offset, SP);
__ mov(Gargs, temp_reg); // source pointer for copy
__ add(Gargs, offset, Gargs);
{
Label loop;
__ bind(loop);
// pull one word down each time through the loop
__ ld_ptr(Address(temp_reg, 0), temp2_reg);
__ st_ptr(temp2_reg, Address(temp_reg, offset));
__ add(temp_reg, wordSize, temp_reg);
__ cmp(temp_reg, argslot_reg);
__ brx(Assembler::less, false, Assembler::pt, loop);
__ delayed()->nop(); // FILLME
}
// Now move the argslot down, to point to the opened-up space.
__ add(argslot_reg, offset, argslot_reg);
}
void CPU::exec32(const Instruction32 &insn) {
switch(insn.OP) {
case 0x00: {
uint32_t &rD = r[insn.spform.rD];
uint32_t &rA = r[insn.spform.rA];
uint32_t &rB = r[insn.spform.rB];
switch(insn.spform.func6) {
// nop
case 0x00: /* nothing */ break;
// br{cond}[l] rA
case 0x04: if(conditional(insn.spform.rB)) branch(rA - 4, insn.spform.CU); break;
// add[.c] rD, rA, rB
case 0x08: rD = add(rA, rB, insn.spform.CU); break;
// addc[.c] rD, rA, rB
case 0x09: rD = addc(rA, rB, insn.spform.CU); break;
// sub[.c] rD, rA, rB
case 0x0A: rD = sub(rA, rB, insn.spform.CU); break;
// subc[.c] rD, rA, rB
case 0x0B: rD = subc(rA, rB, insn.spform.CU); break;
// cmp{tcs}.c rA, rB
case 0x0C: cmp(rA, rB, insn.spform.rD & 0x03, insn.spform.CU); break;
// cmpz{tcs}.c rA, rB
case 0x0D: cmp(rA, 0, insn.spform.rD & 0x03, insn.spform.CU); break;
// neg[.c] rD, rA
case 0x0F: rD = sub(0, rA, insn.spform.CU); break;
// and[.c] rD, rA, rB
case 0x10: rD = bit_and(rA, rB, insn.spform.CU); break;
// or[.c] rD, rA, rB
case 0x11: rD = bit_or(rA, rB, insn.spform.CU); break;
// not[.c] rD, rA, rB
case 0x12: rD = bit_xor(rA, ~0, insn.spform.CU); break;
// xor[.c] rD, rA, rB
case 0x13: rD = bit_or(rA, rB, insn.spform.CU); break;
// bitclr[.c] rD, rA, imm5
case 0x14: rD = bit_and(rA, ~(1 << insn.spform.rB), insn.spform.CU); break;
// bitset[.c] rD, rA, imm5
case 0x15: rD = bit_or(rA, 1 << insn.spform.rB, insn.spform.CU); break;
// bittst.c rA, imm5
case 0x16: bit_and(rA, 1 << insn.spform.rB, insn.spform.CU); break;
// bittgl[.c] rA, imm5
case 0x17: rD = bit_xor(rA, 1 << insn.spform.rB, insn.spform.CU); break;
// sll[.c] rA, imm5
case 0x18: rD = sll(rA, insn.spform.rB, insn.spform.CU); break;
// srl[.c] rA, imm5
case 0x1A: rD = srl(rA, insn.spform.rB, insn.spform.CU); break;
// sra[.c] rA, imm5
case 0x1B: rD = sra(rA, insn.spform.rB, insn.spform.CU); break;
// mul rA, rD
case 0x20: ce_op(rA, rD, std::multiplies<int64_t>()); break;
// mulu rA, rD
case 0x21: ce_op(rA, rD, std::multiplies<uint64_t>()); break;
// div rA, rD
case 0x22: ce_op(rA, rD, std::divides<int64_t>()); break;
// divu rA, rD
case 0x23: ce_op(rA, rD, std::divides<uint64_t>()); break;
// mfce{hl} rD[, rA]
case 0x24:
switch(insn.spform.rB) {
case 0x01: rD = CEL; break;
case 0x02: rD = CEH; break;
case 0x03: rD = CEH; rA = CEL; break;
}
break;
// mtce{hl} rD[, rA]
case 0x25:
switch(insn.spform.rB) {
case 0x01: CEL = rD; break;
case 0x02: CEH = rD; break;
case 0x03: CEH = rD; CEL = rA; break;
}
break;
// mfsr rA, Srn
case 0x28: rA = sr[insn.spform.rB];
// mtsr rA, Srn
case 0x29: sr[insn.spform.rB] = rA;
// t{cond}
case 0x2A: T = conditional(insn.spform.rB); break;
// mv{cond} rD, rA
case 0x2B: if(conditional(insn.spform.rB)) rD = rA; break;
// extsb[.c] rD, rA
case 0x2C: rD = sign_extend(rA, 8); if(insn.spform.CU) basic_flags(rD); break;
// extsh[.c] rD, rA
case 0x2D: rD = sign_extend(rA, 16); if(insn.spform.CU) basic_flags(rD); break;
// extzb[.c] rD, rA
case 0x2E: rD = bit_and(rA, 0x000000FF, insn.spform.CU); break;
// extzh[.c] rD, rA
case 0x2F: rD = bit_and(rA, 0x0000FFFF, insn.spform.CU); break;
// slli[.c] rD, rA, imm5
case 0x38: rD = sll(rA, insn.spform.rB, insn.spform.CU); break;
// srli[.c] rD, rA, imm5
case 0x3A: rD = srl(rA, insn.spform.rB, insn.spform.CU); break;
// srai[.c] rD, rA, imm5
case 0x3B: rD = sra(rA, insn.spform.rB, insn.spform.CU); break;
default: debugDump();
}
} break;
case 0x01: {
uint32_t &rD = r[insn.iform.rD];
switch(insn.iform.func3) {
// addi[.c] rD, imm16
case 0x00: rD = add(rD, sign_extend(insn.iform.Imm16, 16), insn.iform.CU); break;
// cmpi.c rD, imm16
case 0x02: cmp(rD, sign_extend(insn.iform.Imm16, 16), 3, insn.iform.CU); break;
// andi.c rD, imm16
case 0x04: rD = bit_and(rD, insn.iform.Imm16, insn.iform.CU); break;
// ori.c rD, imm16
case 0x05: rD = bit_or(rD, insn.iform.Imm16, insn.iform.CU); break;
// ldi rD, imm16
case 0x06: rD = sign_extend(insn.iform.Imm16, 16); break;
default: debugDump();
}
} break;
case 0x02: {
// j[l] imm24
if(insn.jform.LK)
link();
// Update PC
pc &= 0xFC000000;
pc |= (insn.jform.Disp24 << 1) - 4;
} break;
case 0x03: {
uint32_t &rD = r[insn.rixform.rD];
uint32_t &rA = r[insn.rixform.rA];
// Pre-increment
rA += sign_extend(insn.rixform.Imm12, 12);
switch(insn.rixform.func3) {
// lw rD, [rA, imm12]+
case 0x00: rD = miu.readU32(rA); break;
// lh rD, [rA, imm12]+
case 0x01: rD = sign_extend(miu.readU16(rA), 16); break;
// lhu rD, [rA, imm12]+
case 0x02: rD = miu.readU16(rA); break;
// lb rD, [rA, imm12]+
case 0x03: rD = sign_extend(miu.readU8(rA), 8); break;
// sw rD, [rA, imm12]+
case 0x04: miu.writeU32(rA, rD); break;
// sh rD, [rA, imm12]+
case 0x05: miu.writeU16(rA, rD); break;
// lbu rD, [rA, imm12]+
case 0x06: rD = miu.readU8(rA); break;
// sb rD, [rA, imm12]+
case 0x07: miu.writeU8(rA, rD); break;
default: debugDump();
}
} break;
case 0x04: {
// b{cond}[l]
if(conditional(insn.bcform.BC)) {
if(insn.bcform.LK)
link();
pc += sign_extend(((insn.bcform.Disp18_9 << 9) | insn.bcform.Disp8_0) << 1, 20) - 4;
}
} break;
case 0x05: {
uint32_t &rD = r[insn.iform.rD];
uint32_t imm16 = insn.iform.Imm16 << 16;
switch(insn.iform.func3) {
// addis[.c] rD, imm16
case 0x00: rD = add(rD, imm16, insn.iform.CU); break;
// cmpis.c rD, imm16
case 0x02: cmp(rD, imm16, 3, insn.iform.CU); break;
// andis.c rD, imm16
case 0x04: rD = bit_and(rD, imm16, insn.iform.CU); break;
// oris.c rD, imm16
case 0x05: rD = bit_or(rD, imm16, insn.iform.CU); break;
// ldis rD, imm16
case 0x06: rD = imm16; break;
default: debugDump();
}
} break;
case 0x06: {
uint32_t &rD = r[insn.crform.rD];
uint32_t &crA = cr[insn.crform.crA];
switch(insn.crform.CR_OP) {
// mtcr rD, crA
case 0x00: crA = rD; break;
// mfcr rD, crA
case 0x01: rD = crA; break;
// rte
case 0x84: branch(cr5 - 4, false); /* TODO: missing PSR */ break;
default: debugDump();
}
} break;
case 0x07: {
uint32_t &rD = r[insn.rixform.rD];
uint32_t &rA = r[insn.rixform.rA];
switch(insn.rixform.func3) {
// lw rD, [rA]+, imm12
case 0x00: rD = miu.readU32(rA); break;
// lh rD, [rA]+, imm12
case 0x01: rD = sign_extend(miu.readU16(rA), 16); break;
// lhu rD, [rA]+, imm12
case 0x02: rD = miu.readU16(rA); break;
// lb rD, [rA]+, imm12
case 0x03: rD = sign_extend(miu.readU8(rA), 8); break;
// sw rD, [rA]+, imm12
case 0x04: miu.writeU32(rA, rD); break;
// sh rD, [rA]+, imm12
case 0x05: miu.writeU16(rA, rD); break;
// lbu rD, [rA]+, imm12
case 0x06: rD = miu.readU8(rA); break;
// sb rD, [rA]+, imm12
case 0x07: miu.writeU8(rA, rD); break;
default: debugDump();
}
// Post-increment
rA += sign_extend(insn.rixform.Imm12, 12);
} break;
case 0x08: {
// addri[.c] rD, rA, imm14
uint32_t &rD = r[insn.riform.rD];
uint32_t &rA = r[insn.riform.rA];
uint32_t imm14 = sign_extend(insn.riform.Imm14, 14);
rD = add(rA, imm14, insn.riform.CU);
} break;
case 0x0C: {
// andri[.c] rD, rA, imm14
uint32_t &rD = r[insn.riform.rD];
uint32_t &rA = r[insn.riform.rA];
uint32_t imm14 = insn.riform.Imm14;
rD = bit_and(rA, imm14, insn.riform.CU);
} break;
case 0x0D: {
// orri[.c] rD, rA, imm14
uint32_t &rD = r[insn.riform.rD];
uint32_t &rA = r[insn.riform.rA];
uint32_t imm14 = insn.riform.Imm14;
rD = bit_or(rA, imm14, insn.riform.CU);
} break;
case 0x10: {
// lw rD, [rA, imm15]
uint32_t &rD = r[insn.mform.rD];
uint32_t &rA = r[insn.mform.rA];
uint32_t imm15 = sign_extend(insn.mform.Imm15, 15);
rD = miu.readU32(rA + imm15);
} break;
case 0x11: {
// lh rD, [rA, imm15]
uint32_t &rD = r[insn.mform.rD];
uint32_t &rA = r[insn.mform.rA];
uint32_t imm15 = sign_extend(insn.mform.Imm15, 15);
rD = sign_extend(miu.readU16(rA + imm15), 16);
} break;
case 0x12: {
// lhu rD, [rA, imm15]
uint32_t &rD = r[insn.mform.rD];
uint32_t &rA = r[insn.mform.rA];
uint32_t imm15 = sign_extend(insn.mform.Imm15, 15);
rD = miu.readU16(rA + imm15);
} break;
case 0x13: {
// lb rD, [rA, imm15]
uint32_t &rD = r[insn.mform.rD];
uint32_t &rA = r[insn.mform.rA];
uint32_t imm15 = sign_extend(insn.mform.Imm15, 15);
rD = sign_extend(miu.readU8(rA + imm15), 8);
} break;
case 0x14: {
// sw rD, [rA, imm15]
uint32_t &rD = r[insn.mform.rD];
uint32_t &rA = r[insn.mform.rA];
uint32_t imm15 = sign_extend(insn.mform.Imm15, 15);
miu.writeU32(rA + imm15, rD);
} break;
case 0x15: {
// sh rD, [rA, imm15]
uint32_t &rD = r[insn.mform.rD];
uint32_t &rA = r[insn.mform.rA];
uint32_t imm15 = sign_extend(insn.mform.Imm15, 15);
miu.writeU16(rA + imm15, rD);
} break;
case 0x16: {
// lbu rD, [rA, imm15]
uint32_t &rD = r[insn.mform.rD];
uint32_t &rA = r[insn.mform.rA];
uint32_t imm15 = sign_extend(insn.mform.Imm15, 15);
rD = miu.readU8(rA + imm15);
} break;
case 0x17: {
// sb rD, [rA, imm15]
uint32_t &rD = r[insn.mform.rD];
uint32_t &rA = r[insn.mform.rA];
uint32_t imm15 = sign_extend(insn.mform.Imm15, 15);
miu.writeU8(rA + imm15, rD);
} break;
case 0x18:
// cache op, [rA, imm15]
break;
default: debugDump();
}
}
EXC_TYPE StreamRelayIMAP4Msg (const IMAP4ACCOUNTDEF& accDef,
ISockioInterface& CBSock,
const UINT32 ulMsgID,
const BOOLEAN fIsUID,
const IMAP4RELAYFLAGS& rlyFlags,
IMsgRelayStream& rlyStream)
{
IMAP4FASTMSGINFO fmInfo;
EXC_TYPE exc=imap4FetchMsgFastInfo(CBSock, NULL, fIsUID, ulMsgID, fmInfo, accDef.ulRspTimeout);
if (exc != EOK)
return exc;
const UINT32 ulMsgUID=fmInfo.ulMsgUID;
const UINT32 ulMsgSeqNo=fmInfo.ulMsgSeqNo;
if (rlyFlags.m_fCheckUID != 0)
{
TCHAR szUID[MAX_DWORD_DISPLAY_LENGTH+2]=_T("");
dword_to_argument(ulMsgUID, szUID);
if ((exc=rlyStream.HandleProtoState(szPOP3UidlCmd, ulMsgSeqNo, szUID)) != EOK)
{
if (EWARNINGEXIT == exc)
{
EXC_TYPE err=imap4DeleteMsgSync(CBSock, NULL, ulMsgUID, TRUE, TRUE, NULL, NULL, accDef.ulRspTimeout);
if (err != EOK)
return rlyStream.LogMsgf(IMsgRelayStream::IMSGRLY_PROTO_WARNING, err,
_T("StreamRelayIMAP4Msg - cannot (0x%08x) mark %lu for deletion from \"%s@%s\""),
err, ulMsgUID, accDef.lpszIMAP4UID, accDef.lpszIMAP4Host);
}
return exc;
}
}
if (rlyFlags.m_fCheckSize != 0)
{
TCHAR szMsgSize[MAX_DWORD_DISPLAY_LENGTH+2]=_T("");
dword_to_argument((DWORD) fmInfo.ulMsgSize, szMsgSize);
if ((exc=rlyStream.HandleProtoState(szPOP3ListCmd, ulMsgSeqNo, szMsgSize)) != EOK)
return exc;
}
if ((exc=rlyStream.HandleProtoState(szPOP3TopCmd, ulMsgSeqNo, _T(""))) != EOK)
return exc;
CRFC822MsgExtractor msgEx;
STREAMRLYCFNARGS sra(ulMsgSeqNo, ulMsgUID, accDef, rlyFlags, msgEx, rlyStream);
if (rlyFlags.m_fParseMsg != 0)
{
if ((exc=msgEx.SetDecodeParams(rlyParseCfn, (LPVOID) &sra)) != EOK)
return rlyStream.LogMsgf(IMsgRelayStream::IMSGRLY_PROTO_WARNING, exc,
_T("StreamRelayIMAP4Msg - cannot (0x%08x) init msg %lu parser for \"%s@%s\""),
exc, ulMsgUID, accDef.lpszIMAP4UID, accDef.lpszIMAP4Host);
}
if ((exc=imap4FetchMsgBodySync(CBSock, NULL, TRUE, ulMsgUID, rlyFetchCfn, (LPVOID) &sra, accDef.ulRspTimeout)) != EOK)
return rlyStream.LogMsgf(IMsgRelayStream::IMSGRLY_PROTO_WARNING, exc,
_T("StreamRelayIMAP4Msg - cannot (0x%08x) %s %lu %s from \"%s@%s\""),
exc, szIMAP4FetchCmd, ulMsgUID, IMAP4_BODY, accDef.lpszIMAP4UID, accDef.lpszIMAP4Host);
if (rlyFlags.m_fParseMsg != 0)
{
// see if have any body "leftovers"
CRFC822HdrData& bodyTrail=sra.m_BodyTrail;
if (bodyTrail.GetHdrLen() != 0)
{
if ((exc=ProcessBodyTrail(ulMsgUID, accDef, bodyTrail, sra.m_ulCurLine, rlyStream, msgEx)) != EOK)
return exc;
}
}
// generate fake end of message
int wLen=rlyStream.Write(_T(".\r\n"));
if (wLen != 3)
return rlyStream.LogMsgf(IMsgRelayStream::IMSGRLY_PROTO_WARNING, ENOTCONNECTION,
_T("StreamRelayIMAP4Msg - conn. lost (%d) while send msg %lu EOM from \"%s@%s\""),
wLen, ulMsgUID, accDef.lpszIMAP4UID, accDef.lpszIMAP4Host);
if ((exc=rlyStream.HandleProtoState(szPOP3RetrCmd, ulMsgSeqNo, _T(""))) != EOK)
return exc;
if (rlyFlags.m_fQueryDel != 0)
{
if ((exc=rlyStream.HandleProtoState(szPOP3DeleCmd, ulMsgSeqNo, _T(""))) != EOK)
return exc;
if ((exc=imap4DeleteMsgSync(CBSock, NULL, ulMsgUID, TRUE, TRUE, NULL, NULL, accDef.ulRspTimeout)) != EOK)
return rlyStream.LogMsgf(IMsgRelayStream::IMSGRLY_PROTO_WARNING, exc,
_T("StreamRelayIMAP4Msg - cannot (0x%08x) mark %lu for deletion from \"%s@%s\""),
exc, ulMsgUID, accDef.lpszIMAP4UID, accDef.lpszIMAP4Host);
}
return EOK;
}
