static IMG_VOID DeAssertGpuResetSignal(IMG_VOID)
{
if(sunxi_periph_reset_deassert(gpu_ctrl_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to release gpu control reset!"));
}
if(sunxi_periph_reset_deassert(gpu_core_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to release gpu reset!"));
}
}
int os_clk_reset_deassert(struct clk *clk)
{
#ifdef VFE_CLK
return sunxi_periph_reset_deassert(clk);
#else
return 0;
#endif
}
static IMG_VOID DeAssertResetSignal(struct aw_clk_data clk_data)
{
if(clk_data.need_reset)
{
if(sunxi_periph_reset_deassert(clk_data.clk_handle))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to release gpu %s clock reset!", clk_data.clk_name));
}
}
}
static void clktest_process(void)
{
int i,j,enabled,command = 0xff;
unsigned long rate;
struct clk *cur_clk=NULL;
struct clk *parent_clk=NULL;
int start = simple_strtoul(testclk_priv.start,NULL,0);
if(start ==1)
{
if(!strcmp(testclk_priv.command,"getparents"))
command = 1;
else if(!strcmp(testclk_priv.command,"getparent"))
command = 2;
else if(!strcmp(testclk_priv.command,"setparent"))
command = 3;
else if(!strcmp(testclk_priv.command,"getrate"))
command = 4;
else if(!strcmp(testclk_priv.command,"setrate"))
command = 5;
else if(!strcmp(testclk_priv.command,"is_enabled"))
command = 6;
else if(!strcmp(testclk_priv.command,"disable"))
command = 7;
else if(!strcmp(testclk_priv.command,"enable"))
command = 8;
else if(!strcmp(testclk_priv.command,"dumpreg"))
command = 9;
else if(!strcmp(testclk_priv.command,"assert"))
command = 10;
else if(!strcmp(testclk_priv.command,"deassert"))
command = 11;
else
{
printk("Error Not support command %s\n",testclk_priv.command);
command = 0xff;
}
if((command != 0xff) && (command != 9) )
{
cur_clk = clk_get(NULL,testclk_priv.name);
if(!cur_clk || IS_ERR(cur_clk))
{
cur_clk = NULL;
printk("Error Found clk %s\n",testclk_priv.name);
strcpy(testclk_priv.info,"Error");
return;
}
switch(command)
{
case 1://getparents
{
j =0;
memset(testclk_priv.info,0x0,sizeof(testclk_priv.info));
for(i=0;i<cur_clk->num_parents;i++)
{
memcpy(&testclk_priv.info[j],cur_clk->parent_names[i],strlen(cur_clk->parent_names[i]));
j+=strlen(cur_clk->parent_names[i]);
testclk_priv.info[j] = ' ';
j++;
}
testclk_priv.info[j]=0;
break;
}
case 2: //getparent
{
parent_clk = clk_get_parent(cur_clk);
if(!parent_clk || IS_ERR(parent_clk))
{
printk("Error Found parent of %s\n",cur_clk->name);
strcpy(testclk_priv.info,"Error");
}
else
strcpy(testclk_priv.info,parent_clk->name);
break;
}
case 3: //setparent
{
if(cur_clk->parent)
{
parent_clk = clk_get(NULL,testclk_priv.param);
if(!parent_clk || IS_ERR(parent_clk))
{
printk("Error Found parent %s\n",testclk_priv.param);
strcpy(testclk_priv.info,"Error");
}
else
{
clk_set_parent(cur_clk,parent_clk);
strcpy(testclk_priv.info,cur_clk->parent->name);
clk_put(parent_clk);
}
}
else
strcpy(testclk_priv.info,"Error");
break;
}
case 4://getrate
{
rate = clk_get_rate(cur_clk);
if(rate)
sprintf(testclk_priv.info,"%d",(unsigned int)rate);
else
strcpy(testclk_priv.info,"Error");
break;
}
case 5://setrate
{
rate = simple_strtoul(testclk_priv.param,NULL,0);
if(rate)
{
clk_set_rate(cur_clk,rate);
sprintf(testclk_priv.info,"%d",(unsigned int)rate);
}
else
strcpy(testclk_priv.info,"Error");
break;
}
case 6://is_enabled
{
if (!cur_clk->ops->is_enabled)
enabled = cur_clk->enable_count ? 1 : 0;
else
enabled = cur_clk->ops->is_enabled(cur_clk->hw);
if(enabled)
strcpy(testclk_priv.info,"enabled");
else
strcpy(testclk_priv.info,"disabled");
break;
}
case 7://disable
{
if (!cur_clk->ops->is_enabled)
enabled = cur_clk->enable_count ? 1 : 0;
else
enabled = cur_clk->ops->is_enabled(cur_clk->hw);
if(enabled)
clk_disable_unprepare(cur_clk);
strcpy(testclk_priv.info,"disabled");
break;
}
case 8://enable
{
clk_prepare_enable(cur_clk);
strcpy(testclk_priv.info,"enabled");
break;
}
case 10://assert
{
if(!sunxi_periph_reset_assert(cur_clk))
strcpy(testclk_priv.info,"asserted");
else
strcpy(testclk_priv.info,"failed");
break;
}
case 11://deassert
{
if(!sunxi_periph_reset_deassert(cur_clk))
strcpy(testclk_priv.info,"deasserted");
else
strcpy(testclk_priv.info,"failed");
break;
}
default:
break;
}
if(cur_clk)
clk_put(cur_clk);
}
else if( command == 9)
{
clktest_reg_dump();
strcpy(testclk_priv.info,"OK");
}
}
}
static inline void sw_uart_reset(struct sw_uart_port *sw_uport)
{
sunxi_periph_reset_assert(sw_uport->mclk);
sunxi_periph_reset_deassert(sw_uport->mclk);
}
void ss_reset(void)
{
SS_ENTER();
sunxi_periph_reset_assert(ss_dev->mclk);
sunxi_periph_reset_deassert(ss_dev->mclk);
}
/*!
******************************************************************************
@Function EnableSystemClocks
@Description Setup up the clocks for the graphics device to work.
@Return PVRSRV_ERROR
******************************************************************************/
PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
if (!psSysSpecData->bSysClocksOneTimeInit)
{
sgx_regulator = regulator_get(NULL,"vdd-gpu");
if (IS_ERR(sgx_regulator))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get sgx regulator!"));
}
ParseSysconfigFex();
/* Set up PLL and clock parents */
gpu_pll_clk = clk_get(NULL,PLL_GPU_CLK);
if (!gpu_pll_clk || IS_ERR(gpu_pll_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get gpu pll handle!"));
}
gpu_core_clk = clk_get(NULL, GPUCORE_CLK);
if (!gpu_core_clk || IS_ERR(gpu_core_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get gpu core clock handle!"));
}
gpu_mem_clk = clk_get(NULL, GPUMEM_CLK);
if (!gpu_mem_clk || IS_ERR(gpu_mem_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get gpu mem clock handle!"));
}
gpu_hyd_clk = clk_get(NULL, GPUHYD_CLK);
if (!gpu_hyd_clk || IS_ERR(gpu_hyd_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get gpu hyd clock handle!"));
}
if (clk_set_parent(gpu_core_clk, gpu_pll_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to set the parent of gpu core clock!"));
}
if (clk_set_parent(gpu_mem_clk, gpu_pll_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to set the parent of gpu mem clock!"));
}
if (clk_set_parent(gpu_hyd_clk, gpu_pll_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to set the parent of gpu hyd clock!"));
}
/* set the frequency of gpu pll */
SetGpuFreq(dvfs_level);
mutex_init(&psSysSpecData->sPowerLock);
psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE;
mutex_init(&dvfs_lock);
#ifdef CONFIG_CPU_BUDGET_THERMAL
register_budget_cooling_notifier(&sgx_throttle_notifier);
#endif /* CONFIG_CPU_BUDGET_THERMAL */
sysfs_create_group(&gpsPVRLDMDev->dev.kobj, &gpu_attribute_group);
}
/* enable gpu power */
if (regulator_enable(sgx_regulator))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to enable gpu power!"));
}
/* delay for gpu power stability */
mdelay(2);
/* set gpu power off gating invalid */
sunxi_smc_writel(0, SUNXI_R_PRCM_VBASE + 0x118);
if(sunxi_periph_reset_deassert(gpu_hyd_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to release gpu reset!"));
}
return PVRSRV_OK;
}
