void uart_open(uint8_t port)
{
Usart* usart = get_usart(port);
if (0 == port) {
// IO is initialized in board init
// Enable interrupt with priority higher than USB
NVIC_SetPriority((IRQn_Type) USART_ID_0, USART_INT_LEVEL_0);
NVIC_EnableIRQ((IRQn_Type) USART_ID_0);
NVIC_SetPriority((IRQn_Type) USART_ID_1, USART_INT_LEVEL_1);
NVIC_EnableIRQ((IRQn_Type) USART_ID_1);
// Initialize it in RS232 mode.
pmc_enable_periph_clk(USART_ID_0);
USART_ENABLE_0();
} else if (1 == port) {
// IO is initialized in board init
// Enable interrupt with priority higher than USB
NVIC_SetPriority((IRQn_Type) USART_ID_1, USART_INT_LEVEL_1);
NVIC_EnableIRQ((IRQn_Type) USART_ID_1);
// Initialize it in RS232 mode.
pmc_enable_periph_clk(USART_ID_1);
USART_ENABLE_1();
} else {
return;
}
if (usart_init_rs232(usart, &usart_options,
sysclk_get_peripheral_hz())) {
return;
}
// Enable both RX and TX
usart_enable_tx(usart);
usart_enable_rx(usart);
// Enable interrupts
usart_enable_interrupt(usart, US_IER_RXRDY | US_IER_TXRDY);
}
/**
* \brief Configure USART in synchronous mode.
*
* \param ul_ismaster 1 for master, 0 for slave.
* \param ul_baudrate Baudrate for synchronous communication.
*
*/
static void configure_usart(uint32_t ul_ismaster, uint32_t ul_baudrate)
{
sam_usart_opt_t usart_console_settings = {
0,
US_MR_CHRL_8_BIT,
US_MR_PAR_NO,
US_MR_NBSTOP_1_BIT,
US_MR_CHMODE_NORMAL,
/* This field is only used in IrDA mode. */
0
};
usart_console_settings.baudrate = ul_baudrate;
/* Enable the peripheral clock in the PMC. */
sysclk_enable_peripheral_clock(BOARD_ID_USART);
/* Configure USART in SYNC. master or slave mode. */
if (ul_ismaster) {
usart_init_sync_master(BOARD_USART, &usart_console_settings, sysclk_get_peripheral_hz());
} else {
usart_init_sync_slave(BOARD_USART, &usart_console_settings);
}
/* Disable all the interrupts. */
usart_disable_interrupt(BOARD_USART, ALL_INTERRUPT_MASK);
/* Enable TX & RX function. */
usart_enable_tx(BOARD_USART);
usart_enable_rx(BOARD_USART);
/* Configure and enable interrupt of USART. */
NVIC_EnableIRQ(USART_IRQn);
}
/**
* \brief Set up a USART in SPI master mode device.
*
* The returned device descriptor structure must be passed to the driver
* whenever that device should be used as current slave device.
*
* \param p_usart Base address of the USART instance.
* \param device Pointer to usart device struct that should be initialized.
* \param flags USART configuration flags. Common flags for all
* implementations are the usart modes, which should be SPI_MODE_0,
* SPI_MODE_1, SPI_MODE_2, SPI_MODE_3.
* \param baud_rate Baud rate for communication with slave device in Hz.
* \param sel_id Board specific select id.
*/
void usart_spi_setup_device(Usart *p_usart, struct usart_spi_device *device,
spi_flags_t flags, unsigned long baud_rate,
board_spi_select_id_t sel_id)
{
usart_spi_opt_t opt;
/* avoid Cppcheck Warning */
UNUSED(device);
UNUSED(sel_id);
/* Basic usart SPI configuration. */
opt.baudrate = baud_rate;
opt.char_length = US_MR_CHRL_8_BIT;
opt.spi_mode = flags;
opt.channel_mode = US_MR_CHMODE_NORMAL;
/* Initialize the USART module as SPI master. */
#if (SAM4L)
usart_init_spi_master(p_usart, &opt, sysclk_get_pba_hz());
#else
usart_init_spi_master(p_usart, &opt, sysclk_get_peripheral_hz());
#endif
usart_enable_rx(p_usart);
usart_enable_tx(p_usart);
}
/**
* \brief Send the files through XMODEM protocol
*
* \param usart Base address of the USART instance.
* \param p_buffer Pointer to send buffer
* \param ul_length transfer file size
*/
void xmodem_send_file(usart_if usart, int8_t *p_buffer, uint32_t ul_length)
{
uint8_t c_char, uc_sno = 1;
int32_t l_done;
uint32_t ul_timeout = (sysclk_get_peripheral_hz() / 10);
if (ul_length & (PKTLEN_128-1)) {
ul_length += PKTLEN_128;
ul_length &= ~(PKTLEN_128-1);
}
/* Startup synchronization... */
/* Wait to receive a NAK or 'C' from receiver. */
l_done = 0;
while(!l_done) {
usart_serial_getchar(usart, &c_char);
switch (c_char) {
case XMDM_NAK:
l_done = 1;
break;
case 'C':
l_done = 1;
break;
case 'q': /* ELS addition, not part of XMODEM spec. */
return;
default:
break;
}
}
l_done = 0;
uc_sno = 1;
while (!l_done) {
c_char = xmodem_send_packet(usart, (uint8_t *)p_buffer, uc_sno);
switch(c_char) {
case XMDM_ACK:
++uc_sno;
ul_length -= PKTLEN_128;
p_buffer += PKTLEN_128;
break;
case XMDM_NAK:
break;
case XMDM_CAN:
case XMDM_EOT:
default:
l_done = -1;
break;
}
if (!ul_length) {
usart_serial_putchar(usart, XMDM_EOT);
/* Flush the ACK */
usart_serial_getchar(usart, &c_char);
break;
}
}
}
/*
* Init TWI interface for WM8731 .
*/
static void init_twi_wm8731(void)
{
twi_options_t opt;
/* Configure the options of TWI driver */
opt.master_clk = sysclk_get_peripheral_hz();
opt.speed = TWI_WM8731_CLK;
opt.chip = WM8731_SLAVE_ADDRESS;
twi_master_setup(TWI_WM8731, &opt);
}
/*
* @fn nm_bus_init
* @brief Initialize the bus wrapper
* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
*/
sint8 nm_bus_init(void *pvinit)
{
sint8 result = M2M_SUCCESS;
#ifdef CONF_WINC_USE_I2C
twihs_options_t opt;
/* Enable the peripheral clock for TWI */
pmc_enable_periph_clk(CONF_WINC_I2C_ID);
/* Configure the options of TWI driver */
opt.master_clk = sysclk_get_peripheral_hz();
opt.speed = CONF_WINC_TWIHS_CLOCK;
if (twihs_master_init(CONF_WINC_I2C, &opt) != TWIHS_SUCCESS) {
M2M_ERR("-E-\tTWI master initialization failed.\r");
while (1) {
/* Capture error */
}
}
#elif CONF_WINC_USE_SPI
/* Configure SPI pins. */
ioport_set_pin_mode(CONF_WINC_SPI_MISO_GPIO, CONF_WINC_SPI_MISO_FLAGS);
ioport_set_pin_mode(CONF_WINC_SPI_MOSI_GPIO, CONF_WINC_SPI_MOSI_FLAGS);
ioport_set_pin_mode(CONF_WINC_SPI_CLK_GPIO, CONF_WINC_SPI_CLK_FLAGS);
ioport_set_pin_mode(CONF_WINC_SPI_CS_GPIO, CONF_WINC_SPI_CS_FLAGS);
ioport_disable_pin(CONF_WINC_SPI_MISO_GPIO);
ioport_disable_pin(CONF_WINC_SPI_MOSI_GPIO);
ioport_disable_pin(CONF_WINC_SPI_CLK_GPIO);
ioport_disable_pin(CONF_WINC_SPI_CS_GPIO);
spi_enable_clock(CONF_WINC_SPI);
spi_disable(CONF_WINC_SPI);
spi_reset(CONF_WINC_SPI);
spi_set_master_mode(CONF_WINC_SPI);
spi_disable_mode_fault_detect(CONF_WINC_SPI);
spi_set_peripheral_chip_select_value(CONF_WINC_SPI, CONF_WINC_SPI_NPCS);
spi_set_clock_polarity(CONF_WINC_SPI,
CONF_WINC_SPI_NPCS, CONF_WINC_SPI_POL);
spi_set_clock_phase(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_PHA);
spi_set_bits_per_transfer(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(CONF_WINC_SPI, CONF_WINC_SPI_NPCS,
(sysclk_get_cpu_hz() / CONF_WINC_SPI_CLOCK));
spi_set_transfer_delay(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_DLYBS,
CONF_WINC_SPI_DLYBCT);
spi_enable(CONF_WINC_SPI);
nm_bsp_reset();
#endif
return result;
}
/**
* \brief Receive the files through XMODEM protocol
*
* \param usart Base address of the USART instance.
* \param p_buffer Pointer to receive buffer
*
* \return received file size
*/
uint32_t xmodem_receive_file(usart_if usart, int8_t *p_buffer)
{
uint32_t ul_timeout;
uint8_t c_char;
int32_t l_done;
uint8_t uc_sno = 0x01;
uint32_t ul_size = 0;
/* Wait and put 'C' till start XMODEM transfer */
while (1) {
usart_serial_putchar(usart, 'C');
ul_timeout = (sysclk_get_peripheral_hz() / 10);
while (!(usart_serial_is_rx_ready(usart)) && ul_timeout) {
ul_timeout--;
}
if (usart_serial_is_rx_ready(usart)) {
break;
}
}
/* Begin to receive the data */
l_done = 0;
while (l_done == 0) {
usart_serial_getchar(usart, &c_char);
switch (c_char) {
/* Start of transfer */
case XMDM_SOH:
l_done = xmodem_get_packet(usart, p_buffer+ul_size, uc_sno);
if (l_done == 0) {
uc_sno++;
ul_size += PKTLEN_128;
}
usart_serial_putchar(usart, XMDM_ACK);
break;
/* End of transfer */
case XMDM_EOT:
usart_serial_putchar(usart, XMDM_ACK);
l_done = ul_size;
break;
case XMDM_CAN:
case XMDM_ESC:
default:
l_done = -1;
break;
}
}
return ul_size;
}
spi_p spi_new_instance(Spi * spi_base, uint8_t spi_chip_sel, uint32_t spi_freq, uint8_t spi_mode, uint8_t buffer_size, void(*handler_call_back )(spi_p, uint8_t))
{
_spi_base = spi_base;
if (!spi_is_enabled(_spi_base)) {
_spi_init_base(spi_base);
}
spi_p _spi = malloc(sizeof *_spi);
_spi->_call_back = handler_call_back;
_spi->_cs_pin = spi_chip_sel;
_spi->_spi_rx_fifo_desc = (fifo_desc_t *)malloc(sizeof(fifo_desc_t));
_spi->_spi_tx_fifo_desc = (fifo_desc_t *)malloc(sizeof(fifo_desc_t));
union spi_buffer_element *spi_tx_fifo_buffer = (union spi_buffer_element *)(malloc(sizeof(union spi_buffer_element) * buffer_size));
union spi_buffer_element *spi_rx_fifo_buffer = (union spi_buffer_element *)(malloc(sizeof(union spi_buffer_element) * buffer_size));
fifo_init(_spi->_spi_rx_fifo_desc, spi_rx_fifo_buffer, buffer_size);
fifo_init(_spi->_spi_tx_fifo_desc, spi_tx_fifo_buffer, buffer_size);
spi_set_peripheral_chip_select_value(spi_base, spi_get_pcs(spi_chip_sel));
switch (spi_mode)
{
case 0:
spi_set_clock_polarity(spi_base, spi_chip_sel,0);
spi_set_clock_phase(spi_base, spi_chip_sel, 1);
break;
case 1:
spi_set_clock_polarity(spi_base, spi_chip_sel, 0);
spi_set_clock_phase(spi_base, spi_chip_sel, 0);
break;
case 2:
spi_set_clock_polarity(spi_base, spi_chip_sel, 1);
spi_set_clock_phase(spi_base, spi_chip_sel, 1);
break;
case 3:
spi_set_clock_polarity(spi_base, spi_chip_sel, 1);
spi_set_clock_phase(spi_base, spi_chip_sel, 0);
break;
}
spi_set_bits_per_transfer(spi_base, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_configure_cs_behavior(spi_base, spi_chip_sel, SPI_CS_KEEP_LOW);
spi_set_baudrate_div(spi_base, spi_chip_sel, (sysclk_get_peripheral_hz() / spi_freq));
spi_set_delay_between_chip_select(spi_base, 0x10);
spi_set_transfer_delay(spi_base, spi_chip_sel, 0x01, 0x10);
spi_enable(spi_base);
return _spi;
}
/**
* \brief Initial the ssc interface.
*/
static void init_ssc(void)
{
clock_opt_t tx_clk_option;
data_frame_opt_t tx_data_frame_option;
/* Initialize clock */
pmc_enable_periph_clk(ID_SSC);
/* Reset SSC */
ssc_reset(SSC);
/* Configure SSC */
ssc_set_clock_divider(SSC, SAMPLE_RATE * (BITS_BY_SLOT + 1) * 2,
sysclk_get_peripheral_hz());
/* Transmitter clock mode configuration. */
tx_clk_option.ul_cks = SSC_TCMR_CKS_MCK;
tx_clk_option.ul_cko = SSC_TCMR_CKO_CONTINUOUS;
tx_clk_option.ul_cki = 0;
tx_clk_option.ul_ckg = SSC_TCMR_CKG_NONE;
tx_clk_option.ul_start_sel = SSC_TCMR_START_RF_EDGE;
tx_clk_option.ul_sttdly = 1;
tx_clk_option.ul_period = BITS_BY_SLOT - 1;
/* Transmitter frame mode configuration. */
tx_data_frame_option.ul_datlen = BITS_BY_SLOT - 1;
tx_data_frame_option.ul_msbf = SSC_TFMR_MSBF;
tx_data_frame_option.ul_datnb = 0;
tx_data_frame_option.ul_fslen = BITS_BY_SLOT - 1;
tx_data_frame_option.ul_fslen_ext = 0;
tx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NEGATIVE;
tx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE;
/* Configure the SSC transmitter to I2S mode. */
ssc_set_transmitter(SSC, &tx_clk_option, &tx_data_frame_option);
/* Disable transmitter first */
ssc_disable_tx(SSC);
/* Disable All Interrupt */
ssc_disable_interrupt(SSC, 0xFFFFFFFF);
}
/**
* \brief Configure TC TC_CHANNEL_WAVEFORM in waveform operating mode.
*/
static void tc_waveform_initialize(void)
{
uint32_t ra, rc;
/* Configure the PMC to enable the TC module. */
sysclk_enable_peripheral_clock(ID_TC_WAVEFORM);
/* Init TC to waveform mode. */
tc_init(TC, TC_CHANNEL_WAVEFORM,
/* Waveform Clock Selection */
gc_waveconfig[gs_uc_configuration].ul_intclock
| TC_CMR_WAVE /* Waveform mode is enabled */
| TC_CMR_ACPA_SET /* RA Compare Effect: set */
| TC_CMR_ACPC_CLEAR /* RC Compare Effect: clear */
| TC_CMR_CPCTRG /* UP mode with automatic trigger on RC Compare */
);
/* Configure waveform frequency and duty cycle. */
#if (SAM4L)
rc = (sysclk_get_peripheral_bus_hz(TC) /
divisors[gc_waveconfig[gs_uc_configuration].ul_intclock]) /
gc_waveconfig[gs_uc_configuration].us_frequency;
#else
rc = (sysclk_get_peripheral_hz() /
divisors[gc_waveconfig[gs_uc_configuration].ul_intclock]) /
gc_waveconfig[gs_uc_configuration].us_frequency;
#endif
tc_write_rc(TC, TC_CHANNEL_WAVEFORM, rc);
ra = (100 - gc_waveconfig[gs_uc_configuration].us_dutycycle) * rc / 100;
tc_write_ra(TC, TC_CHANNEL_WAVEFORM, ra);
/* Enable TC TC_CHANNEL_WAVEFORM. */
tc_start(TC, TC_CHANNEL_WAVEFORM);
printf("Start waveform: Frequency = %d Hz,Duty Cycle = %2d%%\n\r",
gc_waveconfig[gs_uc_configuration].us_frequency,
gc_waveconfig[gs_uc_configuration].us_dutycycle);
}
/**
* \brief Test the usart sleepwalking in wait mode.
*/
static void usart_sleepwalking_test_wait(void)
{
enum sleepmgr_mode current_sleep_mode = SLEEPMGR_WAIT;
puts("Test in wait mode, press number '0' to '9' to wake up.\r");
/* Wait for the puts operation to finish. */
delay_ms(50);
/* The sleep manage will set the clock to 24MRC in wait mode,
* reconfig the divisor */
usart_set_async_baudrate(CONSOLE_UART, CONF_UART_BAUDRATE, OSC_MAINCK_24M_RC_HZ);
/* Wait for the clock stable. */
delay_ms(5);
/* Set the wakeup condition */
usart_set_sleepwalking(CONSOLE_UART, '0', true, true, '9');
/* Enable the sleepwalking in PMC */
pmc_enable_sleepwalking(CONSOLE_UART_ID);
/* Enter wait mode. */
sleepmgr_init();
sleepmgr_lock_mode(current_sleep_mode);
sleepmgr_enter_sleep();
/* Config the divisor to the original setting */
usart_set_async_baudrate(CONSOLE_UART, CONF_UART_BAUDRATE, sysclk_get_peripheral_hz());
/* Wait for the clock stable. */
delay_ms(5);
puts("A character is received, system wake up.\r\n\r");
}
/**
* \brief
*
* \param
*
* \return void
*/
void uart_config(void)
{
const sam_uart_opt_t uart_settings = {
.ul_mck = sysclk_get_peripheral_hz(),
.ul_baudrate = 19200,
.ul_mode = UART_MR_PAR_NO
};
sysclk_enable_peripheral_clock(ID_UART);
uart_init( BOARD_UART, &uart_settings );
}
/**
* \brief
*
* \param
*
* \return void
*/
void usart0_config(void)
{
const sam_usart_opt_t usart_0_settings = {
.baudrate = 19200,
.char_length = US_MR_CHRL_8_BIT,
.parity_type = US_MR_PAR_NO,
.stop_bits = US_MR_NBSTOP_1_BIT,
.channel_mode = US_MR_CHMODE_NORMAL,
/* This field is only used in IrDA mode. */
.irda_filter = 0
};
sysclk_enable_peripheral_clock(BOART_ID_USART0);
usart_init_rs232(BOARD_USART0, &usart_0_settings, sysclk_get_peripheral_hz());
/* Disable all the interrupts. */
usart_disable_interrupt(BOARD_USART0, 0xffffffff);
/* Enable the receiver and transmitter. */
usart_enable_tx(BOARD_USART0);
usart_enable_rx(BOARD_USART0);
/* Configure and enable interrupt of USART. */
NVIC_EnableIRQ(USART0_IRQn);
usart_enable_interrupt(BOARD_USART0, US_IER_RXRDY);
}
/**
* \brief
*
* \param
*
* \return void
*/
void usart1_config(void)
{
const sam_usart_opt_t usart_1_settings = {
.baudrate = 115200,
.char_length = US_MR_CHRL_8_BIT,
.parity_type = US_MR_PAR_NO,
.stop_bits = US_MR_NBSTOP_1_BIT,
.channel_mode = US_MR_CHMODE_NORMAL,
/* This field is only used in IrDA mode. */
.irda_filter = 0
};
sysclk_enable_peripheral_clock( BOART_ID_USART1 );
usart_init_rs232( BOARD_USART1, &usart_1_settings, sysclk_get_peripheral_hz() );
/* Disable all the interrupts. */
usart_disable_interrupt(BOARD_USART1, 0xffffffff);
/* Enable the receiver and transmitter. */
usart_enable_tx(BOARD_USART1);
usart_enable_rx(BOARD_USART1);
/* Configure and enable interrupt of USART. */
NVIC_EnableIRQ( USART1_IRQn );
usart_enable_interrupt( BOARD_USART1, US_IER_RXRDY);
}
/**
* \brief
*
* \param uxPriority
*
* \return void
*/
void vStartUartTaskLauncher( unsigned portBASE_TYPE uxPriority )
{
/* Spawn the Sentinel task. */
xTaskCreate( vUartTask, (const signed portCHAR *)"SPILAUNCH",
TASK_RADIO_STACK_SIZE, NULL, uxPriority,
(xTaskHandle *)NULL );
}
/**
* \brief UART handle task..
*
* \param
* \param
*
* \return None
*/
portTASK_FUNCTION_PROTO( vUartTask, pvParameters )
{
uint8_t i, sms_text[] = "AT\r";
(void)pvParameters;
/* Initialize UART model.*/
uart_config();
usart0_config();
usart1_config();
gpio_set_pin_low( PIO_PA17_IDX );
for (;;)
{
vTaskDelay(1000);
uart_write( BOARD_UART, '1' );
usart_serial_write_packet( BOARD_USART1, sms_text, sizeof(sms_text) );
}
}
/**
* \brief
*
* \param
*
* \return void
*/
void USART0_Handler(void)
{
uint32_t ul_status;
/* Read USART Status. */
ul_status = usart_get_status( BOARD_USART0 );
/* Receive buffer is full. */
if (ul_status & US_CSR_RXRDY)
{
usart_read( BOARD_USART0, (uint32_t *)&gs_ul_read_buffer[0] );
}
}
/**
* \brief This function opens an USART
*
* \note Opening of the specified USART implies initializing local variables and
* opening required hardware with the following configuration:
* - bauds as specified
* - 8 bits, no parity, 1 stop bit
* - enable interrupts
*
* \param chn Communication channel [0, 1]
* \param bauds Communication speed in bauds
*
* \retval true on success.
* \retval false on failure.
*/
int8_t busart_if_open(uint8_t chn, uint32_t bauds)
{
#if defined(CONF_BOARD_USART0_RXD) || defined(CONF_BOARD_USART1_RXD)
sam_usart_opt_t usart_console_settings;
/* Expected baud rate. */
usart_console_settings.baudrate = bauds;
/* Configure channel mode (Normal, Automatic, Local_loopback or
* Remote_loopback) */
usart_console_settings.channel_mode = US_MR_CHMODE_NORMAL;
/* Initialize value for USART mode register */
usart_console_settings.parity_type = US_MR_PAR_NO;
usart_console_settings.char_length = US_MR_CHRL_8_BIT;
usart_console_settings.stop_bits = US_MR_NBSTOP_1_BIT;
#else
UNUSED(bauds);
#endif
/* check usart and it is close */
if (chn >= 2) {
return false;
}
if (busart_chn_open[chn]) {
return false;
}
switch (chn) {
#ifdef CONF_BOARD_USART0_RXD
case 0:
{
/* Configure PMC. */
pmc_enable_periph_clk(ID_USART0);
/* Configure USART. */
usart_init_rs232(USART0, &usart_console_settings,
sysclk_get_peripheral_hz());
/* Assign buffers to pointers */
busart_comm_data_0.puc_tq_buf = ptr_tx_usart_buf0;
busart_comm_data_0.puc_rq_buf = ptr_rx_usart_buf0;
busart_comm_data_0.us_rq_count = 0;
busart_comm_data_0.us_rq_idx = 0;
busart_comm_data_0.us_wq_idx = 0;
/* Get board USART0 PDC base address and enable receiver and
* transmitter. */
g_p_usart_pdc0 = usart_get_pdc_base(USART0);
pdc_enable_transfer(g_p_usart_pdc0,
PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);
/* Start receiving data and start timer. */
g_st_usart_rx_packet0.ul_addr = (uint32_t)gs_puc_usart_buf0;
g_st_usart_rx_packet0.ul_size = USART_BUFFER_SIZE;
pdc_rx_init(g_p_usart_pdc0, &g_st_usart_rx_packet0, NULL);
/* Stop transmitting data */
g_st_usart_tx_packet0.ul_addr = (uint32_t)busart_comm_data_0.puc_tq_buf;
g_st_usart_tx_packet0.ul_size = 0;
pdc_tx_init(g_p_usart_pdc0, &g_st_usart_tx_packet0, NULL);
gs_ul_size_usart_buf0 = USART_BUFFER_SIZE;
/* Transfer to PDC communication mode, disable RXRDY interrupt
* and enable RXBUFF interrupt. */
usart_disable_interrupt(USART0, US_IDR_RXRDY);
usart_enable_interrupt(USART0, US_IER_RXBUFF);
/* Enable the receiver and transmitter. */
usart_enable_tx(USART0);
usart_enable_rx(USART0);
/* Configure and enable interrupt of USART. */
NVIC_SetPriority((IRQn_Type)USART0_IRQn, USART0_PRIO);
NVIC_EnableIRQ(USART0_IRQn);
busart_chn_open[chn] = true;
num_bytes_rx_usart0 = 0;
/* Configure TC usart */
_configure_TC_usart();
tc_start(TC_USART, TC_USART_CHN);
return true;
}
break;
#endif
#ifdef CONF_BOARD_USART1_RXD
case 1:
{
/* Configure PMC. */
pmc_enable_periph_clk(ID_USART1);
/* Configure USART. */
usart_init_rs232(USART1, &usart_console_settings,
sysclk_get_peripheral_hz());
/* Assign buffers to pointers */
busart_comm_data_1.puc_tq_buf = ptr_tx_usart_buf1;
busart_comm_data_1.puc_rq_buf = ptr_rx_usart_buf1;
busart_comm_data_1.us_rq_count = 0;
busart_comm_data_1.us_rq_idx = 0;
busart_comm_data_1.us_wq_idx = 0;
/* Get board USART1 PDC base address and enable receiver and
* transmitter. */
g_p_usart_pdc1 = usart_get_pdc_base(USART1);
pdc_enable_transfer(g_p_usart_pdc1,
PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);
/* Start receiving data and start timer. */
g_st_usart_rx_packet1.ul_addr = (uint32_t)gs_puc_usart_buf1;
g_st_usart_rx_packet1.ul_size = USART_BUFFER_SIZE;
pdc_rx_init(g_p_usart_pdc1, &g_st_usart_rx_packet1, NULL);
/* Stop transmitting data */
g_st_usart_tx_packet1.ul_addr = (uint32_t)busart_comm_data_1.puc_tq_buf;
g_st_usart_tx_packet1.ul_size = 0;
pdc_tx_init(g_p_usart_pdc1, &g_st_usart_tx_packet1, NULL);
gs_ul_size_usart_buf1 = USART_BUFFER_SIZE;
/* Transfer to PDC communication mode, disable RXRDY interrupt
* and enable RXBUFF interrupt. */
usart_disable_interrupt(USART1, US_IDR_RXRDY);
usart_enable_interrupt(USART1, US_IER_RXBUFF);
/* Enable the receiver and transmitter. */
usart_enable_tx(USART1);
usart_enable_rx(USART1);
/* Configure and enable interrupt of USART. */
NVIC_SetPriority((IRQn_Type)USART1_IRQn, USART1_PRIO);
NVIC_EnableIRQ(USART1_IRQn);
busart_chn_open[chn] = true;
num_bytes_rx_usart1 = 0;
/* Configure TC usart */
_configure_TC_usart();
tc_start(TC_USART, TC_USART_CHN);
return true;
}
break;
#endif
default:
return false;
}
}
int main(void)
{
int rx_len;
irq_initialize_vectors();
cpu_irq_enable();
unsigned char ch;
// Initialize the sleep manager
sleepmgr_init();
#if !SAM0
sysclk_init();
board_init();
#else
system_init();
#endif
configure_console();
printf("\nUSB CDC\n");
printf("CPU:%dHz\n", sysclk_get_cpu_hz());
printf("sysclk_get_peripheral_hz:%dHz\n", sysclk_get_peripheral_hz());
printf("sysclk_get_main_hz:%dHz\n", sysclk_get_main_hz());
ui_init();
ui_powerdown();
// Start USB stack to authorize VBus monitoring
udc_start();
port_interrupt_disible();
// The main loop manages only the power mode
// because the USB management is done by interrupt
unsigned long input_count=0;
while (true) {
ch = port_inbyte(1);
if(! port_in_is_error())
{
if('c'== ch)
{
port_outbyte('C');
xmodemReceive((unsigned char *)0x2000, 0x100000);
}
else if('x'== ch)
{
port_outbyte('X');
xmodemTransmit((unsigned char *)0x2000, 0x100000);
}
else if('u'== ch)
{
port_outbyte('U');
}
else if('m'== ch)
{
for(int j=0; j<20; j++)
{
//printf("S 64MB");
port_outbyte('+');
for(int i=0; i <1024*1024/4; i++)
{
memcpy((void *)(0x60000000), (void *)0x60010000, 1024*4);
}
//printf("E 64MB ");
}
}
else if('T'== ch)
{
while(1)
{
//delay_us(1);
rx_len = port_read(test_rx_buf, rx_block_len, 1);
//crc16_ccitt(test_rx_buf,rx_block_len);
memcpy(&test_rx_buf[rx_block_len], &test_rx_buf[0], rx_block_len);
if(rx_len != rx_block_len)
break;
#if 0
for(int i=0;i<rx_bulk_len; i++)
{
if('T'!=test_rx_buf[i])
break;
}
#endif
input_count += rx_block_len;
if(0==(input_count&(1024-1)))
{
//port_outbyte('K');
}
if(0==(input_count&(1024*1024-1)))
{
port_outbyte('M');
}
}
}
}
else
{
delay_us(10);
}
//sleepmgr_enter_sleep();
}
}
void uart_config(uint8_t port, usb_cdc_line_coding_t * cfg)
{
Usart* usart = get_usart(port);
uint32_t stopbits, parity, databits;
uint32_t imr;
switch (cfg->bCharFormat) {
case CDC_STOP_BITS_2:
stopbits = US_MR_NBSTOP_2_BIT;
break;
case CDC_STOP_BITS_1_5:
stopbits = US_MR_NBSTOP_1_5_BIT;
break;
case CDC_STOP_BITS_1:
default:
// Default stop bit = 1 stop bit
stopbits = US_MR_NBSTOP_1_BIT;
break;
}
switch (cfg->bParityType) {
case CDC_PAR_EVEN:
parity = US_MR_PAR_EVEN;
break;
case CDC_PAR_ODD:
parity = US_MR_PAR_ODD;
break;
case CDC_PAR_MARK:
parity = US_MR_PAR_MARK;
break;
case CDC_PAR_SPACE:
parity = US_MR_PAR_SPACE;
break;
default:
case CDC_PAR_NONE:
parity = US_MR_PAR_NO;
break;
}
switch(cfg->bDataBits) {
case 5: case 6: case 7:
databits = cfg->bDataBits - 5;
break;
default:
case 8:
databits = US_MR_CHRL_8_BIT;
break;
}
// Options for USART.
usart_options.baudrate = LE32_TO_CPU(cfg->dwDTERate);
usart_options.char_length = databits;
usart_options.parity_type = parity;
usart_options.stop_bits = stopbits;
usart_options.channel_mode = US_MR_CHMODE_NORMAL;
imr = usart_get_interrupt_mask(usart);
usart_disable_interrupt(usart, 0xFFFFFFFF);
usart_init_rs232(usart, &usart_options,
sysclk_get_peripheral_hz());
// Restore both RX and TX
usart_enable_tx(usart);
usart_enable_rx(usart);
usart_enable_interrupt(usart, imr);
}
/**
* \brief Application entry point for tc_capture_waveform example.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
uint8_t key;
uint16_t frequence, dutycycle;
/* Initialize the SAM system */
sysclk_init();
board_init();
/* Initialize the console uart */
configure_console();
/* Output example information */
printf("-- TC capture waveform Example --\r\n");
printf("-- %s\n\r", BOARD_NAME);
printf("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);
/* Configure PIO Pins for TC */
#if (SAM4L || SAM4E)
ioport_set_pin_mode(PIN_TC_WAVEFORM, PIN_TC_WAVEFORM_FLAGS);
ioport_disable_pin(PIN_TC_WAVEFORM); // Disable IO (but enable peripheral mode)
ioport_set_pin_mode(PIN_TC_CAPTURE, PIN_TC_CAPTURE_FLAGS);
ioport_disable_pin(PIN_TC_CAPTURE); // Disable IO (but enable peripheral mode)
#else
gpio_configure_pin(PIN_TC_WAVEFORM, PIN_TC_WAVEFORM_FLAGS);
gpio_configure_pin(PIN_TC_CAPTURE, PIN_TC_CAPTURE_FLAGS);
#endif
/* Configure TC TC_CHANNEL_WAVEFORM as waveform operating mode */
printf("Configure TC%d channel %d as waveform operating mode \n\r",
TC_PERIPHERAL, TC_CHANNEL_WAVEFORM);
tc_waveform_initialize();
/* Configure TC TC_CHANNEL_CAPTURE as capture operating mode */
printf("Configure TC%d channel %d as capture operating mode \n\r",
TC_PERIPHERAL, TC_CHANNEL_CAPTURE);
tc_capture_initialize();
/* Configure TC interrupts for TC TC_CHANNEL_CAPTURE only */
NVIC_DisableIRQ(TC_IRQn);
NVIC_ClearPendingIRQ(TC_IRQn);
NVIC_SetPriority(TC_IRQn, 0);
NVIC_EnableIRQ(TC_IRQn);
/* Display menu */
display_menu();
while (1) {
scanf("%c", (char *)&key);
switch (key) {
case 'h':
display_menu();
break;
case 's':
if (gs_ul_captured_pulses) {
tc_disable_interrupt(TC, TC_CHANNEL_CAPTURE, TC_IDR_LDRBS);
printf("Captured %u pulses from TC%d channel %d, RA = %u, RB = %u \n\r",
gs_ul_captured_pulses, TC_PERIPHERAL,
TC_CHANNEL_CAPTURE, gs_ul_captured_ra,
gs_ul_captured_rb);
#if (SAM4L)
frequence = (sysclk_get_peripheral_bus_hz(TC) /
divisors[TC_CAPTURE_TIMER_SELECTION]) /
gs_ul_captured_rb;
#else
frequence = (sysclk_get_peripheral_hz() /
divisors[TC_CAPTURE_TIMER_SELECTION]) /
gs_ul_captured_rb;
#endif
dutycycle
= (gs_ul_captured_rb - gs_ul_captured_ra) * 100 /
gs_ul_captured_rb;
printf("Captured wave frequency = %d Hz, Duty cycle = %d%% \n\r",
frequence, dutycycle);
gs_ul_captured_pulses = 0;
gs_ul_captured_ra = 0;
gs_ul_captured_rb = 0;
} else {
puts("No waveform has been captured\r");
}
puts("\n\rPress 'h' to display menu\r");
break;
case 'c':
puts("Start capture, press 's' to stop \r");
tc_enable_interrupt(TC, TC_CHANNEL_CAPTURE, TC_IER_LDRBS);
/* Start the timer counter on TC TC_CHANNEL_CAPTURE */
tc_start(TC, TC_CHANNEL_CAPTURE);
break;
default:
/* Set waveform configuration #n */
if ((key >= '0') && (key <= ('0' + gc_uc_nbconfig - 1))) {
if (!gs_ul_captured_pulses) {
gs_uc_configuration = key - '0';
tc_waveform_initialize();
} else {
puts("Capturing ... , press 's' to stop capture first \r");
}
}
break;
}
}
}
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
/* Sanity check arguments */
MBED_ASSERT(obj);
int clockid = NC, flexcom = NC;
/*To determine the uart peripheral associated with pins*/
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT(uart != (UARTName)NC);
if (g_sys_init == 0) {
sysclk_init();
system_board_init();
g_sys_init = 1;
}
pUSART_S(obj) = uart;
pSERIAL_S(obj)->uart_serial_options.baudrate = (9600UL);
pSERIAL_S(obj)->uart_serial_options.charlength = US_MR_CHRL_8_BIT;
pSERIAL_S(obj)->uart_serial_options.paritytype = US_MR_PAR_NO;
pSERIAL_S(obj)->uart_serial_options.stopbits = US_MR_NBSTOP_1_BIT;
pSERIAL_S(obj)->actrec = false;
pSERIAL_S(obj)->acttra = false;
/* Configure UART pins */
if(tx != NC) {
pin_function(tx, pinmap_find_function(tx, PinMap_UART_TX));
ioport_disable_pin(tx);
}
if(rx != NC) {
pin_function(rx, pinmap_find_function(rx, PinMap_UART_RX));
ioport_disable_pin(rx);
}
clockid = get_usart_clock_id(uart);
if (clockid != NC) {
sysclk_enable_peripheral_clock(clockid);
}
flexcom = (int)get_flexcom_id(uart);
#if (!SAM4L)
#if (SAMG55)
/* Configure flexcom for usart */
flexcom_enable((Flexcom* )flexcom);
flexcom_set_opmode((Flexcom* )flexcom, FLEXCOM_USART);
#else
sysclk_enable_peripheral_clock(clockid);
#endif
/* Configure USART */
usart_init_rs232((Usart*)uart, (sam_usart_opt_t*)&(pSERIAL_S(obj)->uart_serial_options),
sysclk_get_peripheral_hz());
#endif
#if (SAM4L)
sysclk_enable_peripheral_clock(clockid);
/* Configure USART */
usart_init_rs232((Usart*)uart, (sam_usart_opt_t*)&(pSERIAL_S(obj)->uart_serial_options, sysclk_get_peripheral_bus_hz((Usart*)uart));
#endif
/* Disable rx and tx in case 1 line only required to be configured for usart */
usart_disable_tx((Usart*)uart);
usart_disable_rx((Usart*)uart);
/* Enable the receiver and transmitter. */
if(tx != NC) {
usart_enable_tx((Usart*)uart);
}
if(rx != NC) {
usart_enable_rx((Usart*)uart);
}
if(uart == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
OSStatus platform_uart_init( platform_uart_driver_t* driver, const platform_uart_t* peripheral, const platform_uart_config_t* config, ring_buffer_t* optional_ring_buffer )
{
pdc_packet_t pdc_uart_packet, pdc_uart_tx_packet;
OSStatus err = kNoErr;
sam_usart_opt_t settings;
bool hardware_shaking = false;
platform_mcu_powersave_disable();
require_action_quiet( ( driver != NULL ) && ( peripheral != NULL ) && ( config != NULL ), exit, err = kParamErr);
require_action_quiet( (optional_ring_buffer->buffer != NULL ) && (optional_ring_buffer->size != 0), exit, err = kUnsupportedErr);
driver->rx_size = 0;
driver->tx_size = 0;
driver->rx_ring_buffer = optional_ring_buffer;
driver->last_transmit_result = kNoErr;
driver->last_receive_result = kNoErr;
driver->peripheral = (platform_uart_t*)peripheral;
#ifndef NO_MICO_RTOS
mico_rtos_init_semaphore( &driver->tx_complete, 1 );
mico_rtos_init_semaphore( &driver->rx_complete, 1 );
mico_rtos_init_semaphore( &driver->sem_wakeup, 1 );
mico_rtos_init_mutex ( &driver->tx_mutex );
#else
driver->tx_complete = false;
driver->rx_complete = false;
#endif
/* Set Tx and Rx pin mode to UART peripheral */
platform_gpio_peripheral_pin_init( peripheral->tx_pin, ( peripheral->tx_pin_mux_mode | IOPORT_MODE_PULLUP ) );
platform_gpio_peripheral_pin_init( peripheral->rx_pin, ( peripheral->rx_pin_mux_mode | IOPORT_MODE_PULLUP ) );
/* Init CTS and RTS pins (if available) */
if ( peripheral->cts_pin != NULL && (config->flow_control == FLOW_CONTROL_CTS || config->flow_control == FLOW_CONTROL_CTS_RTS) )
{
hardware_shaking = true;
platform_gpio_peripheral_pin_init( peripheral->cts_pin, ( peripheral->cts_pin_mux_mode | IOPORT_MODE_PULLUP ) );
}
if ( peripheral->rts_pin != NULL && (config->flow_control == FLOW_CONTROL_CTS || config->flow_control == FLOW_CONTROL_CTS_RTS) )
{
hardware_shaking = true;
platform_gpio_peripheral_pin_init( peripheral->rts_pin, ( peripheral->rts_pin_mux_mode | IOPORT_MODE_PULLUP ) );
}
/* Enable the clock. */
if( pmc_is_periph_clk_enabled( peripheral->peripheral_id ) == 0 ) {
flexcom_enable( peripheral->flexcom_base );
}
flexcom_set_opmode( peripheral->flexcom_base, FLEXCOM_USART );
/* Enable the receiver and transmitter. */
usart_reset_tx( peripheral->port );
usart_reset_rx( peripheral->port );
/* Disable all the interrupts. */
usart_disable_interrupt( peripheral->port, 0xffffffff );
switch ( config->parity ) {
case NO_PARITY:
settings.parity_type = US_MR_PAR_NO;
break;
case EVEN_PARITY:
settings.parity_type = US_MR_PAR_EVEN;
break;
case ODD_PARITY:
settings.parity_type = US_MR_PAR_ODD;
break;
default:
err = kParamErr;
goto exit;
}
switch ( config->data_width) {
case DATA_WIDTH_5BIT:
settings.char_length = US_MR_CHRL_5_BIT;
break;
case DATA_WIDTH_6BIT:
settings.char_length = US_MR_CHRL_6_BIT;
break;
case DATA_WIDTH_7BIT:
settings.char_length = US_MR_CHRL_7_BIT;
break;
case DATA_WIDTH_8BIT:
settings.char_length = US_MR_CHRL_8_BIT;
break;
case DATA_WIDTH_9BIT:
settings.char_length = US_MR_MODE9;
break;
default:
err = kParamErr;
goto exit;
}
settings.baudrate = config->baud_rate;
settings.stop_bits = ( config->stop_bits == STOP_BITS_1 ) ? US_MR_NBSTOP_1_BIT : US_MR_NBSTOP_2_BIT;
settings.channel_mode= US_MR_CHMODE_NORMAL;
/* Configure USART in serial mode. */
if (!hardware_shaking) {
usart_init_rs232( peripheral->port, &settings, sysclk_get_peripheral_hz());
} else {
usart_init_hw_handshaking( peripheral->port, &settings, sysclk_get_peripheral_hz());
}
/* Enable uart interrupt */
NVIC_SetPriority( platform_flexcom_irq_numbers[peripheral->uart_id], 0x06 );
NVIC_EnableIRQ( platform_flexcom_irq_numbers[peripheral->uart_id] );
/* Enable PDC transmit */
pdc_enable_transfer( usart_get_pdc_base( peripheral->port ), PERIPH_PTCR_TXTEN | PERIPH_PTCR_RXTEN );
pdc_disable_transfer( usart_get_pdc_base( driver->peripheral->port ), PERIPH_PTCR_TXTDIS );
pdc_uart_packet.ul_addr = (uint32_t)driver->rx_ring_buffer->buffer;
pdc_uart_packet.ul_size = (uint32_t)driver->rx_ring_buffer->size;
pdc_rx_init( usart_get_pdc_base( peripheral->port ), &pdc_uart_packet, &pdc_uart_packet );
pdc_uart_tx_packet.ul_addr = (uint32_t)0;
pdc_uart_tx_packet.ul_size = (uint32_t)1;
pdc_tx_init( usart_get_pdc_base( driver->peripheral->port ), &pdc_uart_tx_packet, NULL );
usart_enable_interrupt( peripheral->port, US_IER_ENDRX | US_IER_RXBUFF | US_IER_RXRDY | US_IER_ENDTX );
/* Enable the receiver and transmitter. */
usart_enable_tx( peripheral->port );
usart_enable_rx( peripheral->port );
exit:
platform_mcu_powersave_enable( );
return err;
}