/* Test system controller finding */
static int dm_test_syscon_by_driver_data(struct unit_test_state *uts)
{
struct udevice *dev;
ut_assertok(syscon_get_by_driver_data(SYSCON0, &dev));
ut_asserteq(SYSCON0, dev->driver_data);
ut_assertok(syscon_get_by_driver_data(SYSCON1, &dev));
ut_asserteq(SYSCON1, dev->driver_data);
ut_asserteq(-ENODEV, syscon_get_by_driver_data(2, &dev));
return 0;
}
struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data)
{
struct syscon_uc_info *priv;
struct udevice *dev;
int ret;
ret = syscon_get_by_driver_data(driver_data, &dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_uclass_priv(dev);
return priv->regmap;
}
int pmu_turn_power(unsigned int lss, bool on)
{
struct pmu_mid *pmu;
struct udevice *dev;
int ret;
ret = syscon_get_by_driver_data(X86_SYSCON_PMU, &dev);
if (ret)
return ret;
pmu = dev_get_priv(dev);
return pmu_power_lss(pmu->regs, lss, on);
}
static int ich6_gpio_probe(struct udevice *dev)
{
struct ich6_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ich6_bank_priv *bank = dev_get_priv(dev);
struct udevice *pinctrl;
/* Set up pin control if available */
syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
bank->use_sel = plat->base_addr;
bank->io_sel = plat->base_addr + 4;
bank->lvl = plat->base_addr + 8;
return 0;
}
static int broadwell_gpio_probe(struct udevice *dev)
{
struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct broadwell_bank_priv *priv = dev_get_priv(dev);
struct udevice *pinctrl;
int ret;
/* Set up pin control if available */
ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
priv->regs = (struct pch_lp_gpio_regs *)(uintptr_t)plat->base_addr;
priv->bank = plat->bank;
priv->offset = priv->bank * 32;
debug("%s: probe done, regs %p, bank %d\n", __func__, priv->regs,
priv->bank);
return 0;
}
int dram_init(void)
{
struct pei_data _pei_data __aligned(8);
struct pei_data *pei_data = &_pei_data;
struct udevice *dev, *me_dev, *pch_dev;
struct chipset_power_state ps;
const void *spd_data;
int ret, size;
memset(pei_data, '\0', sizeof(struct pei_data));
/* Print ME state before MRC */
ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
if (ret)
return ret;
intel_me_status(me_dev);
/* Save ME HSIO version */
ret = uclass_first_device(UCLASS_PCH, &pch_dev);
if (ret)
return ret;
if (!pch_dev)
return -ENODEV;
power_state_get(pch_dev, &ps);
intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);
broadwell_fill_pei_data(pei_data);
mainboard_fill_pei_data(pei_data);
ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
if (ret)
return ret;
if (!dev)
return -ENODEV;
size = 256;
ret = mrc_locate_spd(dev, size, &spd_data);
if (ret)
return ret;
memcpy(pei_data->spd_data[0][0], spd_data, size);
memcpy(pei_data->spd_data[1][0], spd_data, size);
ret = prepare_mrc_cache(pei_data);
if (ret)
debug("prepare_mrc_cache failed: %d\n", ret);
debug("PEI version %#x\n", pei_data->pei_version);
ret = mrc_common_init(dev, pei_data, true);
if (ret)
return ret;
debug("Memory init done\n");
ret = sdram_find(dev);
if (ret)
return ret;
gd->ram_size = gd->arch.meminfo.total_32bit_memory;
debug("RAM size %llx\n", (unsigned long long)gd->ram_size);
debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size,
pei_data->data_to_save);
/* S3 resume: don't save scrambler seed or MRC data */
if (pei_data->boot_mode != SLEEP_STATE_S3) {
/*
* This will be copied to SDRAM in reserve_arch(), then written
* to SPI flash in mrccache_save()
*/
gd->arch.mrc_output = (char *)pei_data->data_to_save;
gd->arch.mrc_output_len = pei_data->data_to_save_size;
}
gd->arch.pei_meminfo = pei_data->meminfo;
return 0;
}
