static int nuc910_nand_init(struct nand_device *nand)
{
struct nuc910_nand_controller *nuc910_nand = nand->controller_priv;
struct target *target = nand->target;
int bus_width = nand->bus_width ? : 8;
int result;
if ((result = validate_target_state(nand)) != ERROR_OK)
return result;
/* nuc910 only supports 8bit */
if (bus_width != 8)
{
LOG_ERROR("nuc910 only supports 8 bit bus width, not %i", bus_width);
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
/* inform calling code about selected bus width */
nand->bus_width = bus_width;
nuc910_nand->io.target = target;
nuc910_nand->io.data = NUC910_SMDATA;
nuc910_nand->io.op = ARM_NAND_NONE;
/* configure nand controller */
target_write_u32(target, NUC910_FMICSR, NUC910_FMICSR_SM_EN);
target_write_u32(target, NUC910_SMCSR, 0x010000a8); /* 2048 page size */
target_write_u32(target, NUC910_SMTCR, 0x00010204);
target_write_u32(target, NUC910_SMIER, 0x00000000);
return ERROR_OK;
}
static int stm32lx_enable_write_half_page(struct flash_bank *bank)
{
struct target *target = bank->target;
int retval;
uint32_t reg32;
/**
* Unlock the program memory, then set the FPRG bit in the PECR register.
*/
retval = stm32lx_unlock_program_memory(bank);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, FLASH_PECR, ®32);
if (retval != ERROR_OK)
return retval;
reg32 |= FLASH_PECR__FPRG;
retval = target_write_u32(target, FLASH_PECR, reg32);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, FLASH_PECR, ®32);
if (retval != ERROR_OK)
return retval;
reg32 |= FLASH_PECR__PROG;
retval = target_write_u32(target, FLASH_PECR, reg32);
return retval;
}
static int lpc288x_protect(struct flash_bank *bank, int set, int first, int last)
{
int lockregion, status;
uint32_t value;
struct target *target = bank->target;
/* probed? halted? */
status = lpc288x_system_ready(bank);
if (status != ERROR_OK)
return status;
if ((first < 0) || (last < first) || (last >= bank->num_sectors))
return ERROR_FLASH_SECTOR_INVALID;
/* Configure the flash controller timing */
lpc288x_set_flash_clk(bank);
for (lockregion = first; lockregion <= last; lockregion++) {
if (set) {
/* write an odd value to base addy to protect... */
value = 0x01;
} else {
/* write an even value to base addy to unprotect... */
value = 0x00;
}
target_write_u32(target, bank->sectors[lockregion].offset, value);
target_write_u32(target, F_CTRL, FC_LOAD_REQ | FC_PROTECT | FC_WEN | FC_FUNC |
FC_CS);
}
return ERROR_OK;
}
/* AHB tcyc (in ns) 83 ns
* LOAD_TIMER_ERASE FPT_TIME = ((400,000,000 / AHB tcyc (in ns)) - 2) / 512
* = 9412 (9500) (AN10548 9375)
* LOAD_TIMER_WRITE FPT_TIME = ((1,000,000 / AHB tcyc (in ns)) - 2) / 512
* = 23 (75) (AN10548 72 - is this wrong?)
* TODO: Sort out timing calcs ;) */
static void lpc288x_load_timer(int erase, struct target *target)
{
if (erase == LOAD_TIMER_ERASE)
target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 9500);
else
target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 75);
}
static int stm32x_unlock_option_reg(struct target *target)
{
uint32_t ctrl;
int retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
if (retval != ERROR_OK)
return retval;
if ((ctrl & OPTCR_LOCK) == 0)
return ERROR_OK;
/* unlock option registers */
retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
if (retval != ERROR_OK)
return retval;
if (ctrl & OPTCR_LOCK) {
LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
return ERROR_TARGET_FAILURE;
}
return ERROR_OK;
}
static int em357_mass_erase(struct flash_bank *bank)
{
struct target *target = bank->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* unlock option flash registers */
int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
if (retval != ERROR_OK)
return retval;
/* mass erase flash memory */
retval = target_write_u32(target, EM357_FLASH_CR, FLASH_MER);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, EM357_FLASH_CR, FLASH_MER | FLASH_STRT);
if (retval != ERROR_OK)
return retval;
retval = em357_wait_status_busy(bank, 100);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
int armv7m_trace_itm_config(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct armv7m_trace_config *trace_config = &armv7m->trace_config;
int retval;
retval = target_write_u32(target, ITM_LAR, ITM_LAR_KEY);
if (retval != ERROR_OK)
return retval;
/* Enable ITM, TXENA, set TraceBusID and other parameters */
retval = target_write_u32(target, ITM_TCR, (1 << 0) | (1 << 3) |
(trace_config->itm_diff_timestamps << 1) |
(trace_config->itm_synchro_packets << 2) |
(trace_config->itm_async_timestamps << 4) |
(trace_config->itm_ts_prescale << 8) |
(trace_config->trace_bus_id << 16));
if (retval != ERROR_OK)
return retval;
for (unsigned int i = 0; i < 8; i++) {
retval = target_write_u32(target, ITM_TER0 + i * 4,
trace_config->itm_ter[i]);
if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
}
static int stm32lx_lock_program_memory(struct flash_bank *bank)
{
struct target *target = bank->target;
int retval;
uint32_t reg32;
/* To lock the program memory, simply set the lock bit and lock PECR */
retval = target_read_u32(target, FLASH_PECR, ®32);
if (retval != ERROR_OK)
return retval;
reg32 |= FLASH_PECR__PRGLOCK;
retval = target_write_u32(target, FLASH_PECR, reg32);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, FLASH_PECR, ®32);
if (retval != ERROR_OK)
return retval;
reg32 |= FLASH_PECR__PELOCK;
retval = target_write_u32(target, FLASH_PECR, reg32);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
int mips32_configure_break_unit(struct target *target)
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
int retval;
uint32_t dcr, bpinfo;
int i;
if (mips32->bp_scanned)
return ERROR_OK;
/* get info about breakpoint support */
if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
return retval;
if (dcr & EJTAG_DCR_IB)
{
/* get number of inst breakpoints */
if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
return retval;
mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator));
for (i = 0; i < mips32->num_inst_bpoints; i++)
{
mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
}
/* clear IBIS reg */
if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
return retval;
}
if (dcr & EJTAG_DCR_DB)
{
/* get number of data breakpoints */
if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
return retval;
mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator));
for (i = 0; i < mips32->num_data_bpoints; i++)
{
mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
}
/* clear DBIS reg */
if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
return retval;
}
LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
mips32->num_data_bpoints);
mips32->bp_scanned = 1;
return ERROR_OK;
}
static int lpc288x_erase(struct flash_bank *bank, int first, int last)
{
uint32_t status;
int sector;
struct target *target = bank->target;
status = lpc288x_system_ready(bank); /* probed? halted? */
if (status != ERROR_OK)
return status;
if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
LOG_INFO("Bad sector range");
return ERROR_FLASH_SECTOR_INVALID;
}
/* Configure the flash controller timing */
lpc288x_set_flash_clk(bank);
for (sector = first; sector <= last; sector++) {
if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
return ERROR_FLASH_OPERATION_FAILED;
lpc288x_load_timer(LOAD_TIMER_ERASE, target);
target_write_u32(target, bank->sectors[sector].offset, 0x00);
target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_CS);
}
if (lpc288x_wait_status_busy(bank, 1000) != ERROR_OK)
return ERROR_FLASH_OPERATION_FAILED;
return ERROR_OK;
}
static int stm32x_unlock_reg(struct target *target)
{
uint32_t ctrl;
/* first check if not already unlocked
* otherwise writing on STM32_FLASH_KEYR will fail
*/
int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
if (retval != ERROR_OK)
return retval;
if ((ctrl & FLASH_LOCK) == 0)
return ERROR_OK;
/* unlock flash registers */
retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
if (retval != ERROR_OK)
return retval;
if (ctrl & FLASH_LOCK) {
LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
return ERROR_TARGET_FAILURE;
}
return ERROR_OK;
}
/* The frequency is the AHB clock frequency divided by (CLK_DIV ×3) + 1.
* This must be programmed such that the Flash Programming clock frequency is 66 kHz ± 20%.
* AHB = 12 MHz ?
* 12000000/66000 = 182
* CLK_DIV = 60 ? */
static void lpc288x_set_flash_clk(struct flash_bank *bank)
{
uint32_t clk_time;
struct lpc288x_flash_bank *lpc288x_info = bank->driver_priv;
clk_time = (lpc288x_info->cclk / 66000) / 3;
target_write_u32(bank->target, F_CTRL, FC_CS | FC_WEN);
target_write_u32(bank->target, F_CLK_TIME, clk_time);
}
static int str7x_protect(struct flash_bank *bank, int set, int first, int last)
{
struct str7x_flash_bank *str7x_info = bank->driver_priv;
struct target *target = bank->target;
int i;
uint32_t cmd;
uint32_t protect_blocks;
if (bank->target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
protect_blocks = 0xFFFFFFFF;
if (set)
{
for (i = first; i <= last; i++)
protect_blocks &= ~(str7x_info->sector_bits[i]);
}
/* clear FLASH_ER register */
int err;
err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
if (err != ERROR_OK)
return err;
cmd = FLASH_SPR;
err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
if (err != ERROR_OK)
return err;
cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
if (err != ERROR_OK)
return err;
cmd = protect_blocks;
err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
if (err != ERROR_OK)
return err;
cmd = FLASH_SPR | FLASH_WMS;
err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
if (err != ERROR_OK)
return err;
err = str7x_waitbusy(bank);
if (err != ERROR_OK)
return err;
err = str7x_result(bank);
if (err != ERROR_OK)
return err;
return ERROR_OK;
}
/* Static methods implementation */
static int stm32lx_unlock_program_memory(struct flash_bank *bank)
{
struct target *target = bank->target;
int retval;
uint32_t reg32;
/*
* Unlocking the program memory is done by unlocking the PECR,
* then by writing the 2 PRGKEY to the PRGKEYR register
*/
/* check flash is not already unlocked */
retval = target_read_u32(target, FLASH_PECR, ®32);
if (retval != ERROR_OK)
return retval;
if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
return ERROR_OK;
/* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
retval = target_write_u32(target, FLASH_PEKEYR, PEKEY1);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, FLASH_PEKEYR, PEKEY2);
if (retval != ERROR_OK)
return retval;
/* Make sure it worked */
retval = target_read_u32(target, FLASH_PECR, ®32);
if (retval != ERROR_OK)
return retval;
if (reg32 & FLASH_PECR__PELOCK) {
LOG_ERROR("PELOCK is not cleared :(");
return ERROR_FLASH_OPERATION_FAILED;
}
retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY1);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, FLASH_PRGKEYR, PRGKEY2);
if (retval != ERROR_OK)
return retval;
/* Make sure it worked */
retval = target_read_u32(target, FLASH_PECR, ®32);
if (retval != ERROR_OK)
return retval;
if (reg32 & FLASH_PECR__PRGLOCK) {
LOG_ERROR("PRGLOCK is not cleared :(");
return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_OK;
}
static int str7x_erase(struct flash_bank *bank, int first, int last)
{
struct str7x_flash_bank *str7x_info = bank->driver_priv;
struct target *target = bank->target;
int i;
uint32_t cmd;
uint32_t sectors = 0;
int err;
if (bank->target->state != TARGET_HALTED)
{
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
for (i = first; i <= last; i++)
{
sectors |= str7x_info->sector_bits[i];
}
LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
/* clear FLASH_ER register */
err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
if (err != ERROR_OK)
return err;
cmd = FLASH_SER;
err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
if (err != ERROR_OK)
return err;
cmd = sectors;
err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
if (err != ERROR_OK)
return err;
cmd = FLASH_SER | FLASH_WMS;
err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
if (err != ERROR_OK)
return err;
err = str7x_waitbusy(bank);
if (err != ERROR_OK)
return err;
err = str7x_result(bank);
if (err != ERROR_OK)
return err;
for (i = first; i <= last; i++)
bank->sectors[i].is_erased = 1;
return ERROR_OK;
}
static int s3c2440_init(struct nand_device *nand)
{
struct target *target = nand->target;
target_write_u32(target, S3C2410_NFCONF,
S3C2440_NFCONF_TACLS(3) |
S3C2440_NFCONF_TWRPH0(7) |
S3C2440_NFCONF_TWRPH1(7));
target_write_u32(target, S3C2440_NFCONT,
S3C2440_NFCONT_INITECC | S3C2440_NFCONT_ENABLE);
return ERROR_OK;
}
int mips32_enable_interrupts(struct target *target, int enable)
{
int retval;
int update = 0;
uint32_t dcr;
/* read debug control register */
retval = target_read_u32(target, EJTAG_DCR, &dcr);
if (retval != ERROR_OK)
return retval;
if (enable) {
if (!(dcr & EJTAG_DCR_INTE)) {
/* enable interrupts */
dcr |= EJTAG_DCR_INTE;
update = 1;
}
} else {
if (dcr & EJTAG_DCR_INTE) {
/* disable interrupts */
dcr &= ~EJTAG_DCR_INTE;
update = 1;
}
}
if (update) {
retval = target_write_u32(target, EJTAG_DCR, dcr);
if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
}
static int mrvlqspi_start_transfer(struct flash_bank *bank, bool rw_mode)
{
int retval;
uint32_t regval;
struct target *target = bank->target;
retval = mrvlqspi_set_ss_state(bank, QSPI_SS_ENABLE, QSPI_TIMEOUT);
if (retval != ERROR_OK)
return retval;
retval = target_read_u32(target,
mrvlqspi_get_reg(bank, CONF), ®val);
if (retval != ERROR_OK)
return retval;
if (rw_mode)
regval |= RW_EN;
else
regval &= ~(RW_EN);
regval |= XFER_START;
retval = target_write_u32(target,
mrvlqspi_get_reg(bank, CONF), regval);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
int s3c2440_write_block_data(struct nand_device *nand, uint8_t *data, int data_size)
{
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
struct target *target = nand->target;
uint32_t nfdata = s3c24xx_info->data;
uint32_t tmp;
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
while (data_size >= 4) {
tmp = le_to_h_u32(data);
target_write_u32(target, nfdata, tmp);
data_size -= 4;
data += 4;
}
while (data_size > 0) {
target_write_u8(target, nfdata, *data);
data_size -= 1;
data += 1;
}
return ERROR_OK;
}
static int mips32_configure_dbs(struct target *target)
{
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
int retval, i;
uint32_t bpinfo;
/* get number of data breakpoints */
retval = target_read_u32(target, ejtag_info->ejtag_dbs_addr, &bpinfo);
if (retval != ERROR_OK)
return retval;
mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
mips32->data_break_list = calloc(mips32->num_data_bpoints,
sizeof(struct mips32_comparator));
for (i = 0; i < mips32->num_data_bpoints; i++)
mips32->data_break_list[i].reg_address =
ejtag_info->ejtag_dba0_addr +
(ejtag_info->ejtag_dba_step_size * i);
/* clear DBIS reg */
retval = target_write_u32(target, ejtag_info->ejtag_dbs_addr, 0);
return retval;
}
static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
uint32_t erase_register, uint32_t erase_value)
{
int res;
res = nrf5_nvmc_erase_enable(chip);
if (res != ERROR_OK)
goto error;
res = target_write_u32(chip->target,
erase_register,
erase_value);
if (res != ERROR_OK)
goto set_read_only;
res = nrf5_wait_for_nvmc(chip);
if (res != ERROR_OK)
goto set_read_only;
return nrf5_nvmc_read_only(chip);
set_read_only:
nrf5_nvmc_read_only(chip);
error:
LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
erase_register, erase_value);
return ERROR_FAIL;
}
/* write a long (32bit) from the pc to the netx */
int fn_write_data32(void *pvHandle, unsigned long ulNetxAddress, unsigned long ulData)
{
command_context_t *cmd_ctx;
target_t *target;
int iResult;
/* cast the handle to the command context */
cmd_ctx = (command_context_t*)pvHandle;
/* get the target from the command context */
target = get_current_target(cmd_ctx);
/* read the data from the netX */
iResult = target_write_u32(target, ulNetxAddress, ulData);
if( iResult==ERROR_OK )
{
iResult = 0;
}
else
{
iResult = 1;
}
wxMilliSleep(1);
return iResult;
}
static int xmc4xxx_enter_page_mode(struct flash_bank *bank)
{
int res;
uint32_t status;
res = target_write_u32(bank->target, FLASH_CMD_ENTER_PAGEMODE, 0x50);
if (res != ERROR_OK) {
LOG_ERROR("Unable to write enter page mode command");
return ERROR_FAIL;
}
res = xmc4xxx_get_flash_status(bank, &status);
if (res != ERROR_OK)
return res;
/* Make sure we're in page mode */
if (!(status & FSR_PFPAGE_MASK)) {
LOG_ERROR("Unable to enter page mode");
return ERROR_FAIL;
}
/* Make sure we didn't encounter a sequence error */
if (status & FSR_SQER_MASK) {
LOG_ERROR("Sequence error while entering page mode");
return ERROR_FAIL;
}
return res;
}
/**
* Disable NAND device attached to a controller.
*
* @param info NAND controller information for controlling NAND device.
* @return Success or failure of the disabling.
*/
static int at91sam9_disable(struct nand_device *nand)
{
struct at91sam9_nand *info = nand->controller_priv;
struct target *target = nand->target;
return target_write_u32(target, info->ce.pioc + AT91C_PIOx_SODR, 1 << info->ce.num);
}
static int mrvlqspi_fifo_flush(struct flash_bank *bank, int timeout)
{
int retval;
uint32_t val;
struct target *target = bank->target;
retval = target_read_u32(target,
mrvlqspi_get_reg(bank, CONF), &val);
if (retval != ERROR_OK)
return retval;
val |= FIFO_FLUSH;
retval = target_write_u32(target,
mrvlqspi_get_reg(bank, CONF), val);
if (retval != ERROR_OK)
return retval;
/* wait for fifo_flush to clear */
for (;;) {
retval = target_read_u32(target,
mrvlqspi_get_reg(bank, CONF), &val);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%08" PRIX32, val);
if ((val & FIFO_FLUSH) == 0)
break;
if (timeout-- <= 0) {
LOG_ERROR("timed out waiting for flash");
return ERROR_FAIL;
}
alive_sleep(1);
}
return ERROR_OK;
}
static int mrvlqspi_stop_transfer(struct flash_bank *bank)
{
int retval;
uint32_t regval;
struct target *target = bank->target;
int timeout = QSPI_TIMEOUT;
/* wait for xfer_ready and wfifo_empty to set */
for (;;) {
retval = target_read_u32(target,
mrvlqspi_get_reg(bank, CNTL), ®val);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%08" PRIx32, regval);
if ((regval & (XFER_RDY | WFIFO_EMPTY)) ==
(XFER_RDY | WFIFO_EMPTY))
break;
if (timeout-- <= 0) {
LOG_ERROR("timed out waiting for flash");
return ERROR_FAIL;
}
alive_sleep(1);
}
retval = target_read_u32(target,
mrvlqspi_get_reg(bank, CONF), ®val);
if (retval != ERROR_OK)
return retval;
regval |= XFER_STOP;
retval = target_write_u32(target,
mrvlqspi_get_reg(bank, CONF), regval);
if (retval != ERROR_OK)
return retval;
/* wait for xfer_start to reset */
for (;;) {
retval = target_read_u32(target,
mrvlqspi_get_reg(bank, CONF), ®val);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%08" PRIx32, regval);
if ((regval & XFER_START) == 0)
break;
if (timeout-- <= 0) {
LOG_ERROR("timed out waiting for flash");
return ERROR_FAIL;
}
alive_sleep(1);
}
retval = mrvlqspi_set_ss_state(bank, QSPI_SS_DISABLE, QSPI_TIMEOUT);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
static int fm4_disable_hw_watchdog(struct target *target)
{
int retval;
retval = target_write_u32(target, WDG_LCK, 0x1ACCE551);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, WDG_LCK, 0xE5331AAE);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, WDG_CTL, 0);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
/**
* Initialize the ECC controller on the AT91SAM9.
*
* @param target Target to configure ECC on.
* @param info NAND controller information for where the ECC is.
* @return Success or failure of initialization.
*/
static int at91sam9_ecc_init(struct target *target, struct at91sam9_nand *info)
{
if (!info->ecc) {
LOG_ERROR("ECC controller address must be set when not reading raw NAND data");
return ERROR_NAND_OPERATION_FAILED;
}
/* reset ECC parity registers */
return target_write_u32(target, info->ecc + AT91C_ECCx_CR, 1);
}
static int s3c2410_init(struct nand_device *nand)
{
struct target *target = nand->target;
target_write_u32(target, S3C2410_NFCONF,
S3C2410_NFCONF_EN | S3C2410_NFCONF_TACLS(3) |
S3C2410_NFCONF_TWRPH0(5) | S3C2410_NFCONF_TWRPH1(3));
return ERROR_OK;
}
static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
{
struct target *target = bank->target;
int retval;
uint32_t reg32;
/*
* To erase a sector (i.e. FLASH_PAGES_PER_SECTOR pages),
* first unlock the memory, loop over the pages of this sector
* and write 0x0 to its first word.
*/
retval = stm32lx_unlock_program_memory(bank);
if (retval != ERROR_OK)
return retval;
for (int page = 0; page < FLASH_PAGES_PER_SECTOR; page++) {
reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
retval = target_write_u32(target, FLASH_PECR, reg32);
if (retval != ERROR_OK)
return retval;
retval = stm32lx_wait_until_bsy_clear(bank);
if (retval != ERROR_OK)
return retval;
uint32_t addr = bank->base + bank->sectors[sector].offset + (page
* FLASH_PAGE_SIZE);
retval = target_write_u32(target, addr, 0x0);
if (retval != ERROR_OK)
return retval;
retval = stm32lx_wait_until_bsy_clear(bank);
if (retval != ERROR_OK)
return retval;
}
retval = stm32lx_lock_program_memory(bank);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
