static bool _tegra_dc_enable(struct tegra_dc *dc)
{
if (dc->mode.pclk == 0)
return false;
tegra_dc_io_start(dc);
if (dc->out && dc->out->enable)
dc->out->enable();
tegra_dc_setup_clk(dc, dc->clk);
clk_enable(dc->clk);
clk_enable(dc->emc_clk);
tegra_periph_reset_deassert(dc->clk);
msleep(10);
enable_irq(dc->irq);
tegra_dc_init(dc);
if (dc->out_ops && dc->out_ops->enable)
dc->out_ops->enable(dc);
/* force a full blending update */
dc->blend.z[0] = -1;
tegra_dc_ext_enable(dc->ext);
return true;
}
static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
{
bool ret = true;
if (dc->out->enable)
dc->out->enable();
tegra_dc_setup_clk(dc, dc->clk);
tegra_dc_clk_enable(dc);
if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
mutex_lock(&tegra_dcs[1]->lock);
disable_irq(tegra_dcs[1]->irq);
} else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
mutex_lock(&tegra_dcs[0]->lock);
disable_irq(tegra_dcs[0]->irq);
}
msleep(5);
tegra_periph_reset_assert(dc->clk);
msleep(2);
#ifdef CONFIG_TEGRA_SILICON_PLATFORM
tegra_periph_reset_deassert(dc->clk);
msleep(1);
#endif
if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
enable_dc_irq(tegra_dcs[1]->irq);
mutex_unlock(&tegra_dcs[1]->lock);
} else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
enable_dc_irq(tegra_dcs[0]->irq);
mutex_unlock(&tegra_dcs[0]->lock);
}
enable_dc_irq(dc->irq);
if (tegra_dc_init(dc)) {
dev_err(&dc->ndev->dev, "cannot initialize\n");
ret = false;
}
if (dc->out_ops && dc->out_ops->enable)
dc->out_ops->enable(dc);
if (dc->out->postpoweron)
dc->out->postpoweron();
/* force a full blending update */
dc->blend.z[0] = -1;
tegra_dc_ext_enable(dc->ext);
if (!ret) {
dev_err(&dc->ndev->dev, "initialization failed,disabling");
_tegra_dc_controller_disable(dc);
}
trace_printk("%s:reset enable\n", dc->ndev->name);
return ret;
}
static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
{
int failed_init = 0;
if (dc->out->enable)
dc->out->enable();
tegra_dc_setup_clk(dc, dc->clk);
tegra_dc_clk_enable(dc);
/* do not accept interrupts during initialization */
tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
enable_dc_irq(dc->irq);
failed_init = tegra_dc_init(dc);
if (failed_init) {
tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
disable_irq(dc->irq);
tegra_dc_clear_bandwidth(dc);
tegra_dc_clk_disable(dc);
if (dc->out && dc->out->disable)
dc->out->disable();
return false;
}
if (dc->out_ops && dc->out_ops->enable)
dc->out_ops->enable(dc);
/* force a full blending update */
dc->blend.z[0] = -1;
tegra_dc_ext_enable(dc->ext);
trace_printk("%s:enable\n", dc->ndev->name);
tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
if (dc->out->postpoweron)
dc->out->postpoweron();
return true;
}
static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
struct tegra_dc_dsi_data *dsi, u32 clk)
{
u32 rm;
rm = clk % 1000;
if (rm != 0)
clk -= rm;
clk *= 2; /* Value for PLLD routine is required to be twice as */
/* the desired clock rate */
dc->mode.pclk = clk*1000;
tegra_dc_setup_clk(dc, dsi->dsi_clk);
clk_enable(dsi->dsi_clk);
tegra_periph_reset_deassert(dsi->dsi_clk);
dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
dsi->current_bit_clk_ns = 1000*1000 / (dsi->current_dsi_clk_khz * 2);
}
