int kai_emc_init(void)
{
int hw_ramcode;
int board_strap = nabijr_get_board_strap();
hw_ramcode = tegra_get_hw_ramcode();
printk("hardware ramcode is %d\n", hw_ramcode);
printk("board_strap is %d\n", board_strap);
switch (hw_ramcode) {
case 0: /* ELPIDA */
tegra_init_emc(nabi_emc_tables_Elpida_1GB_EDJ4216EBBG_DJ_F_ddr3,
ARRAY_SIZE(nabi_emc_tables_Elpida_1GB_EDJ4216EBBG_DJ_F_ddr3));
break;
case 1: /* HYNIX */
tegra_init_emc(nabi_emc_tables_Hynix_1GB_H5TC4G63MFR_H9A_ddr3,
ARRAY_SIZE(nabi_emc_tables_Hynix_1GB_H5TC4G63MFR_H9A_ddr3));
break;
case 2: /* SAMSUNG */
default:
tegra_init_emc(nabi_emc_tables_Samsung_1GB_K4B4G1646B_HYK0_ddr3,
ARRAY_SIZE(nabi_emc_tables_Samsung_1GB_K4B4G1646B_HYK0_ddr3));
break;
case 3: /* MICRON */
tegra_init_emc(nabi_emc_tables_Micron_1GB_MT41K256M16HA_125E_ddr3,
ARRAY_SIZE(nabi_emc_tables_Micron_1GB_MT41K256M16HA_125E_ddr3));
break;
}
return 0;
}
int kai_emc_init(void)
{
tegra_init_emc(kai_emc_tables_h5tc4g,
ARRAY_SIZE(kai_emc_tables_h5tc4g));
return 0;
}
int tf101_emc_init(void)
{
/* TODO: detect */
tegra_init_emc(tf101_elpida_emc_chips, ARRAY_SIZE(tf101_elpida_emc_chips));
return 0;
}
int enrc2b_emc_init(void)
{
tegra_init_emc(enrc2b_emc_tables_h5tc2g_evt_533,
ARRAY_SIZE(enrc2b_emc_tables_h5tc2g_evt_533));
return 0;
}
int p3_emc_init(void)
{
/* Init P3 emc table. */
tegra_init_emc(p4_emc_chips,
ARRAY_SIZE(p4_emc_chips));
return 0;
}
int __init n1_emc_init(void)
{
tegra_init_emc(n1_emc_tables_samsung,
ARRAY_SIZE(n1_emc_tables_samsung));
pr_info("%s+\n", __func__);
return 0;
}
int enrc2u_emc_init(void)
{
struct board_info board_info;
tegra_init_emc(enrc2u_emc_tables_h5tc2g_evt_533,
ARRAY_SIZE(enrc2u_emc_tables_h5tc2g_evt_533));
return 0;
}
int n1_emc_init(void)
{
/* EMC Table of n1 project */
tegra_init_emc(n1_emc_tables_samsung,
ARRAY_SIZE(n1_emc_tables_samsung));
pr_info("%s+\n", __func__);
return 0;
}
int enterprise_emc_init(void)
{
struct board_info board_info;
tegra_get_board_info(&board_info);
if (board_info.fab <= BOARD_FAB_A02)
tegra_init_emc(enterprise_emc_tables_h5tc2g,
ARRAY_SIZE(enterprise_emc_tables_h5tc2g));
return 0;
}
int acer_t20_emc_init(void)
{
switch (RAM_CODE) {
case 0:
tegra_init_emc(vangogh_emc_tables_elpida_8Gb_300Mhz, ARRAY_SIZE(vangogh_emc_tables_elpida_8Gb_300Mhz));
break;
case 1:
tegra_init_emc(vangogh_emc_tables_elpida_4Gb_300Mhz, ARRAY_SIZE(vangogh_emc_tables_elpida_4Gb_300Mhz));
break;
case 2:
tegra_init_emc(vangogh_emc_tables_Hynix_4Gb_300Mhz, ARRAY_SIZE(vangogh_emc_tables_Hynix_4Gb_300Mhz));
break;
case 3:
tegra_init_emc(vangogh_emc_tables_Hynix_8Gb_300Mhz, ARRAY_SIZE(vangogh_emc_tables_Hynix_8Gb_300Mhz));
break;
default:
tegra_init_emc(vangogh_emc_tables_elpida_4Gb_300Mhz, ARRAY_SIZE(vangogh_emc_tables_elpida_4Gb_300Mhz));
}
return 0;
}
int antares_emc_init(void)
{
u32 reg;
int ram_id;
void __iomem *apb_misc = IO_ADDRESS(TEGRA_APB_MISC_BASE);
const struct tegra_emc_table *emc_tables;
int emc_tables_size;
bool is_normal;
reg = readl(apb_misc + STRAP_OPT);
ram_id = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
printk("[MEMORY] %s, ram_id = %d\n", __func__, ram_id);
switch (ram_id) {
default:
case 0:
pr_info("%s: ram: Elpida_EDB8132B1PB_6D_F_300Mhz\n", __func__);
emc_tables = antares_emc_tables_Elpida_EDB8132B1PB_6D_F_300Mhz;
emc_tables_size = ARRAY_SIZE(antares_emc_tables_Elpida_EDB8132B1PB_6D_F_300Mhz);
break;
case 1:
pr_info("%s: ram: Elpida_EDB8132B2PB_6D_F_300Mhz\n", __func__);
emc_tables = antares_emc_tables_Elpida_EDB8132B2PB_6D_F_300Mhz;
emc_tables_size = ARRAY_SIZE(antares_emc_tables_Elpida_EDB8132B2PB_6D_F_300Mhz);
break;
case 2:
pr_info("%s: ram: Hynix_H8TJR00X0MLR_0YM_300Mhz!\n", __func__);
antares_guery_ram_normal_mode(&is_normal);
if (!is_normal) {
pr_info("Apply Hynix memory patch\n");
tegra_emc_write_mrw(9);
}
/* set Elpida as default */
emc_tables = antares_emc_tables_Hynix_H8TJR00X0MLR_0YM_300Mhz;
emc_tables_size = ARRAY_SIZE(antares_emc_tables_Hynix_H8TJR00X0MLR_0YM_300Mhz);
break;
}
tegra_init_emc(emc_tables, emc_tables_size);
return 0;
}
void __init smba_init_emc(void)
{
tegra_init_emc(smba_emc_chips, ARRAY_SIZE(smba_emc_chips));
}
void olympus_emc_init(void)
{
printk(KERN_INFO "pICS_%s",__func__);
tegra_init_emc(olympus_emc_chips, ARRAY_SIZE(olympus_emc_chips));
}
int enterprise_emc_init(void)
{
tegra_init_emc(enterprise_emc_tables_h5tc2g,
ARRAY_SIZE(enterprise_emc_tables_h5tc2g));
return 0;
}