static int tegra_bt_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(rtd->cpu_dai);
#endif
struct snd_soc_card *card = rtd->card;
struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
int err, srate, mclk, min_mclk, sample_size;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
sample_size = 16;
break;
default:
return -EINVAL;
}
srate = params_rate(params);
switch (srate) {
case 11025:
case 22050:
case 44100:
case 88200:
mclk = 11289600;
break;
case 8000:
case 16000:
case 32000:
case 48000:
case 64000:
case 96000:
mclk = 12288000;
break;
default:
return -EINVAL;
}
min_mclk = 64 * srate;
err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
if (err < 0) {
if (!(machine->util_data.set_mclk % min_mclk))
mclk = machine->util_data.set_mclk;
else {
dev_err(card->dev, "Can't configure clocks\n");
return err;
}
}
tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
err = snd_soc_dai_set_fmt(rtd->cpu_dai,
SND_SOC_DAIFMT_DSP_A |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS);
if (err < 0) {
dev_err(rtd->codec->card->dev, "cpu_dai fmt not set\n");
return err;
}
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tegra_max98088_set_dam_cif(i2s->dam_ifc, params_rate(params),
params_channels(params), sample_size, 0, 0, 0, 0);
#endif
return 0;
}
static int tegra_max98088_startup(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
struct tegra_max98088 *machine = snd_soc_card_get_drvdata(rtd->card);
struct codec_config *codec_info;
struct codec_config *bb_info;
int codec_index;
if (!i2s->is_dam_used)
return 0;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/*dam configuration*/
if (!i2s->dam_ch_refcount)
i2s->dam_ifc = tegra30_dam_allocate_controller();
tegra30_dam_allocate_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN1);
i2s->dam_ch_refcount++;
tegra30_dam_enable_clock(i2s->dam_ifc);
tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
(i2s->dam_ifc*2), i2s->txcif);
/*
*make the dam tx to i2s rx connection if this is the only client
*using i2s for playback
*/
if (i2s->playback_ref_count == 1)
tegra30_ahub_set_rx_cif_source(
TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id,
TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->dam_ifc);
/* enable the dam*/
tegra30_dam_enable(i2s->dam_ifc, TEGRA30_DAM_ENABLE,
TEGRA30_DAM_CHIN1);
} else {
i2s->is_call_mode_rec = machine->is_call_mode;
if (!i2s->is_call_mode_rec)
return 0;
if (machine->is_device_bt)
codec_index = BT_SCO;
else
codec_index = HIFI_CODEC;
codec_info = &machine->codec_info[codec_index];
bb_info = &machine->codec_info[BASEBAND];
/* allocate a dam for voice call recording */
i2s->call_record_dam_ifc = tegra30_dam_allocate_controller();
tegra30_dam_allocate_channel(i2s->call_record_dam_ifc,
TEGRA30_DAM_CHIN0_SRC);
tegra30_dam_allocate_channel(i2s->call_record_dam_ifc,
TEGRA30_DAM_CHIN1);
tegra30_dam_enable_clock(i2s->call_record_dam_ifc);
/* configure the dam */
tegra_max98088_set_dam_cif(i2s->call_record_dam_ifc,
codec_info->rate, codec_info->channels,
codec_info->bitsize, 1, bb_info->rate,
bb_info->channels, bb_info->bitsize);
/* setup the connections for voice call record */
tegra30_ahub_unset_rx_cif_source(i2s->rxcif);
tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
(i2s->call_record_dam_ifc*2),
TEGRA30_AHUB_TXCIF_I2S0_TX0 + bb_info->i2s_id);
tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
(i2s->call_record_dam_ifc*2),
TEGRA30_AHUB_TXCIF_I2S0_TX0 + codec_info->i2s_id);
tegra30_ahub_set_rx_cif_source(i2s->rxcif,
TEGRA30_AHUB_TXCIF_DAM0_TX0 + i2s->call_record_dam_ifc);
/* enable the dam*/
tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_ENABLE,
TEGRA30_DAM_CHIN1);
tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_ENABLE,
TEGRA30_DAM_CHIN0_SRC);
}
return 0;
}
static int tegra_max98088_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
struct snd_soc_codec *codec = rtd->codec;
struct snd_soc_card *card = codec->card;
struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card);
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
#endif
int srate, mclk, sample_size, i2s_daifmt;
int err;
struct clk *clk;
int rate;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
sample_size = 16;
break;
default:
return -EINVAL;
}
srate = params_rate(params);
switch (srate) {
case 8000:
case 16000:
case 24000:
case 32000:
case 48000:
case 64000:
case 96000:
mclk = 12288000;
break;
case 11025:
case 22050:
case 44100:
case 88200:
mclk = 11289600;
break;
default:
mclk = 12000000;
break;
}
#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
clk = clk_get_sys(NULL, "cdev1");
#else
clk = clk_get_sys("extern1", NULL);
#endif
if (IS_ERR(clk)) {
dev_err(card->dev, "Can't retrieve clk cdev1\n");
err = PTR_ERR(clk);
return err;
}
rate = clk_get_rate(clk);
printk("extern1 rate=%d\n",rate);
#if TEGRA30_I2S_MASTER_PLAYBACK
i2s_daifmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS;
#else
i2s_daifmt = SND_SOC_DAIFMT_I2S |
SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM;
mclk = rate;
#endif
err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk);
if (err < 0) {
if (!(machine->util_data.set_mclk % mclk))
mclk = machine->util_data.set_mclk;
else {
dev_err(card->dev, "Can't configure clocks\n");
return err;
}
}
tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1);
err = snd_soc_dai_set_fmt(codec_dai,i2s_daifmt);
if (err < 0) {
dev_err(card->dev, "codec_dai fmt not set\n");
return err;
}
err = snd_soc_dai_set_fmt(cpu_dai, i2s_daifmt);
if (err < 0) {
dev_err(card->dev, "cpu_dai fmt not set\n");
return err;
}
err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
SND_SOC_CLOCK_IN);
if (err < 0) {
dev_err(card->dev, "codec_dai clock not set\n");
return err;
}
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
tegra_max98088_set_dam_cif(i2s->dam_ifc, srate,
params_channels(params), sample_size, 0, 0, 0, 0);
#endif
return 0;
}
