/* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { debug("board_mmc_init called\n"); /* Enable muxes, etc. for SDMMC controllers */ pin_mux_mmc(); /* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */ tegra_mmc_init(0, 4, -1, GPIO_PP1); /* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */ tegra_mmc_init(3, 4, -1, -1); return 0; }
/* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { debug("board_mmc_init called\n"); /* Enable muxes, etc. for SDMMC controllers */ pin_mux_mmc(); debug("board_mmc_init: init eMMC\n"); /* init dev 0, eMMC chip, with 8-bit bus */ tegra_mmc_init(0, 8, -1, -1); debug("board_mmc_init: init SD slot\n"); /* init dev 3, SD slot, with 4-bit bus */ tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); return 0; }
/* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { debug("board_mmc_init called\n"); /* Enable muxes, etc. for SDMMC controllers */ pin_mux_mmc(); debug("board_mmc_init: init eMMC\n"); /* init dev 0, eMMC chip, with 4-bit bus */ /* The board has an 8-bit bus, but 8-bit doesn't work yet */ tegra_mmc_init(0, 4, -1, -1); debug("board_mmc_init: init SD slot\n"); /* init dev 1, SD slot, with 4-bit bus */ tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5); return 0; }
/* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { debug("board_mmc_init called\n"); /* Enable muxes, etc. for SDMMC controllers */ pin_mux_mmc(); debug("board_mmc_init: init SD slot J26\n"); /* init dev 0, SD slot J26, with 4-bit bus */ /* The board has an 8-bit bus, but 8-bit doesn't work yet */ tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); debug("board_mmc_init: init SD slot J5\n"); /* init dev 2, SD slot J5, with 4-bit bus */ tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5); return 0; }
/* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { debug("%s called\n", __func__); /* Enable muxes, etc. for SDMMC controllers */ pin_mux_mmc(); debug("%s: init MMC\n", __func__); tegra_mmc_init(); return 0; }
int board_mmc_init(bd_t *bd) { tegra_mmc_init(); return 0; }
static int tegra_mmc_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct tegra_mmc_plat *plat = dev_get_platdata(dev); struct tegra_mmc_priv *priv = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; int bus_width, ret; cfg->name = dev->name; bus_width = dev_read_u32_default(dev, "bus-width", 1); cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; cfg->host_caps = 0; if (bus_width == 8) cfg->host_caps |= MMC_MODE_8BIT; if (bus_width >= 4) cfg->host_caps |= MMC_MODE_4BIT; cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; /* * min freq is for card identification, and is the highest * low-speed SDIO card frequency (actually 400KHz) * max freq is highest HS eMMC clock as per the SD/MMC spec * (actually 52MHz) */ cfg->f_min = 375000; cfg->f_max = 48000000; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; priv->reg = (void *)dev_read_addr(dev); ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl); if (ret) { debug("reset_get_by_name() failed: %d\n", ret); return ret; } ret = clk_get_by_index(dev, 0, &priv->clk); if (ret) { debug("clk_get_by_index() failed: %d\n", ret); return ret; } ret = reset_assert(&priv->reset_ctl); if (ret) return ret; ret = clk_enable(&priv->clk); if (ret) return ret; ret = clk_set_rate(&priv->clk, 20000000); if (IS_ERR_VALUE(ret)) return ret; ret = reset_deassert(&priv->reset_ctl); if (ret) return ret; /* These GPIOs are optional */ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio, GPIOD_IS_OUT); if (dm_gpio_is_valid(&priv->pwr_gpio)) dm_gpio_set_value(&priv->pwr_gpio, 1); upriv->mmc = &plat->mmc; return tegra_mmc_init(dev); }