static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
unsigned status;
unsigned long sl_irq_flags;
int ret;
spin_lock_irqsave(&tegra_rtc_lock, sl_irq_flags);
if(tegra_rtc_check_busy()) { /* wait for the busy bit to clear. */
spin_unlock_irqrestore(&tegra_rtc_lock, sl_irq_flags);
ret = tegra_rtc_wait_while_busy(dev);
if (ret)
return ret;
spin_lock_irqsave(&tegra_rtc_lock, sl_irq_flags);
}
/* read the original value, and OR in the flag. */
status = tegra_rtc_read(RTC_TEGRA_REG_INTR_MASK);
if (enabled)
status |= RTC_TEGRA_INTR_MASK_SEC_ALARM0; /* set it */
else
status &= ~RTC_TEGRA_INTR_MASK_SEC_ALARM0; /* clear it */
tegra_rtc_write(RTC_TEGRA_REG_INTR_MASK, status);
spin_unlock_irqrestore(&tegra_rtc_lock, sl_irq_flags);
return 0;
}
/* wait for hardware to be ready for writing.
* do not call this inside the spin lock because it sleeps.
*/
static int tegra_rtc_wait_while_busy(struct device *dev)
{
/* TODO: wait for busy then not busy to catch a leading edge. */
int retries = RTC_TEGRA_RETRIES;
while (tegra_rtc_check_busy()) {
if (!retries--) {
dev_err(dev, "write failed:retry count exceeded.\n");
return -ETIMEDOUT;
}
msleep(1);
}
return 0;
}
/* waits for the RTC to not be busy accessing APB, then write a single value. */
static int tegra_rtc_write_not_busy(struct device *dev, unsigned ofs, u32 value)
{
unsigned long sl_irq_flags;
int ret;
spin_lock_irqsave(&tegra_rtc_lock, sl_irq_flags);
if(tegra_rtc_check_busy()) {
spin_unlock_irqrestore(&tegra_rtc_lock, sl_irq_flags);
ret = tegra_rtc_wait_while_busy(dev);
if (ret)
return ret;
spin_lock_irqsave(&tegra_rtc_lock, sl_irq_flags);
}
tegra_rtc_write(ofs, value);
spin_unlock_irqrestore(&tegra_rtc_lock, sl_irq_flags);
return 0;
}
/* Wait for hardware to be ready for writing.
* This function tries to maximize the amount of time before the next update.
* It does this by waiting for the RTC to become busy with its periodic update,
* then returning once the RTC first becomes not busy.
* This periodic update (where the seconds and milliseconds are copied to the
* AHB side) occurs every eight 32kHz clocks (~250uS).
* The behavior of this function allows us to make some assumptions without
* introducing a race, because 250uS is plenty of time to read/write a value.
*/
static int tegra_rtc_wait_while_busy(void)
{
int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
/* first wait for the RTC to become busy. this is when it
* posts its updated seconds+msec registers to AHB side. */
while (tegra_rtc_check_busy()) {
if (!retries--)
goto retry_failed;
udelay(1);
}
/* now we have about 250 us to manipulate registers */
return 0;
retry_failed:
pr_err("RTC: write failed:retry count exceeded.\n");
return -ETIMEDOUT;
}
/* Wait for hardware to be ready for writing.
* This function tries to maximize the amount of time before the next update.
* It does this by waiting for the RTC to become busy with its periodic update,
* then returning once the RTC first becomes not busy.
* This periodic update (where the seconds and milliseconds are copied to the
* AHB side) occurs every eight 32kHz clocks (~250uS).
* The behavior of this function allows us to make some assumptions without
* introducing a race, because 250uS is plenty of time to read/write a value.
*/
static int tegra_rtc_wait_while_busy(struct device *dev)
{
struct tegra_rtc_info *info = dev_get_drvdata(dev);
int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
/* first wait for the RTC to become busy. this is when it
* posts its updated seconds+msec registers to AHB side. */
while (tegra_rtc_check_busy(info)) {
if (!retries--)
goto retry_failed;
udelay(1);
}
/* now we have about 250 us to manipulate registers */
return 0;
retry_failed:
dev_err(dev, "write failed:retry count exceeded.\n");
return -ETIMEDOUT;
}
