void timer_handler(int sig, union uml_pt_regs *regs)
{
local_irq_disable();
irq_enter();
update_process_times(CHOOSE_MODE(
(UPT_SC(regs) && user_context(UPT_SP(regs))),
(regs)->skas.is_user));
irq_exit();
local_irq_enable();
if(current_thread->cpu == 0)
timer_irq(regs);
}
void lk_scheduler(void)
{
static enum handler_return ret;
mt_irq_ack(MT6575_GPT_IRQ_ID);
DRV_WriteReg32( GPT_IRQACK_REG, 0x10);
ret = timer_irq(0);
if(ret == INT_RESCHEDULE) {
thread_preempt();
}
DRV_WriteReg32(GPT5_CON_REG, GPT_CLEAR);
DRV_WriteReg32(GPT5_CON_REG, GPT_ENABLE|GPT_MODE4_ONE_SHOT);
}
enum handler_return lk_scheduler(void)
{
static enum handler_return ret;
/* ack GPT5 irq */
DRV_WriteReg32(GPT_IRQACK_REG, 0x10);
DRV_WriteReg32(GPT5_CON_REG, GPT_CLEAR);
DRV_WriteReg32(GPT5_CON_REG, GPT_DISABLE);
ret = timer_irq(0);
/* ack GIC irq */
mt_irq_ack(MT_GPT_IRQ_ID);
/* enable GPT5 */
DRV_WriteReg32(GPT5_CON_REG, GPT_ENABLE|GPT_MODE4_ONE_SHOT);
return ret;
}
void lk_scheduler(void)
{
//static enum handler_return ret;
/* ack GPT5 irq */
DRV_WriteReg32(GPT_IRQACK_REG, 0x10);
DRV_WriteReg32(GPT5_CON_REG, GPT_CLEAR);
DRV_WriteReg32(GPT5_CON_REG, GPT_DISABLE);
timer_irq(0);
/*
* CAUTION! The de-assert signal to GIC might delay serveral clocks.
* Here must have enough delay to make sure the GPT signal had arrived GIC.
*/
/* ack GIC irq */
mt_irq_ack(MT_GPT_IRQ_ID);
/* enable GPT5 */
DRV_WriteReg32(GPT5_CON_REG, GPT_ENABLE|GPT_MODE4_ONE_SHOT);
}
void fddi_isr(struct s_smc *smc)
{
u_long is ; /* ISR source */
u_short stu, stl ;
SMbuf *mb ;
#ifdef USE_BREAK_ISR
int force_irq ;
#endif
#ifdef ODI2
if (smc->os.hwm.rx_break) {
mac_drv_fill_rxd(smc) ;
if (smc->hw.fp.rx_q[QUEUE_R1].rx_used > 0) {
smc->os.hwm.rx_break = 0 ;
process_receive(smc) ;
}
else {
smc->os.hwm.detec_count = 0 ;
smt_force_irq(smc) ;
}
}
#endif
smc->os.hwm.isr_flag = TRUE ;
#ifdef USE_BREAK_ISR
force_irq = TRUE ;
if (smc->os.hwm.leave_isr) {
smc->os.hwm.leave_isr = FALSE ;
process_receive(smc) ;
}
#endif
while ((is = GET_ISR() & ISR_MASK)) {
NDD_TRACE("CH0B",is,0,0) ;
DB_GEN("ISA = 0x%x",is,0,7) ;
if (is & IMASK_SLOW) {
NDD_TRACE("CH1b",is,0,0) ;
if (is & IS_PLINT1) { /* PLC1 */
plc1_irq(smc) ;
}
if (is & IS_PLINT2) { /* PLC2 */
plc2_irq(smc) ;
}
if (is & IS_MINTR1) { /* FORMAC+ STU1(U/L) */
stu = inpw(FM_A(FM_ST1U)) ;
stl = inpw(FM_A(FM_ST1L)) ;
DB_GEN("Slow transmit complete",0,0,6) ;
mac1_irq(smc,stu,stl) ;
}
if (is & IS_MINTR2) { /* FORMAC+ STU2(U/L) */
stu= inpw(FM_A(FM_ST2U)) ;
stl= inpw(FM_A(FM_ST2L)) ;
DB_GEN("Slow receive complete",0,0,6) ;
DB_GEN("stl = %x : stu = %x",stl,stu,7) ;
mac2_irq(smc,stu,stl) ;
}
if (is & IS_MINTR3) { /* FORMAC+ STU3(U/L) */
stu= inpw(FM_A(FM_ST3U)) ;
stl= inpw(FM_A(FM_ST3L)) ;
DB_GEN("FORMAC Mode Register 3",0,0,6) ;
mac3_irq(smc,stu,stl) ;
}
if (is & IS_TIMINT) { /* Timer 82C54-2 */
timer_irq(smc) ;
#ifdef NDIS_OS2
force_irq_pending = 0 ;
#endif
/*
* out of RxD detection
*/
if (++smc->os.hwm.detec_count > 4) {
/*
* check out of RxD condition
*/
process_receive(smc) ;
}
}
if (is & IS_TOKEN) { /* Restricted Token Monitor */
rtm_irq(smc) ;
}
if (is & IS_R1_P) { /* Parity error rx queue 1 */
/* clear IRQ */
outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_P) ;
SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ;
}
if (is & IS_R1_C) { /* Encoding error rx queue 1 */
/* clear IRQ */
outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_C) ;
SMT_PANIC(smc,HWM_E0005,HWM_E0005_MSG) ;
}
if (is & IS_XA_C) { /* Encoding error async tx q */
/* clear IRQ */
outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_C) ;
SMT_PANIC(smc,HWM_E0006,HWM_E0006_MSG) ;
}
if (is & IS_XS_C) { /* Encoding error sync tx q */
/* clear IRQ */
outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_C) ;
SMT_PANIC(smc,HWM_E0007,HWM_E0007_MSG) ;
}
}
/*
* Fast Tx complete Async/Sync Queue (BMU service)
*/
if (is & (IS_XS_F|IS_XA_F)) {
DB_GEN("Fast tx complete queue",0,0,6) ;
/*
* clear IRQ, Note: no IRQ is lost, because
* we always service both queues
*/
outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_F) ;
outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_F) ;
mac_drv_clear_txd(smc) ;
llc_restart_tx(smc) ;
}
/*
* Fast Rx Complete (BMU service)
*/
if (is & IS_R1_F) {
DB_GEN("Fast receive complete",0,0,6) ;
/* clear IRQ */
#ifndef USE_BREAK_ISR
outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
process_receive(smc) ;
#else
process_receive(smc) ;
if (smc->os.hwm.leave_isr) {
force_irq = FALSE ;
} else {
outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
process_receive(smc) ;
}
#endif
}
#ifndef NDIS_OS2
while ((mb = get_llc_rx(smc))) {
smt_to_llc(smc,mb) ;
}
#else
if (offDepth)
post_proc() ;
while (!offDepth && (mb = get_llc_rx(smc))) {
smt_to_llc(smc,mb) ;
}
if (!offDepth && smc->os.hwm.rx_break) {
process_receive(smc) ;
}
#endif
if (smc->q.ev_get != smc->q.ev_put) {
NDD_TRACE("CH2a",0,0,0) ;
ev_dispatcher(smc) ;
}
#ifdef NDIS_OS2
post_proc() ;
if (offDepth) { /* leave fddi_isr because */
break ; /* indications not allowed */
}
#endif
#ifdef USE_BREAK_ISR
if (smc->os.hwm.leave_isr) {
break ; /* leave fddi_isr */
}
#endif
/* NOTE: when the isr is left, no rx is pending */
} /* end of interrupt source polling loop */
#ifdef USE_BREAK_ISR
if (smc->os.hwm.leave_isr && force_irq) {
smt_force_irq(smc) ;
}
#endif
smc->os.hwm.isr_flag = FALSE ;
NDD_TRACE("CH0E",0,0,0) ;
}
int sc_main(int, char **) {
MBWrapper cpu("MBWrapper");
Memory inst_ram("inst_ram", INST_RAM_SIZE);
// Memory data_ram("data_ram", SRAM_SIZE);
Bus bus("bus");
TIMER timer("timer", sc_core::sc_time(20, sc_core::SC_NS));
Vga vga("vga");
Intc intc("intc");
Gpio gpio("gpio");
sc_core::sc_signal<bool> timer_irq("timer_irq");
sc_core::sc_signal<bool> vga_irq("vga_irq");
sc_core::sc_signal<bool> cpu_irq("cpu_irq");
// Load the program in RAM
soclib::common::Loader::register_loader("elf",
soclib::common::elf_load);
try {
soclib::common::Loader loader("../software/cross/a.out");
loader.load(inst_ram.storage, 0, SOFT_SIZE);
for (int i = 0; i < SOFT_SIZE / 4; i++) {
inst_ram.storage[i] =
uint32_be_to_machine(inst_ram.storage[i]);
}
} catch (soclib::exception::RunTimeError e) {
std::cerr << "unable to load ELF file in memory:" << std::endl;
std::cerr << e.what() << std::endl;
abort();
}
// initiators
cpu.socket.bind(bus.target);
vga.initiator(bus.target);
// targets
// bus.initiator(data_ram.target);
bus.initiator(inst_ram.target);
bus.initiator(vga.target);
bus.initiator(timer.target);
bus.initiator(gpio.target);
bus.initiator(intc.target);
// interrupts
vga.irq(vga_irq);
timer.irq(timer_irq);
intc.in0(vga_irq);
intc.in1(timer_irq);
intc.out(cpu_irq);
cpu.irq(cpu_irq);
// port start addr size
bus.map(inst_ram.target, INST_RAM_BASEADDR, INST_RAM_SIZE);
// bus.map(data_ram.target, SRAM_BASEADDR, SRAM_SIZE);
bus.map(vga.target, VGA_BASEADDR, VGA_SIZE);
bus.map(gpio.target, GPIO_BASEADDR, GPIO_SIZE);
bus.map(timer.target, TIMER_BASEADDR, TIMER_SIZE);
bus.map(intc.target, INTC_BASEADDR, INTC_SIZE);
// start the simulation
sc_core::sc_start();
return 0;
}
